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15#include <common.h>
16#include <cpu_func.h>
17#include <dm.h>
18#include <log.h>
19#include <net.h>
20#include <netdev.h>
21#include <config.h>
22#include <malloc.h>
23#include <asm/cache.h>
24#include <asm/global_data.h>
25#include <asm/io.h>
26#include <dm/device_compat.h>
27#include <dm/devres.h>
28#include <linux/bitops.h>
29#include <linux/bug.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <phy.h>
33#include <miiphy.h>
34#include <watchdog.h>
35#include <asm/arch/cpu.h>
36#include <asm/arch/soc.h>
37#include <linux/compat.h>
38#include <linux/mbus.h>
39#include <asm-generic/gpio.h>
40
41DECLARE_GLOBAL_DATA_PTR;
42
43#if !defined(CONFIG_PHYLIB)
44# error Marvell mvneta requires PHYLIB
45#endif
46
47#define CONFIG_NR_CPUS 1
48#define ETH_HLEN 14
49
50
51#define WRAP (2 + ETH_HLEN + 4 + 32)
52#define MTU 1500
53#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
54
55#define MVNETA_SMI_TIMEOUT 10000
56
57
58#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
59#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
60#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
61#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
62#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
63#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
64#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
65#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
66#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
67#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
68#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
69#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
70#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
71#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
72#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
73#define MVNETA_PORT_RX_RESET 0x1cc0
74#define MVNETA_PORT_RX_DMA_RESET BIT(0)
75#define MVNETA_PHY_ADDR 0x2000
76#define MVNETA_PHY_ADDR_MASK 0x1f
77#define MVNETA_SMI 0x2004
78#define MVNETA_PHY_REG_MASK 0x1f
79
80#define MVNETA_SMI_DATA_OFFS 0
81#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
82#define MVNETA_SMI_DEV_ADDR_OFFS 16
83#define MVNETA_SMI_REG_ADDR_OFFS 21
84#define MVNETA_SMI_OPCODE_OFFS 26
85#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
86#define MVNETA_SMI_READ_VALID (1 << 27)
87#define MVNETA_SMI_BUSY (1 << 28)
88#define MVNETA_MBUS_RETRY 0x2010
89#define MVNETA_UNIT_INTR_CAUSE 0x2080
90#define MVNETA_UNIT_CONTROL 0x20B0
91#define MVNETA_PHY_POLLING_ENABLE BIT(1)
92#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
93#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
94#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
95#define MVNETA_WIN_SIZE_MASK (0xffff0000)
96#define MVNETA_BASE_ADDR_ENABLE 0x2290
97#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
98#define MVNETA_PORT_ACCESS_PROTECT 0x2294
99#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
100#define MVNETA_PORT_CONFIG 0x2400
101#define MVNETA_UNI_PROMISC_MODE BIT(0)
102#define MVNETA_DEF_RXQ(q) ((q) << 1)
103#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
104#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
105#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
106#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
107#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
108#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
109#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
110 MVNETA_DEF_RXQ_ARP(q) | \
111 MVNETA_DEF_RXQ_TCP(q) | \
112 MVNETA_DEF_RXQ_UDP(q) | \
113 MVNETA_DEF_RXQ_BPDU(q) | \
114 MVNETA_TX_UNSET_ERR_SUM | \
115 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
116#define MVNETA_PORT_CONFIG_EXTEND 0x2404
117#define MVNETA_MAC_ADDR_LOW 0x2414
118#define MVNETA_MAC_ADDR_HIGH 0x2418
119#define MVNETA_SDMA_CONFIG 0x241c
120#define MVNETA_SDMA_BRST_SIZE_16 4
121#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
122#define MVNETA_RX_NO_DATA_SWAP BIT(4)
123#define MVNETA_TX_NO_DATA_SWAP BIT(5)
124#define MVNETA_DESC_SWAP BIT(6)
125#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
126#define MVNETA_PORT_STATUS 0x2444
127#define MVNETA_TX_IN_PRGRS BIT(1)
128#define MVNETA_TX_FIFO_EMPTY BIT(8)
129#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
130#define MVNETA_SERDES_CFG 0x24A0
131#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
132#define MVNETA_QSGMII_SERDES_PROTO 0x0667
133#define MVNETA_TYPE_PRIO 0x24bc
134#define MVNETA_FORCE_UNI BIT(21)
135#define MVNETA_TXQ_CMD_1 0x24e4
136#define MVNETA_TXQ_CMD 0x2448
137#define MVNETA_TXQ_DISABLE_SHIFT 8
138#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
139#define MVNETA_ACC_MODE 0x2500
140#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
141#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
142#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
143#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
144
145
146
147#define MVNETA_INTR_NEW_CAUSE 0x25a0
148#define MVNETA_INTR_NEW_MASK 0x25a4
149
150
151
152
153
154
155
156
157#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
159#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
160#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
161
162#define MVNETA_INTR_OLD_CAUSE 0x25a8
163#define MVNETA_INTR_OLD_MASK 0x25ac
164
165
166#define MVNETA_INTR_MISC_CAUSE 0x25b0
167#define MVNETA_INTR_MISC_MASK 0x25b4
168#define MVNETA_INTR_ENABLE 0x25b8
169
170#define MVNETA_RXQ_CMD 0x2680
171#define MVNETA_RXQ_DISABLE_SHIFT 8
172#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
173#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
174#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
175#define MVNETA_GMAC_CTRL_0 0x2c00
176#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
177#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
178#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
179#define MVNETA_GMAC_CTRL_2 0x2c08
180#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
181#define MVNETA_GMAC2_PORT_RGMII BIT(4)
182#define MVNETA_GMAC2_PORT_RESET BIT(6)
183#define MVNETA_GMAC_STATUS 0x2c10
184#define MVNETA_GMAC_LINK_UP BIT(0)
185#define MVNETA_GMAC_SPEED_1000 BIT(1)
186#define MVNETA_GMAC_SPEED_100 BIT(2)
187#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
188#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
189#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
190#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
191#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
192#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
193#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
194#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
195#define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
196#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
197#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
198#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
199#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
200#define MVNETA_GMAC_SET_FC_EN BIT(8)
201#define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
202#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
203#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
204#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
205#define MVNETA_MIB_COUNTERS_BASE 0x3080
206#define MVNETA_MIB_LATE_COLLISION 0x7c
207#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
208#define MVNETA_DA_FILT_OTH_MCAST 0x3500
209#define MVNETA_DA_FILT_UCAST_BASE 0x3600
210#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
211#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
212#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
213#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
214#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
215#define MVNETA_TXQ_DEC_SENT_SHIFT 16
216#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
217#define MVNETA_TXQ_SENT_DESC_SHIFT 16
218#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
219#define MVNETA_PORT_TX_RESET 0x3cf0
220#define MVNETA_PORT_TX_DMA_RESET BIT(0)
221#define MVNETA_TX_MTU 0x3e0c
222#define MVNETA_TX_TOKEN_SIZE 0x3e14
223#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
224#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
225#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
226
227
228#define MVNETA_QUEUE_NEXT_DESC(q, index) \
229 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
230
231
232
233
234#define MVNETA_TXDONE_COAL_PKTS 16
235#define MVNETA_RX_COAL_PKTS 32
236#define MVNETA_RX_COAL_USEC 100
237
238
239
240
241
242
243
244
245
246#define MVNETA_MH_SIZE 2
247
248#define MVNETA_VLAN_TAG_LEN 4
249
250#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
251#define MVNETA_TX_CSUM_MAX_SIZE 9800
252#define MVNETA_ACC_MODE_EXT 1
253
254
255#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
256#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
257#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
258
259#define MVNETA_TX_MTU_MAX 0x3ffff
260
261
262#define MVNETA_MAX_RXD 16
263
264
265#define MVNETA_MAX_TXD 16
266
267
268#define MVNETA_DESC_ALIGNED_SIZE 32
269
270struct mvneta_port {
271 void __iomem *base;
272 struct mvneta_rx_queue *rxqs;
273 struct mvneta_tx_queue *txqs;
274
275 u8 mcast_count[256];
276 u16 tx_ring_size;
277 u16 rx_ring_size;
278
279 phy_interface_t phy_interface;
280 unsigned int link;
281 unsigned int duplex;
282 unsigned int speed;
283
284 int init;
285 int phyaddr;
286 struct phy_device *phydev;
287#if CONFIG_IS_ENABLED(DM_GPIO)
288 struct gpio_desc phy_reset_gpio;
289#endif
290 struct mii_dev *bus;
291};
292
293
294
295
296
297
298#define MVNETA_TX_L3_OFF_SHIFT 0
299#define MVNETA_TX_IP_HLEN_SHIFT 8
300#define MVNETA_TX_L4_UDP BIT(16)
301#define MVNETA_TX_L3_IP6 BIT(17)
302#define MVNETA_TXD_IP_CSUM BIT(18)
303#define MVNETA_TXD_Z_PAD BIT(19)
304#define MVNETA_TXD_L_DESC BIT(20)
305#define MVNETA_TXD_F_DESC BIT(21)
306#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
307 MVNETA_TXD_L_DESC | \
308 MVNETA_TXD_F_DESC)
309#define MVNETA_TX_L4_CSUM_FULL BIT(30)
310#define MVNETA_TX_L4_CSUM_NOT BIT(31)
311
312#define MVNETA_RXD_ERR_CRC 0x0
313#define MVNETA_RXD_ERR_SUMMARY BIT(16)
314#define MVNETA_RXD_ERR_OVERRUN BIT(17)
315#define MVNETA_RXD_ERR_LEN BIT(18)
316#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
317#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
318#define MVNETA_RXD_L3_IP4 BIT(25)
319#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
320#define MVNETA_RXD_L4_CSUM_OK BIT(30)
321
322struct mvneta_tx_desc {
323 u32 command;
324 u16 reserverd1;
325 u16 data_size;
326 u32 buf_phys_addr;
327 u32 reserved2;
328 u32 reserved3[4];
329};
330
331struct mvneta_rx_desc {
332 u32 status;
333 u16 reserved1;
334 u16 data_size;
335
336 u32 buf_phys_addr;
337 u32 reserved2;
338
339 u32 buf_cookie;
340 u16 reserved3;
341 u16 reserved4;
342
343 u32 reserved5;
344 u32 reserved6;
345};
346
347struct mvneta_tx_queue {
348
349 u8 id;
350
351
352 int size;
353
354
355 int txq_put_index;
356
357
358 int txq_get_index;
359
360
361 struct mvneta_tx_desc *descs;
362
363
364 dma_addr_t descs_phys;
365
366
367 int last_desc;
368
369
370 int next_desc_to_proc;
371};
372
373struct mvneta_rx_queue {
374
375 u8 id;
376
377
378 int size;
379
380
381 struct mvneta_rx_desc *descs;
382
383
384 dma_addr_t descs_phys;
385
386
387 int last_desc;
388
389
390 int next_desc_to_proc;
391};
392
393
394static int rxq_number = 1;
395static int txq_number = 1;
396static int rxq_def;
397
398struct buffer_location {
399 struct mvneta_tx_desc *tx_descs;
400 struct mvneta_rx_desc *rx_descs;
401 u32 rx_buffers;
402};
403
404
405
406
407
408static struct buffer_location buffer_loc;
409
410
411
412
413
414#define BD_SPACE (1 << 20)
415
416
417
418
419
420__weak int board_network_enable(struct mii_dev *bus)
421{
422 return 0;
423}
424
425
426
427
428static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
429{
430 writel(data, pp->base + offset);
431}
432
433
434static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
435{
436 return readl(pp->base + offset);
437}
438
439
440static void mvneta_mib_counters_clear(struct mvneta_port *pp)
441{
442 int i;
443
444
445 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
446 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
447}
448
449
450
451
452
453
454
455
456static int mvneta_rxq_desc_is_first_last(u32 status)
457{
458 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
459 MVNETA_RXD_FIRST_LAST_DESC;
460}
461
462
463static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
464 struct mvneta_rx_queue *rxq,
465 int ndescs)
466{
467
468
469
470 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
471 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
472 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
473 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
474 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
475 }
476
477 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
478 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
479}
480
481
482static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
483 struct mvneta_rx_queue *rxq)
484{
485 u32 val;
486
487 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
488 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
489}
490
491
492
493
494static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
495 struct mvneta_rx_queue *rxq,
496 int rx_done, int rx_filled)
497{
498 u32 val;
499
500 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
501 val = rx_done |
502 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
503 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
504 return;
505 }
506
507
508 while ((rx_done > 0) || (rx_filled > 0)) {
509 if (rx_done <= 0xff) {
510 val = rx_done;
511 rx_done = 0;
512 } else {
513 val = 0xff;
514 rx_done -= 0xff;
515 }
516 if (rx_filled <= 0xff) {
517 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
518 rx_filled = 0;
519 } else {
520 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
521 rx_filled -= 0xff;
522 }
523 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
524 }
525}
526
527
528static struct mvneta_rx_desc *
529mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
530{
531 int rx_desc = rxq->next_desc_to_proc;
532
533 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
534 return rxq->descs + rx_desc;
535}
536
537
538
539
540static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
541 struct mvneta_tx_queue *txq,
542 int pend_desc)
543{
544 u32 val;
545
546
547
548
549 val = pend_desc;
550 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
551}
552
553
554static struct mvneta_tx_desc *
555mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
556{
557 int tx_desc = txq->next_desc_to_proc;
558
559 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
560 return txq->descs + tx_desc;
561}
562
563
564static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
565 struct mvneta_rx_queue *rxq,
566 int buf_size)
567{
568 u32 val;
569
570 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
571
572 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
573 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
574
575 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
576}
577
578static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
579{
580
581 return pp->phyaddr > PHY_MAX_ADDR;
582}
583
584
585
586static void mvneta_port_up(struct mvneta_port *pp)
587{
588 int queue;
589 u32 q_map;
590
591
592 mvneta_mib_counters_clear(pp);
593 q_map = 0;
594 for (queue = 0; queue < txq_number; queue++) {
595 struct mvneta_tx_queue *txq = &pp->txqs[queue];
596 if (txq->descs != NULL)
597 q_map |= (1 << queue);
598 }
599 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
600
601
602 q_map = 0;
603 for (queue = 0; queue < rxq_number; queue++) {
604 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
605 if (rxq->descs != NULL)
606 q_map |= (1 << queue);
607 }
608 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
609}
610
611
612static void mvneta_port_down(struct mvneta_port *pp)
613{
614 u32 val;
615 int count;
616
617
618 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
619
620
621 if (val != 0)
622 mvreg_write(pp, MVNETA_RXQ_CMD,
623 val << MVNETA_RXQ_DISABLE_SHIFT);
624
625
626 count = 0;
627 do {
628 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
629 dev_warn(pp->phydev->dev,
630 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
631 val);
632 break;
633 }
634 mdelay(1);
635
636 val = mvreg_read(pp, MVNETA_RXQ_CMD);
637 } while (val & 0xff);
638
639
640
641
642 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
643
644 if (val != 0)
645 mvreg_write(pp, MVNETA_TXQ_CMD,
646 (val << MVNETA_TXQ_DISABLE_SHIFT));
647
648
649 count = 0;
650 do {
651 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
652 dev_warn(pp->phydev->dev,
653 "TIMEOUT for TX stopped status=0x%08x\n",
654 val);
655 break;
656 }
657 mdelay(1);
658
659
660 val = mvreg_read(pp, MVNETA_TXQ_CMD);
661
662 } while (val & 0xff);
663
664
665 count = 0;
666 do {
667 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
668 dev_warn(pp->phydev->dev,
669 "TX FIFO empty timeout status=0x08%x\n",
670 val);
671 break;
672 }
673 mdelay(1);
674
675 val = mvreg_read(pp, MVNETA_PORT_STATUS);
676 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
677 (val & MVNETA_TX_IN_PRGRS));
678
679 udelay(200);
680}
681
682
683static void mvneta_port_enable(struct mvneta_port *pp)
684{
685 u32 val;
686
687
688 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
689 val |= MVNETA_GMAC0_PORT_ENABLE;
690 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
691}
692
693
694static void mvneta_port_disable(struct mvneta_port *pp)
695{
696 u32 val;
697
698
699 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
700 val &= ~MVNETA_GMAC0_PORT_ENABLE;
701 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
702
703 udelay(200);
704}
705
706
707
708
709static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
710{
711 int offset;
712 u32 val;
713
714 if (queue == -1) {
715 val = 0;
716 } else {
717 val = 0x1 | (queue << 1);
718 val |= (val << 24) | (val << 16) | (val << 8);
719 }
720
721 for (offset = 0; offset <= 0xc; offset += 4)
722 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
723}
724
725
726static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
727{
728 int offset;
729 u32 val;
730
731 if (queue == -1) {
732 val = 0;
733 } else {
734 val = 0x1 | (queue << 1);
735 val |= (val << 24) | (val << 16) | (val << 8);
736 }
737
738 for (offset = 0; offset <= 0xfc; offset += 4)
739 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
740}
741
742
743static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
744{
745 int offset;
746 u32 val;
747
748 if (queue == -1) {
749 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
750 val = 0;
751 } else {
752 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
753 val = 0x1 | (queue << 1);
754 val |= (val << 24) | (val << 16) | (val << 8);
755 }
756
757 for (offset = 0; offset <= 0xfc; offset += 4)
758 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
759}
760
761
762
763
764
765
766
767
768
769
770static void mvneta_defaults_set(struct mvneta_port *pp)
771{
772 int cpu;
773 int queue;
774 u32 val;
775
776
777 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
778 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
779 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
780
781
782 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
783 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
784 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
785 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
786
787
788 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
789
790
791
792
793 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
794 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
795 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
796 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
797
798
799 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
800 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
801
802
803 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
804 for (queue = 0; queue < txq_number; queue++) {
805 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
806 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
807 }
808
809 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
810 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
811
812
813 val = MVNETA_ACC_MODE_EXT;
814 mvreg_write(pp, MVNETA_ACC_MODE, val);
815
816
817 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
818 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
819
820 val = 0;
821 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
822 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
823
824
825 val = 0;
826
827
828 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
829 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
830 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
831
832
833 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
834
835
836 if (!mvneta_port_is_fixed_link(pp)) {
837 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
838 val |= MVNETA_PHY_POLLING_ENABLE;
839 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
840 }
841
842 mvneta_set_ucast_table(pp, -1);
843 mvneta_set_special_mcast_table(pp, -1);
844 mvneta_set_other_mcast_table(pp, -1);
845}
846
847
848static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
849 int queue)
850{
851 unsigned int unicast_reg;
852 unsigned int tbl_offset;
853 unsigned int reg_offset;
854
855
856 last_nibble = (0xf & last_nibble);
857
858
859 tbl_offset = (last_nibble / 4) * 4;
860
861
862 reg_offset = last_nibble % 4;
863
864 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
865
866 if (queue == -1) {
867
868 unicast_reg &= ~(0xff << (8 * reg_offset));
869 } else {
870 unicast_reg &= ~(0xff << (8 * reg_offset));
871 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
872 }
873
874 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
875}
876
877
878static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
879 int queue)
880{
881 unsigned int mac_h;
882 unsigned int mac_l;
883
884 if (queue != -1) {
885 mac_l = (addr[4] << 8) | (addr[5]);
886 mac_h = (addr[0] << 24) | (addr[1] << 16) |
887 (addr[2] << 8) | (addr[3] << 0);
888
889 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
890 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
891 }
892
893
894 mvneta_set_ucast_addr(pp, addr[5], queue);
895}
896
897static int mvneta_write_hwaddr(struct udevice *dev)
898{
899 mvneta_mac_addr_set(dev_get_priv(dev),
900 ((struct eth_pdata *)dev_get_plat(dev))->enetaddr,
901 rxq_def);
902
903 return 0;
904}
905
906
907static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
908 u32 phys_addr, u32 cookie)
909{
910 rx_desc->buf_cookie = cookie;
911 rx_desc->buf_phys_addr = phys_addr;
912}
913
914
915static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
916 struct mvneta_tx_queue *txq,
917 int sent_desc)
918{
919 u32 val;
920
921
922 while (sent_desc > 0xff) {
923 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
924 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
925 sent_desc = sent_desc - 0xff;
926 }
927
928 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
929 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
930}
931
932
933static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
934 struct mvneta_tx_queue *txq)
935{
936 u32 val;
937 int sent_desc;
938
939 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
940 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
941 MVNETA_TXQ_SENT_DESC_SHIFT;
942
943 return sent_desc;
944}
945
946
947static void mvneta_rx_error(struct mvneta_port *pp,
948 struct mvneta_rx_desc *rx_desc)
949{
950 u32 status = rx_desc->status;
951
952 if (!mvneta_rxq_desc_is_first_last(status)) {
953 dev_err(pp->phydev->dev,
954 "bad rx status %08x (buffer oversize), size=%d\n",
955 status, rx_desc->data_size);
956 return;
957 }
958
959 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
960 case MVNETA_RXD_ERR_CRC:
961 dev_err(pp->phydev->dev,
962 "bad rx status %08x (crc error), size=%d\n", status,
963 rx_desc->data_size);
964 break;
965 case MVNETA_RXD_ERR_OVERRUN:
966 dev_err(pp->phydev->dev,
967 "bad rx status %08x (overrun error), size=%d\n", status,
968 rx_desc->data_size);
969 break;
970 case MVNETA_RXD_ERR_LEN:
971 dev_err(pp->phydev->dev,
972 "bad rx status %08x (max frame length error), size=%d\n",
973 status, rx_desc->data_size);
974 break;
975 case MVNETA_RXD_ERR_RESOURCE:
976 dev_err(pp->phydev->dev,
977 "bad rx status %08x (resource error), size=%d\n",
978 status, rx_desc->data_size);
979 break;
980 }
981}
982
983static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
984 int rxq)
985{
986 return &pp->rxqs[rxq];
987}
988
989
990
991static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
992 struct mvneta_rx_queue *rxq)
993{
994 int rx_done;
995
996 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
997 if (rx_done)
998 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
999}
1000
1001
1002static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1003 int num)
1004{
1005 int i;
1006
1007 for (i = 0; i < num; i++) {
1008 u32 addr;
1009
1010
1011 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
1012 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
1013 }
1014
1015
1016
1017
1018 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1019
1020 return 0;
1021}
1022
1023
1024
1025
1026static int mvneta_rxq_init(struct mvneta_port *pp,
1027 struct mvneta_rx_queue *rxq)
1028
1029{
1030 rxq->size = pp->rx_ring_size;
1031
1032
1033 rxq->descs_phys = (dma_addr_t)rxq->descs;
1034 if (rxq->descs == NULL)
1035 return -ENOMEM;
1036
1037 WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
1038
1039 rxq->last_desc = rxq->size - 1;
1040
1041
1042 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1043 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1044
1045
1046 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1047 mvneta_rxq_fill(pp, rxq, rxq->size);
1048
1049 return 0;
1050}
1051
1052
1053static void mvneta_rxq_deinit(struct mvneta_port *pp,
1054 struct mvneta_rx_queue *rxq)
1055{
1056 mvneta_rxq_drop_pkts(pp, rxq);
1057
1058 rxq->descs = NULL;
1059 rxq->last_desc = 0;
1060 rxq->next_desc_to_proc = 0;
1061 rxq->descs_phys = 0;
1062}
1063
1064
1065static int mvneta_txq_init(struct mvneta_port *pp,
1066 struct mvneta_tx_queue *txq)
1067{
1068 txq->size = pp->tx_ring_size;
1069
1070
1071 txq->descs_phys = (dma_addr_t)txq->descs;
1072 if (txq->descs == NULL)
1073 return -ENOMEM;
1074
1075 WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
1076
1077 txq->last_desc = txq->size - 1;
1078
1079
1080 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1081 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1082
1083
1084 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1085 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1086
1087 return 0;
1088}
1089
1090
1091static void mvneta_txq_deinit(struct mvneta_port *pp,
1092 struct mvneta_tx_queue *txq)
1093{
1094 txq->descs = NULL;
1095 txq->last_desc = 0;
1096 txq->next_desc_to_proc = 0;
1097 txq->descs_phys = 0;
1098
1099
1100 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1101 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1102
1103
1104 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1105 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1106}
1107
1108
1109static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1110{
1111 int queue;
1112
1113 for (queue = 0; queue < txq_number; queue++)
1114 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1115}
1116
1117
1118static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1119{
1120 int queue;
1121
1122 for (queue = 0; queue < rxq_number; queue++)
1123 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1124}
1125
1126
1127
1128static int mvneta_setup_rxqs(struct mvneta_port *pp)
1129{
1130 int queue;
1131
1132 for (queue = 0; queue < rxq_number; queue++) {
1133 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1134 if (err) {
1135 dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
1136 __func__, queue);
1137 mvneta_cleanup_rxqs(pp);
1138 return err;
1139 }
1140 }
1141
1142 return 0;
1143}
1144
1145
1146static int mvneta_setup_txqs(struct mvneta_port *pp)
1147{
1148 int queue;
1149
1150 for (queue = 0; queue < txq_number; queue++) {
1151 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1152 if (err) {
1153 dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
1154 __func__, queue);
1155 mvneta_cleanup_txqs(pp);
1156 return err;
1157 }
1158 }
1159
1160 return 0;
1161}
1162
1163static void mvneta_start_dev(struct mvneta_port *pp)
1164{
1165
1166 mvneta_port_enable(pp);
1167}
1168
1169static void mvneta_adjust_link(struct udevice *dev)
1170{
1171 struct mvneta_port *pp = dev_get_priv(dev);
1172 struct phy_device *phydev = pp->phydev;
1173 int status_change = 0;
1174
1175 if (mvneta_port_is_fixed_link(pp)) {
1176 debug("Using fixed link, skip link adjust\n");
1177 return;
1178 }
1179
1180 if (phydev->link) {
1181 if ((pp->speed != phydev->speed) ||
1182 (pp->duplex != phydev->duplex)) {
1183 u32 val;
1184
1185 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1186 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1187 MVNETA_GMAC_CONFIG_GMII_SPEED |
1188 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1189 MVNETA_GMAC_AN_SPEED_EN |
1190 MVNETA_GMAC_AN_DUPLEX_EN);
1191
1192 if (phydev->duplex)
1193 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1194
1195 if (phydev->speed == SPEED_1000)
1196 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1197 else
1198 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1199
1200 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1201
1202 pp->duplex = phydev->duplex;
1203 pp->speed = phydev->speed;
1204 }
1205 }
1206
1207 if (phydev->link != pp->link) {
1208 if (!phydev->link) {
1209 pp->duplex = -1;
1210 pp->speed = 0;
1211 }
1212
1213 pp->link = phydev->link;
1214 status_change = 1;
1215 }
1216
1217 if (status_change) {
1218 if (phydev->link) {
1219 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1220 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1221 MVNETA_GMAC_FORCE_LINK_DOWN);
1222 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1223 mvneta_port_up(pp);
1224 } else {
1225 mvneta_port_down(pp);
1226 }
1227 }
1228}
1229
1230static int mvneta_open(struct udevice *dev)
1231{
1232 struct mvneta_port *pp = dev_get_priv(dev);
1233 int ret;
1234
1235 ret = mvneta_setup_rxqs(pp);
1236 if (ret)
1237 return ret;
1238
1239 ret = mvneta_setup_txqs(pp);
1240 if (ret)
1241 return ret;
1242
1243 mvneta_adjust_link(dev);
1244
1245 mvneta_start_dev(pp);
1246
1247 return 0;
1248}
1249
1250
1251static int mvneta_init2(struct mvneta_port *pp)
1252{
1253 int queue;
1254
1255
1256 mvneta_port_disable(pp);
1257
1258
1259 mvneta_defaults_set(pp);
1260
1261 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1262 GFP_KERNEL);
1263 if (!pp->txqs)
1264 return -ENOMEM;
1265
1266
1267 pp->txqs[0].descs = buffer_loc.tx_descs;
1268
1269
1270 for (queue = 0; queue < txq_number; queue++) {
1271 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1272 txq->id = queue;
1273 txq->size = pp->tx_ring_size;
1274 }
1275
1276 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1277 GFP_KERNEL);
1278 if (!pp->rxqs) {
1279 kfree(pp->txqs);
1280 return -ENOMEM;
1281 }
1282
1283
1284 pp->rxqs[0].descs = buffer_loc.rx_descs;
1285
1286
1287 for (queue = 0; queue < rxq_number; queue++) {
1288 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1289 rxq->id = queue;
1290 rxq->size = pp->rx_ring_size;
1291 }
1292
1293 return 0;
1294}
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1307{
1308
1309
1310
1311
1312 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1313
1314
1315 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1316 MVNETA_BASE_ADDR_ENABLE_BIT);
1317
1318
1319 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1320 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1321}
1322
1323static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1324{
1325 const struct mbus_dram_target_info *dram;
1326 u32 win_enable;
1327 u32 win_protect;
1328 int i;
1329
1330 dram = mvebu_mbus_dram_info();
1331 for (i = 0; i < 6; i++) {
1332 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1333 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1334
1335 if (i < 4)
1336 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1337 }
1338
1339 win_enable = 0x3f;
1340 win_protect = 0;
1341
1342 for (i = 0; i < dram->num_cs; i++) {
1343 const struct mbus_dram_window *cs = dram->cs + i;
1344 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1345 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1346
1347 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1348 (cs->size - 1) & 0xffff0000);
1349
1350 win_enable &= ~(1 << i);
1351 win_protect |= 3 << (2 * i);
1352 }
1353
1354 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1355}
1356
1357
1358static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1359{
1360 u32 ctrl;
1361
1362
1363 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1364
1365 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1366
1367
1368
1369
1370 switch (phy_mode) {
1371 case PHY_INTERFACE_MODE_QSGMII:
1372 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1373 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1374 break;
1375 case PHY_INTERFACE_MODE_SGMII:
1376 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1377 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1378 break;
1379 case PHY_INTERFACE_MODE_RGMII:
1380 case PHY_INTERFACE_MODE_RGMII_ID:
1381 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1382 break;
1383 default:
1384 return -EINVAL;
1385 }
1386
1387
1388 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1389 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1390
1391 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1392 MVNETA_GMAC2_PORT_RESET) != 0)
1393 continue;
1394
1395 return 0;
1396}
1397
1398
1399static int mvneta_init(struct udevice *dev)
1400{
1401 struct eth_pdata *pdata = dev_get_plat(dev);
1402 struct mvneta_port *pp = dev_get_priv(dev);
1403 int err;
1404
1405 pp->tx_ring_size = MVNETA_MAX_TXD;
1406 pp->rx_ring_size = MVNETA_MAX_RXD;
1407
1408 err = mvneta_init2(pp);
1409 if (err < 0) {
1410 dev_err(dev, "can't init eth hal\n");
1411 return err;
1412 }
1413
1414 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
1415
1416 err = mvneta_port_power_up(pp, pp->phy_interface);
1417 if (err < 0) {
1418 dev_err(dev, "can't power up port\n");
1419 return err;
1420 }
1421
1422
1423 mvneta_open(dev);
1424
1425 return 0;
1426}
1427
1428
1429
1430
1431
1432static int smi_wait_ready(struct mvneta_port *pp)
1433{
1434 u32 timeout = MVNETA_SMI_TIMEOUT;
1435 u32 smi_reg;
1436
1437
1438 do {
1439
1440 smi_reg = mvreg_read(pp, MVNETA_SMI);
1441 if (timeout-- == 0) {
1442 printf("Error: SMI busy timeout\n");
1443 return -EFAULT;
1444 }
1445 } while (smi_reg & MVNETA_SMI_BUSY);
1446
1447 return 0;
1448}
1449
1450
1451
1452
1453
1454
1455static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1456{
1457 struct mvneta_port *pp = bus->priv;
1458 u32 smi_reg;
1459 u32 timeout;
1460
1461
1462 if (addr > MVNETA_PHY_ADDR_MASK) {
1463 printf("Error: Invalid PHY address %d\n", addr);
1464 return -EFAULT;
1465 }
1466
1467 if (reg > MVNETA_PHY_REG_MASK) {
1468 printf("Err: Invalid register offset %d\n", reg);
1469 return -EFAULT;
1470 }
1471
1472
1473 if (smi_wait_ready(pp) < 0)
1474 return -EFAULT;
1475
1476
1477 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1478 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
1479 | MVNETA_SMI_OPCODE_READ;
1480
1481
1482 mvreg_write(pp, MVNETA_SMI, smi_reg);
1483
1484
1485 timeout = MVNETA_SMI_TIMEOUT;
1486
1487 do {
1488
1489 smi_reg = mvreg_read(pp, MVNETA_SMI);
1490 if (timeout-- == 0) {
1491 printf("Err: SMI read ready timeout\n");
1492 return -EFAULT;
1493 }
1494 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1495
1496
1497 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1498 ;
1499
1500 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
1501}
1502
1503
1504
1505
1506
1507
1508
1509static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1510 u16 value)
1511{
1512 struct mvneta_port *pp = bus->priv;
1513 u32 smi_reg;
1514
1515
1516 if (addr > MVNETA_PHY_ADDR_MASK) {
1517 printf("Error: Invalid PHY address %d\n", addr);
1518 return -EFAULT;
1519 }
1520
1521 if (reg > MVNETA_PHY_REG_MASK) {
1522 printf("Err: Invalid register offset %d\n", reg);
1523 return -EFAULT;
1524 }
1525
1526
1527 if (smi_wait_ready(pp) < 0)
1528 return -EFAULT;
1529
1530
1531 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1532 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1533 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
1534 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1535
1536
1537 mvreg_write(pp, MVNETA_SMI, smi_reg);
1538
1539 return 0;
1540}
1541
1542static int mvneta_start(struct udevice *dev)
1543{
1544 struct mvneta_port *pp = dev_get_priv(dev);
1545 struct phy_device *phydev;
1546
1547 mvneta_port_power_up(pp, pp->phy_interface);
1548
1549 if (!pp->init || pp->link == 0) {
1550 if (mvneta_port_is_fixed_link(pp)) {
1551 u32 val;
1552
1553 pp->init = 1;
1554 pp->link = 1;
1555 mvneta_init(dev);
1556
1557 val = MVNETA_GMAC_FORCE_LINK_UP |
1558 MVNETA_GMAC_IB_BYPASS_AN_EN |
1559 MVNETA_GMAC_SET_FC_EN |
1560 MVNETA_GMAC_ADVERT_FC_EN |
1561 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1562
1563 if (pp->duplex)
1564 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1565
1566 if (pp->speed == SPEED_1000)
1567 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1568 else if (pp->speed == SPEED_100)
1569 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1570
1571 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1572 } else {
1573
1574 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1575
1576 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1577 pp->phy_interface);
1578 if (!phydev) {
1579 printf("phy_connect failed\n");
1580 return -ENODEV;
1581 }
1582
1583 pp->phydev = phydev;
1584 phy_config(phydev);
1585 phy_startup(phydev);
1586 if (!phydev->link) {
1587 printf("%s: No link.\n", phydev->dev->name);
1588 return -1;
1589 }
1590
1591
1592 mvneta_init(dev);
1593 pp->init = 1;
1594 return 0;
1595 }
1596 }
1597
1598
1599 mvneta_port_up(pp);
1600 mvneta_port_enable(pp);
1601
1602 return 0;
1603}
1604
1605static int mvneta_send(struct udevice *dev, void *packet, int length)
1606{
1607 struct mvneta_port *pp = dev_get_priv(dev);
1608 struct mvneta_tx_queue *txq = &pp->txqs[0];
1609 struct mvneta_tx_desc *tx_desc;
1610 int sent_desc;
1611 u32 timeout = 0;
1612
1613
1614 tx_desc = mvneta_txq_next_desc_get(txq);
1615
1616 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
1617 tx_desc->data_size = length;
1618 flush_dcache_range((ulong)packet,
1619 (ulong)packet + ALIGN(length, PKTALIGN));
1620
1621
1622 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1623 mvneta_txq_pend_desc_add(pp, txq, 1);
1624
1625
1626 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1627 while (!sent_desc) {
1628 if (timeout++ > 10000) {
1629 printf("timeout: packet not sent\n");
1630 return -1;
1631 }
1632 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1633 }
1634
1635
1636 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1637
1638 return 0;
1639}
1640
1641static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
1642{
1643 struct mvneta_port *pp = dev_get_priv(dev);
1644 int rx_done;
1645 struct mvneta_rx_queue *rxq;
1646 int rx_bytes = 0;
1647
1648
1649 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1650 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1651
1652 if (rx_done) {
1653 struct mvneta_rx_desc *rx_desc;
1654 unsigned char *data;
1655 u32 rx_status;
1656
1657
1658
1659
1660
1661 rx_desc = mvneta_rxq_next_desc_get(rxq);
1662
1663 rx_status = rx_desc->status;
1664 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1665 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1666 mvneta_rx_error(pp, rx_desc);
1667
1668 return -EIO;
1669 }
1670
1671
1672 rx_bytes = rx_desc->data_size - 6;
1673
1674
1675 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
1676
1677
1678
1679
1680 *packetp = data;
1681
1682
1683
1684
1685
1686 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
1687 }
1688
1689 return rx_bytes;
1690}
1691
1692static int mvneta_probe(struct udevice *dev)
1693{
1694 struct eth_pdata *pdata = dev_get_plat(dev);
1695 struct mvneta_port *pp = dev_get_priv(dev);
1696 void *blob = (void *)gd->fdt_blob;
1697 int node = dev_of_offset(dev);
1698 struct mii_dev *bus;
1699 unsigned long addr;
1700 void *bd_space;
1701 int ret;
1702 int fl_node;
1703
1704
1705
1706
1707
1708
1709 if (!buffer_loc.tx_descs) {
1710 u32 size;
1711
1712
1713 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
1714 flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
1715 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
1716 DCACHE_OFF);
1717 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
1718 size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
1719 ARCH_DMA_MINALIGN);
1720 memset(buffer_loc.tx_descs, 0, size);
1721 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
1722 ((phys_addr_t)bd_space + size);
1723 size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
1724 ARCH_DMA_MINALIGN);
1725 buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
1726 }
1727
1728 pp->base = (void __iomem *)pdata->iobase;
1729
1730
1731 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
1732 mvneta_bypass_mbus_windows(pp);
1733 else
1734 mvneta_conf_mbus_windows(pp);
1735
1736
1737 pp->phy_interface = pdata->phy_interface;
1738
1739
1740 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1741 if (fl_node != -FDT_ERR_NOTFOUND) {
1742
1743 pp->phyaddr = PHY_MAX_ADDR + 1;
1744 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1745 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1746 } else {
1747
1748 addr = fdtdec_get_int(blob, node, "phy", 0);
1749 addr = fdt_node_offset_by_phandle(blob, addr);
1750 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1751 }
1752
1753 bus = mdio_alloc();
1754 if (!bus) {
1755 printf("Failed to allocate MDIO bus\n");
1756 return -ENOMEM;
1757 }
1758
1759 bus->read = mvneta_mdio_read;
1760 bus->write = mvneta_mdio_write;
1761 snprintf(bus->name, sizeof(bus->name), dev->name);
1762 bus->priv = (void *)pp;
1763 pp->bus = bus;
1764
1765 ret = mdio_register(bus);
1766 if (ret)
1767 return ret;
1768
1769#if CONFIG_IS_ENABLED(DM_GPIO)
1770 gpio_request_by_name(dev, "phy-reset-gpios", 0,
1771 &pp->phy_reset_gpio, GPIOD_IS_OUT);
1772
1773 if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
1774 dm_gpio_set_value(&pp->phy_reset_gpio, 1);
1775 mdelay(10);
1776 dm_gpio_set_value(&pp->phy_reset_gpio, 0);
1777 }
1778#endif
1779
1780 return board_network_enable(bus);
1781}
1782
1783static void mvneta_stop(struct udevice *dev)
1784{
1785 struct mvneta_port *pp = dev_get_priv(dev);
1786
1787 mvneta_port_down(pp);
1788 mvneta_port_disable(pp);
1789}
1790
1791static const struct eth_ops mvneta_ops = {
1792 .start = mvneta_start,
1793 .send = mvneta_send,
1794 .recv = mvneta_recv,
1795 .stop = mvneta_stop,
1796 .write_hwaddr = mvneta_write_hwaddr,
1797};
1798
1799static int mvneta_of_to_plat(struct udevice *dev)
1800{
1801 struct eth_pdata *pdata = dev_get_plat(dev);
1802 const char *phy_mode;
1803
1804 pdata->iobase = dev_read_addr(dev);
1805
1806
1807 pdata->phy_interface = -1;
1808 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1809 NULL);
1810 if (phy_mode)
1811 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1812 if (pdata->phy_interface == -1) {
1813 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1814 return -EINVAL;
1815 }
1816
1817 return 0;
1818}
1819
1820static const struct udevice_id mvneta_ids[] = {
1821 { .compatible = "marvell,armada-370-neta" },
1822 { .compatible = "marvell,armada-xp-neta" },
1823 { .compatible = "marvell,armada-3700-neta" },
1824 { }
1825};
1826
1827U_BOOT_DRIVER(mvneta) = {
1828 .name = "mvneta",
1829 .id = UCLASS_ETH,
1830 .of_match = mvneta_ids,
1831 .of_to_plat = mvneta_of_to_plat,
1832 .probe = mvneta_probe,
1833 .ops = &mvneta_ops,
1834 .priv_auto = sizeof(struct mvneta_port),
1835 .plat_auto = sizeof(struct eth_pdata),
1836};
1837