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7#include <common.h>
8#include <dm.h>
9#include <log.h>
10#include <malloc.h>
11#include <dm/platform_data/pfe_dm_eth.h>
12#include <net.h>
13#include <linux/delay.h>
14#include <net/pfe_eth/pfe_eth.h>
15#include <net/pfe_eth/pfe_mdio.h>
16
17struct gemac_s gem_info[] = {
18
19 {
20
21 .gemac_speed = PFE_MAC_SPEED_1000M,
22 .gemac_duplex = DUPLEX_FULL,
23
24
25 .phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
26 .phy_mode = PHY_INTERFACE_MODE_SGMII,
27 },
28
29 {
30
31 .gemac_speed = PFE_MAC_SPEED_1000M,
32 .gemac_duplex = DUPLEX_FULL,
33
34
35 .phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
36 .phy_mode = PHY_INTERFACE_MODE_RGMII_ID,
37 },
38};
39
40static inline void pfe_gemac_enable(void *gemac_base)
41{
42 writel(readl(gemac_base + EMAC_ECNTRL_REG) |
43 EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
44}
45
46static inline void pfe_gemac_disable(void *gemac_base)
47{
48 writel(readl(gemac_base + EMAC_ECNTRL_REG) &
49 ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
50}
51
52static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
53{
54 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
55 u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
56 u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
57 u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
58 ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
59
60 if (speed == _1000BASET) {
61 ecr |= EMAC_ECNTRL_SPEED;
62 rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
63 } else if (speed != _100BASET) {
64 rcr |= EMAC_RCNTRL_RMII_10T;
65 rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
66 }
67
68 writel(ecr, gemac_base + EMAC_ECNTRL_REG);
69 out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
70
71
72 rcr &= ~EMAC_RCNTRL_LOOP;
73
74 rcr |= EMAC_RCNTRL_FCE;
75
76
77 rcr |= EMAC_RCNTRL_MII_MODE;
78
79 writel(rcr, gemac_base + EMAC_RCNTRL_REG);
80
81
82 writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
83 gemac_base + EMAC_TCNTRL_REG);
84}
85
86static int pfe_eth_write_hwaddr(struct udevice *dev)
87{
88 struct pfe_eth_dev *priv = dev_get_priv(dev);
89 struct gemac_s *gem = priv->gem;
90 struct eth_pdata *pdata = dev_get_plat(dev);
91 uchar *mac = pdata->enetaddr;
92
93 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
94 gem->gemac_base + EMAC_PHY_ADDR_LOW);
95 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
96 EMAC_PHY_ADDR_HIGH);
97 return 0;
98}
99
100
101
102
103
104
105
106static inline void pfe_eth_stop(struct udevice *dev)
107{
108 struct pfe_eth_dev *priv = dev_get_priv(dev);
109
110 pfe_gemac_disable(priv->gem->gemac_base);
111
112 gpi_disable(priv->gem->egpi_base);
113}
114
115static int pfe_eth_start(struct udevice *dev)
116{
117 struct pfe_eth_dev *priv = dev_get_priv(dev);
118 struct gemac_s *gem = priv->gem;
119 int speed;
120
121
122 pfe_eth_write_hwaddr(dev);
123
124 writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
125 writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
126 writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
127 writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
128 + EMAC_TX_SECTION_EMPTY);
129 writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
130 + EMAC_MIB_CTRL_STS_REG);
131
132#ifdef CONFIG_PHYLIB
133
134 if (phy_startup(priv->phydev)) {
135 printf("Could not initialize PHY %s\n",
136 priv->phydev->dev->name);
137 return -1;
138 }
139 speed = priv->phydev->speed;
140 printf("Speed detected %x\n", speed);
141 if (priv->phydev->duplex == DUPLEX_HALF) {
142 printf("Half duplex not supported\n");
143 return -1;
144 }
145#endif
146
147 pfe_gemac_set_speed(gem->gemac_base, speed);
148
149
150 gpi_enable(gem->egpi_base);
151
152
153 pfe_gemac_enable(gem->gemac_base);
154
155 return 0;
156}
157
158static int pfe_eth_send(struct udevice *dev, void *packet, int length)
159{
160 struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev_get_priv(dev);
161
162 int rc;
163 int i = 0;
164
165 rc = pfe_send(priv->gemac_port, packet, length);
166
167 if (rc < 0) {
168 printf("Tx Queue full\n");
169 return rc;
170 }
171
172 while (1) {
173 rc = pfe_tx_done();
174 if (rc == 0)
175 break;
176
177 udelay(100);
178 i++;
179 if (i == 30000) {
180 printf("Tx timeout, send failed\n");
181 break;
182 }
183 }
184
185 return 0;
186}
187
188static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
189{
190 struct pfe_eth_dev *priv = dev_get_priv(dev);
191 uchar *pkt_buf;
192 int len;
193 int phy_port;
194
195 len = pfe_recv(&pkt_buf, &phy_port);
196
197 if (len == 0)
198 return -EAGAIN;
199 else if (len < 0)
200 return -EAGAIN;
201
202 debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
203 phy_port, len);
204 if (phy_port != priv->gemac_port) {
205 printf("Rx pkt not on expected port\n");
206 return -EAGAIN;
207 }
208
209 *packetp = pkt_buf;
210
211 return len;
212}
213
214static int pfe_eth_probe(struct udevice *dev)
215{
216 struct pfe_eth_dev *priv = dev_get_priv(dev);
217 struct pfe_ddr_address pfe_addr;
218 struct pfe_eth_pdata *pdata = dev_get_plat(dev);
219 int ret = 0;
220 static int init_done;
221
222 if (!init_done) {
223 pfe_addr.ddr_pfe_baseaddr =
224 (void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
225 pfe_addr.ddr_pfe_phys_baseaddr =
226 (unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
227
228 debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
229 pfe_addr.ddr_pfe_baseaddr,
230 (u32)pfe_addr.ddr_pfe_phys_baseaddr);
231
232 ret = pfe_drv_init(&pfe_addr);
233 if (ret)
234 return ret;
235
236 init_pfe_scfg_dcfg_regs();
237 init_done = 1;
238 }
239
240 priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
241 priv->gem = &gem_info[priv->gemac_port];
242 priv->dev = dev;
243
244 switch (priv->gemac_port) {
245 case EMAC_PORT_0:
246 default:
247 priv->gem->gemac_base = EMAC1_BASE_ADDR;
248 priv->gem->egpi_base = EGPI1_BASE_ADDR;
249 break;
250 case EMAC_PORT_1:
251 priv->gem->gemac_base = EMAC2_BASE_ADDR;
252 priv->gem->egpi_base = EGPI2_BASE_ADDR;
253 break;
254 }
255
256 ret = pfe_eth_board_init(dev);
257 if (ret)
258 return ret;
259
260#if defined(CONFIG_PHYLIB)
261 ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
262 gem_info[priv->gemac_port].phy_address);
263#endif
264 return ret;
265}
266
267static int pfe_eth_bind(struct udevice *dev)
268{
269 struct pfe_eth_pdata *pdata = dev_get_plat(dev);
270 char name[20];
271
272 sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
273
274 return device_set_name(dev, name);
275}
276
277static const struct eth_ops pfe_eth_ops = {
278 .start = pfe_eth_start,
279 .send = pfe_eth_send,
280 .recv = pfe_eth_recv,
281 .free_pkt = pfe_eth_free_pkt,
282 .stop = pfe_eth_stop,
283 .write_hwaddr = pfe_eth_write_hwaddr,
284};
285
286U_BOOT_DRIVER(pfe_eth) = {
287 .name = "pfe_eth",
288 .id = UCLASS_ETH,
289 .bind = pfe_eth_bind,
290 .probe = pfe_eth_probe,
291 .remove = pfe_eth_remove,
292 .ops = &pfe_eth_ops,
293 .priv_auto = sizeof(struct pfe_eth_dev),
294 .plat_auto = sizeof(struct pfe_eth_pdata)
295};
296
