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32#include <common.h>
33#include <log.h>
34#include <linux/bitops.h>
35#include <linux/delay.h>
36
37#include <bitfield.h>
38#include <errno.h>
39#include <malloc.h>
40#include <miiphy.h>
41#include <netdev.h>
42
43#define PHY_AUTONEGOTIATE_TIMEOUT 5000
44
45#define PORT_MASK(port_count) ((1 << (port_count)) - 1)
46
47
48#define DEVADDR_PHY(p) (p)
49#define DEVADDR_SERDES 0x0F
50
51
52#define SMI_CMD_REG 0x00
53#define SMI_DATA_REG 0x01
54
55
56#define GLOBAL1_STATUS 0x00
57#define GLOBAL1_CTRL 0x04
58#define GLOBAL1_MON_CTRL 0x1A
59
60
61#define GLOBAL2_REG_PHY_CMD 0x18
62#define GLOBAL2_REG_PHY_DATA 0x19
63
64
65#define PORT_REG_STATUS 0x00
66#define PORT_REG_PHYS_CTRL 0x01
67#define PORT_REG_SWITCH_ID 0x03
68#define PORT_REG_CTRL 0x04
69#define PORT_REG_VLAN_MAP 0x06
70#define PORT_REG_VLAN_ID 0x07
71
72
73#define PHY_REG_CTRL1 0x10
74#define PHY_REG_STATUS1 0x11
75#define PHY_REG_PAGE 0x16
76
77
78#define SERDES_REG_CTRL_1 0x10
79
80
81#define PHY_PAGE_COPPER 0
82#define PHY_PAGE_SERDES 1
83
84
85#define GLOBAL1_CTRL_SWRESET BIT(15)
86
87#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
88#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
89
90#define PORT_REG_STATUS_SPEED_SHIFT 8
91#define PORT_REG_STATUS_SPEED_10 0
92#define PORT_REG_STATUS_SPEED_100 1
93#define PORT_REG_STATUS_SPEED_1000 2
94
95#define PORT_REG_STATUS_CMODE_MASK 0xF
96#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
97#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
98#define PORT_REG_STATUS_CMODE_SGMII 0xa
99
100#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
101#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
102#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
103#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
104#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
105#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
106#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
107#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
108#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
109#define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
110#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
111
112#define PORT_REG_CTRL_PSTATE_SHIFT 0
113#define PORT_REG_CTRL_PSTATE_WIDTH 2
114
115#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
116#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
117
118#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
119#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
120
121#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
122
123
124#define PORT_REG_CTRL_PSTATE_DISABLED 0
125#define PORT_REG_CTRL_PSTATE_FORWARD 3
126
127#define PHY_REG_CTRL1_ENERGY_DET_OFF 0
128#define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE 1
129#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
130#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131
132
133#define PHY_REG_STATUS1_SPEED 0xc000
134#define PHY_REG_STATUS1_GBIT 0x8000
135#define PHY_REG_STATUS1_100 0x4000
136#define PHY_REG_STATUS1_DUPLEX 0x2000
137#define PHY_REG_STATUS1_SPDDONE 0x0800
138#define PHY_REG_STATUS1_LINK 0x0400
139#define PHY_REG_STATUS1_ENERGY 0x0010
140
141
142
143
144
145
146#define SMI_BUSY BIT(15)
147#define SMI_CMD_CLAUSE_22 BIT(12)
148#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
149#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150
151#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
152 SMI_CMD_CLAUSE_22_OP_READ)
153#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
154 SMI_CMD_CLAUSE_22_OP_WRITE)
155
156#define SMI_CMD_ADDR_SHIFT 5
157#define SMI_CMD_ADDR_WIDTH 5
158#define SMI_CMD_REG_SHIFT 0
159#define SMI_CMD_REG_WIDTH 5
160
161
162#ifndef CONFIG_MV88E61XX_PHY_PORTS
163#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
164 to activate
165#endif
166#ifndef CONFIG_MV88E61XX_CPU_PORT
167#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
168#endif
169
170
171
172
173
174#ifndef CONFIG_MV88E61XX_FIXED_PORTS
175#define CONFIG_MV88E61XX_FIXED_PORTS 0
176#endif
177
178
179#define PORT_SWITCH_ID_6020 0x0200
180#define PORT_SWITCH_ID_6070 0x0700
181#define PORT_SWITCH_ID_6071 0x0710
182#define PORT_SWITCH_ID_6096 0x0980
183#define PORT_SWITCH_ID_6097 0x0990
184#define PORT_SWITCH_ID_6172 0x1720
185#define PORT_SWITCH_ID_6176 0x1760
186#define PORT_SWITCH_ID_6220 0x2200
187#define PORT_SWITCH_ID_6240 0x2400
188#define PORT_SWITCH_ID_6250 0x2500
189#define PORT_SWITCH_ID_6352 0x3520
190
191struct mv88e61xx_phy_priv {
192 struct mii_dev *mdio_bus;
193 int smi_addr;
194 int id;
195 int port_count;
196 int port_reg_base;
197 u16 port_stat_link_mask;
198 u16 port_stat_dup_mask;
199 u8 port_stat_speed_width;
200 u8 global1;
201 u8 global2;
202 u8 phy_ctrl1_en_det_shift;
203 u8 phy_ctrl1_en_det_width;
204 u8 phy_ctrl1_en_det_ctrl;
205};
206
207static inline int smi_cmd(int cmd, int addr, int reg)
208{
209 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
210 addr);
211 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
212 return cmd;
213}
214
215static inline int smi_cmd_read(int addr, int reg)
216{
217 return smi_cmd(SMI_CMD_READ, addr, reg);
218}
219
220static inline int smi_cmd_write(int addr, int reg)
221{
222 return smi_cmd(SMI_CMD_WRITE, addr, reg);
223}
224
225__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
226{
227 return 0;
228}
229
230
231static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
232{
233 int val;
234 u32 timeout = 100;
235
236 do {
237 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
238 if (val >= 0 && (val & SMI_BUSY) == 0)
239 return 0;
240
241 mdelay(1);
242 } while (--timeout);
243
244 puts("SMI busy timeout\n");
245 return -ETIMEDOUT;
246}
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
265{
266 struct mv88e61xx_phy_priv *priv = phydev->priv;
267 struct mii_dev *mdio_bus = priv->mdio_bus;
268 int smi_addr = priv->smi_addr;
269 int res;
270
271
272 if (smi_addr == 0)
273 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
274
275
276 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
277 if (res < 0)
278 return res;
279
280
281 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
282 smi_cmd_read(dev, reg));
283 if (res < 0)
284 return res;
285
286
287 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
288 if (res < 0)
289 return res;
290
291
292 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
293 if (res < 0)
294 return res;
295
296 return bitfield_extract(res, 0, 16);
297}
298
299
300static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
301 u16 val)
302{
303 struct mv88e61xx_phy_priv *priv = phydev->priv;
304 struct mii_dev *mdio_bus = priv->mdio_bus;
305 int smi_addr = priv->smi_addr;
306 int res;
307
308
309 if (smi_addr == 0) {
310 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
311 val);
312 }
313
314
315 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
316 if (res < 0)
317 return res;
318
319
320 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
321 SMI_DATA_REG, val);
322 if (res < 0)
323 return res;
324
325
326 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
327 smi_cmd_write(dev, reg));
328 if (res < 0)
329 return res;
330
331
332 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
333 if (res < 0)
334 return res;
335
336 return 0;
337}
338
339static int mv88e61xx_phy_wait(struct phy_device *phydev)
340{
341 struct mv88e61xx_phy_priv *priv = phydev->priv;
342 int val;
343 u32 timeout = 100;
344
345 do {
346 val = mv88e61xx_reg_read(phydev, priv->global2,
347 GLOBAL2_REG_PHY_CMD);
348 if (val >= 0 && (val & SMI_BUSY) == 0)
349 return 0;
350
351 mdelay(1);
352 } while (--timeout);
353
354 return -ETIMEDOUT;
355}
356
357static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
358 int devad, int reg)
359{
360 struct mv88e61xx_phy_priv *priv;
361 struct phy_device *phydev;
362 int res;
363
364 phydev = (struct phy_device *)smi_wrapper->priv;
365 priv = phydev->priv;
366
367
368 res = mv88e61xx_reg_write(phydev, priv->global2,
369 GLOBAL2_REG_PHY_CMD,
370 smi_cmd_read(dev, reg));
371
372
373 res = mv88e61xx_phy_wait(phydev);
374 if (res < 0)
375 return res;
376
377
378 return mv88e61xx_reg_read(phydev, priv->global2,
379 GLOBAL2_REG_PHY_DATA);
380}
381
382static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
383 int devad, int reg, u16 data)
384{
385 struct mv88e61xx_phy_priv *priv;
386 struct phy_device *phydev;
387 int res;
388
389 phydev = (struct phy_device *)smi_wrapper->priv;
390 priv = phydev->priv;
391
392
393 res = mv88e61xx_reg_write(phydev, priv->global2,
394 GLOBAL2_REG_PHY_DATA, data);
395 if (res < 0)
396 return res;
397
398 res = mv88e61xx_reg_write(phydev, priv->global2,
399 GLOBAL2_REG_PHY_CMD,
400 smi_cmd_write(dev, reg));
401 if (res < 0)
402 return res;
403
404
405 return mv88e61xx_phy_wait(phydev);
406}
407
408
409static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
410{
411 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
412 MDIO_DEVAD_NONE, reg);
413}
414
415
416static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
417 int reg, u16 val)
418{
419 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
420 MDIO_DEVAD_NONE, reg, val);
421}
422
423static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
424{
425 struct mv88e61xx_phy_priv *priv = phydev->priv;
426
427 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
428}
429
430static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
431 u16 val)
432{
433 struct mv88e61xx_phy_priv *priv = phydev->priv;
434
435 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
436 reg, val);
437}
438
439static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
440{
441 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
442}
443
444static int mv88e61xx_get_switch_id(struct phy_device *phydev)
445{
446 int res;
447
448 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
449 if (res < 0)
450 return res;
451 return res & 0xfff0;
452}
453
454static bool mv88e61xx_6352_family(struct phy_device *phydev)
455{
456 struct mv88e61xx_phy_priv *priv = phydev->priv;
457
458 switch (priv->id) {
459 case PORT_SWITCH_ID_6172:
460 case PORT_SWITCH_ID_6176:
461 case PORT_SWITCH_ID_6240:
462 case PORT_SWITCH_ID_6352:
463 return true;
464 }
465 return false;
466}
467
468static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
469{
470 int res;
471
472 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
473 if (res < 0)
474 return res;
475 return res & PORT_REG_STATUS_CMODE_MASK;
476}
477
478static int mv88e61xx_parse_status(struct phy_device *phydev)
479{
480 unsigned int speed;
481 unsigned int mii_reg;
482
483 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
484
485 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
486 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
487 int i = 0;
488
489 puts("Waiting for PHY realtime link");
490 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
491
492 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
493 puts(" TIMEOUT !\n");
494 phydev->link = 0;
495 break;
496 }
497
498 if ((i++ % 1000) == 0)
499 putc('.');
500 udelay(1000);
501 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
502 PHY_REG_STATUS1);
503 }
504 puts(" done\n");
505 udelay(500000);
506 } else {
507 if (mii_reg & PHY_REG_STATUS1_LINK)
508 phydev->link = 1;
509 else
510 phydev->link = 0;
511 }
512
513 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
514 phydev->duplex = DUPLEX_FULL;
515 else
516 phydev->duplex = DUPLEX_HALF;
517
518 speed = mii_reg & PHY_REG_STATUS1_SPEED;
519
520 switch (speed) {
521 case PHY_REG_STATUS1_GBIT:
522 phydev->speed = SPEED_1000;
523 break;
524 case PHY_REG_STATUS1_100:
525 phydev->speed = SPEED_100;
526 break;
527 default:
528 phydev->speed = SPEED_10;
529 break;
530 }
531
532 return 0;
533}
534
535static int mv88e61xx_switch_reset(struct phy_device *phydev)
536{
537 struct mv88e61xx_phy_priv *priv = phydev->priv;
538 int time;
539 int val;
540 u8 port;
541
542
543 for (port = 0; port < priv->port_count; port++) {
544 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
545 if (val < 0)
546 return val;
547 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
548 PORT_REG_CTRL_PSTATE_WIDTH,
549 PORT_REG_CTRL_PSTATE_DISABLED);
550 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
551 if (val < 0)
552 return val;
553 }
554
555
556 udelay(2000);
557
558
559 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
560 if (val < 0)
561 return val;
562 val |= GLOBAL1_CTRL_SWRESET;
563 val = mv88e61xx_reg_write(phydev, priv->global1,
564 GLOBAL1_CTRL, val);
565 if (val < 0)
566 return val;
567
568
569 for (time = 1000; time; time--) {
570 val = mv88e61xx_reg_read(phydev, priv->global1,
571 GLOBAL1_CTRL);
572 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
573 break;
574 udelay(1000);
575 }
576 if (!time)
577 return -ETIMEDOUT;
578
579 return 0;
580}
581
582static int mv88e61xx_serdes_init(struct phy_device *phydev)
583{
584 int val;
585
586 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
587 if (val < 0)
588 return val;
589
590
591 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
592 if (val < 0)
593 return val;
594 val &= ~(BMCR_PDOWN);
595 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
596 if (val < 0)
597 return val;
598
599 return 0;
600}
601
602static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
603{
604 int val;
605
606 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
607 if (val < 0)
608 return val;
609 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
610 PORT_REG_CTRL_PSTATE_WIDTH,
611 PORT_REG_CTRL_PSTATE_FORWARD);
612 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
613 if (val < 0)
614 return val;
615
616 return 0;
617}
618
619static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
620 u16 mask)
621{
622 int val;
623
624
625 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
626 if (val < 0)
627 return val;
628 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
629 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
630 port + 1);
631 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
632 if (val < 0)
633 return val;
634
635
636 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
637 if (val < 0)
638 return val;
639 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
640 PORT_REG_VLAN_MAP_TABLE_WIDTH,
641 mask);
642 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
643 if (val < 0)
644 return val;
645
646 return 0;
647}
648
649static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
650{
651 struct mv88e61xx_phy_priv *priv = phydev->priv;
652 int res;
653 int val;
654 bool forced = false;
655
656 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
657 if (val < 0)
658 return val;
659 if (!(val & priv->port_stat_link_mask)) {
660
661 u32 timeout = 100;
662 forced = true;
663
664 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
665 if (val < 0)
666 return val;
667 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
668 PORT_REG_PHYS_CTRL_LINK_VALUE);
669 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
670 val);
671 if (val < 0)
672 return val;
673
674
675 do {
676 val = mv88e61xx_port_read(phydev, port,
677 PORT_REG_STATUS);
678 if (val < 0) {
679 res = -EIO;
680 goto unforce;
681 }
682 if (val & priv->port_stat_link_mask)
683 break;
684 } while (--timeout);
685
686 if (timeout == 0) {
687 res = -ETIMEDOUT;
688 goto unforce;
689 }
690 }
691
692 if (val & priv->port_stat_dup_mask)
693 phydev->duplex = DUPLEX_FULL;
694 else
695 phydev->duplex = DUPLEX_HALF;
696
697 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
698 priv->port_stat_speed_width);
699 switch (val) {
700 case PORT_REG_STATUS_SPEED_1000:
701 phydev->speed = SPEED_1000;
702 break;
703 case PORT_REG_STATUS_SPEED_100:
704 phydev->speed = SPEED_100;
705 break;
706 default:
707 phydev->speed = SPEED_10;
708 break;
709 }
710
711 res = 0;
712
713unforce:
714 if (forced) {
715 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
716 if (val < 0)
717 return val;
718 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
719 PORT_REG_PHYS_CTRL_LINK_VALUE);
720 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
721 val);
722 if (val < 0)
723 return val;
724 }
725
726 return res;
727}
728
729static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
730{
731 struct mv88e61xx_phy_priv *priv = phydev->priv;
732 int val;
733
734 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
735 if (val < 0)
736 return val;
737
738 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
739 PORT_REG_PHYS_CTRL_FC_VALUE |
740 PORT_REG_PHYS_CTRL_FC_FORCE);
741 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
742 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
743 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
744
745 if (priv->id == PORT_SWITCH_ID_6071) {
746 val |= PORT_REG_PHYS_CTRL_SPD100;
747 } else {
748 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
749 PORT_REG_PHYS_CTRL_PCS_AN_RST |
750 PORT_REG_PHYS_CTRL_SPD1000;
751 }
752
753 if (port == CONFIG_MV88E61XX_CPU_PORT)
754 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
755 PORT_REG_PHYS_CTRL_LINK_FORCE;
756
757 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
758 val);
759}
760
761static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
762{
763 struct mv88e61xx_phy_priv *priv = phydev->priv;
764 int val;
765
766
767 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
768 if (val < 0)
769 return val;
770 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
771 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
772 CONFIG_MV88E61XX_CPU_PORT);
773 val = mv88e61xx_reg_write(phydev, priv->global1,
774 GLOBAL1_MON_CTRL, val);
775 if (val < 0)
776 return val;
777
778
779 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
780 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
781 if (val < 0)
782 return val;
783
784
785 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
786 if (val < 0)
787 return val;
788
789 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
790 if (val < 0)
791 return val;
792
793
794 if (mv88e61xx_6352_family(phydev)) {
795 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
796 if (val < 0)
797 return val;
798 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
799 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
800 val == PORT_REG_STATUS_CMODE_SGMII) {
801 val = mv88e61xx_serdes_init(phydev);
802 if (val < 0)
803 return val;
804 }
805 } else {
806 val = mv88e61xx_fixed_port_setup(phydev,
807 CONFIG_MV88E61XX_CPU_PORT);
808 if (val < 0)
809 return val;
810 }
811
812 return 0;
813}
814
815static int mv88e61xx_switch_init(struct phy_device *phydev)
816{
817 static int init;
818 int res;
819
820 if (init)
821 return 0;
822
823 res = mv88e61xx_switch_reset(phydev);
824 if (res < 0)
825 return res;
826
827 res = mv88e61xx_set_cpu_port(phydev);
828 if (res < 0)
829 return res;
830
831 init = 1;
832
833 return 0;
834}
835
836static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
837{
838 int val;
839
840 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
841 if (val < 0)
842 return val;
843 val &= ~(BMCR_PDOWN);
844 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
845 if (val < 0)
846 return val;
847
848 return 0;
849}
850
851static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
852{
853 struct mv88e61xx_phy_priv *priv = phydev->priv;
854 int val;
855
856
857
858
859
860 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
861 if (val < 0)
862 return val;
863 val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
864 priv->phy_ctrl1_en_det_width,
865 priv->phy_ctrl1_en_det_ctrl);
866 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
867 if (val < 0)
868 return val;
869
870 return 0;
871}
872
873static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
874{
875 int val;
876
877 val = mv88e61xx_port_enable(phydev, phy);
878 if (val < 0)
879 return val;
880
881 val = mv88e61xx_port_set_vlan(phydev, phy,
882 1 << CONFIG_MV88E61XX_CPU_PORT);
883 if (val < 0)
884 return val;
885
886 return 0;
887}
888
889
890
891
892
893
894
895
896
897static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
898{
899 struct mv88e61xx_phy_priv *priv = phydev->priv;
900
901
902
903
904
905
906
907 priv->port_reg_base = 0x10;
908 priv->id = mv88e61xx_get_switch_id(phydev);
909 if (priv->id != 0xfff0) {
910 priv->global1 = 0x1B;
911 priv->global2 = 0x1C;
912 return 0;
913 }
914
915
916
917
918
919 priv->port_reg_base = 0x08;
920 priv->id = mv88e61xx_get_switch_id(phydev);
921 if (priv->id != 0xfff0) {
922 priv->global1 = 0x0F;
923 priv->global2 = 0x07;
924 return 0;
925 }
926
927 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
928 return -ENODEV;
929}
930
931static int mv88e61xx_probe(struct phy_device *phydev)
932{
933 struct mii_dev *smi_wrapper;
934 struct mv88e61xx_phy_priv *priv;
935 int res;
936
937 res = mv88e61xx_hw_reset(phydev);
938 if (res < 0)
939 return res;
940
941 priv = malloc(sizeof(*priv));
942 if (!priv)
943 return -ENOMEM;
944
945 memset(priv, 0, sizeof(*priv));
946
947
948
949
950
951
952 smi_wrapper = mdio_alloc();
953 if (!smi_wrapper) {
954 free(priv);
955 return -ENOMEM;
956 }
957
958
959
960
961
962 priv->mdio_bus = phydev->bus;
963
964
965
966
967
968
969 priv->smi_addr = phydev->addr;
970
971
972
973
974
975 smi_wrapper->priv = phydev;
976 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
977 smi_wrapper->read = mv88e61xx_phy_read_indirect;
978 smi_wrapper->write = mv88e61xx_phy_write_indirect;
979
980
981 phydev->bus = smi_wrapper;
982
983 phydev->priv = priv;
984
985 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
986 if (res < 0)
987 return res;
988
989 debug("%s ID 0x%x\n", __func__, priv->id);
990
991 switch (priv->id) {
992 case PORT_SWITCH_ID_6096:
993 case PORT_SWITCH_ID_6097:
994 case PORT_SWITCH_ID_6172:
995 case PORT_SWITCH_ID_6176:
996 case PORT_SWITCH_ID_6240:
997 case PORT_SWITCH_ID_6352:
998 priv->port_count = 11;
999 priv->port_stat_link_mask = BIT(11);
1000 priv->port_stat_dup_mask = BIT(10);
1001 priv->port_stat_speed_width = 2;
1002 priv->phy_ctrl1_en_det_shift = 8;
1003 priv->phy_ctrl1_en_det_width = 2;
1004 priv->phy_ctrl1_en_det_ctrl =
1005 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
1006 break;
1007 case PORT_SWITCH_ID_6020:
1008 case PORT_SWITCH_ID_6070:
1009 case PORT_SWITCH_ID_6071:
1010 case PORT_SWITCH_ID_6220:
1011 case PORT_SWITCH_ID_6250:
1012 priv->port_count = 7;
1013 priv->port_stat_link_mask = BIT(12);
1014 priv->port_stat_dup_mask = BIT(9);
1015 priv->port_stat_speed_width = 1;
1016 priv->phy_ctrl1_en_det_shift = 14;
1017 priv->phy_ctrl1_en_det_width = 1;
1018 priv->phy_ctrl1_en_det_ctrl =
1019 PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
1020 break;
1021 default:
1022 free(priv);
1023 return -ENODEV;
1024 }
1025
1026 res = mdio_register(smi_wrapper);
1027 if (res)
1028 printf("Failed to register SMI bus\n");
1029
1030 return 0;
1031}
1032
1033static int mv88e61xx_phy_config(struct phy_device *phydev)
1034{
1035 struct mv88e61xx_phy_priv *priv = phydev->priv;
1036 int res;
1037 int i;
1038 int ret = -1;
1039
1040 res = mv88e61xx_switch_init(phydev);
1041 if (res < 0)
1042 return res;
1043
1044 for (i = 0; i < priv->port_count; i++) {
1045 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1046 phydev->addr = i;
1047
1048 res = mv88e61xx_phy_enable(phydev, i);
1049 if (res < 0) {
1050 printf("Error enabling PHY %i\n", i);
1051 continue;
1052 }
1053 res = mv88e61xx_phy_setup(phydev, i);
1054 if (res < 0) {
1055 printf("Error setting up PHY %i\n", i);
1056 continue;
1057 }
1058 res = mv88e61xx_phy_config_port(phydev, i);
1059 if (res < 0) {
1060 printf("Error configuring PHY %i\n", i);
1061 continue;
1062 }
1063
1064 res = phy_reset(phydev);
1065 if (res < 0) {
1066 printf("Error resetting PHY %i\n", i);
1067 continue;
1068 }
1069 res = genphy_config_aneg(phydev);
1070 if (res < 0) {
1071 printf("Error setting PHY %i autoneg\n", i);
1072 continue;
1073 }
1074
1075
1076 ret = 0;
1077 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1078 res = mv88e61xx_fixed_port_setup(phydev, i);
1079 if (res < 0) {
1080 printf("Error configuring port %i\n", i);
1081 continue;
1082 }
1083 }
1084 }
1085
1086 return ret;
1087}
1088
1089static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1090{
1091 int val;
1092
1093 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1094 if (val < 0)
1095 return 0;
1096
1097
1098
1099
1100
1101
1102 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1103}
1104
1105static int mv88e61xx_phy_startup(struct phy_device *phydev)
1106{
1107 struct mv88e61xx_phy_priv *priv = phydev->priv;
1108 int i;
1109 int link = 0;
1110 int res;
1111 int speed = phydev->speed;
1112 int duplex = phydev->duplex;
1113
1114 for (i = 0; i < priv->port_count; i++) {
1115 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1116 phydev->addr = i;
1117 if (!mv88e61xx_phy_is_connected(phydev))
1118 continue;
1119 res = genphy_update_link(phydev);
1120 if (res < 0)
1121 continue;
1122 res = mv88e61xx_parse_status(phydev);
1123 if (res < 0)
1124 continue;
1125 link = (link || phydev->link);
1126 }
1127 }
1128 phydev->link = link;
1129
1130
1131
1132 phydev->speed = speed;
1133 phydev->duplex = duplex;
1134
1135 return 0;
1136}
1137
1138static struct phy_driver mv88e61xx_driver = {
1139 .name = "Marvell MV88E61xx",
1140 .uid = 0x01410eb1,
1141 .mask = 0xfffffff0,
1142 .features = PHY_GBIT_FEATURES,
1143 .probe = mv88e61xx_probe,
1144 .config = mv88e61xx_phy_config,
1145 .startup = mv88e61xx_phy_startup,
1146 .shutdown = &genphy_shutdown,
1147};
1148
1149static struct phy_driver mv88e609x_driver = {
1150 .name = "Marvell MV88E609x",
1151 .uid = 0x1410c89,
1152 .mask = 0xfffffff0,
1153 .features = PHY_GBIT_FEATURES,
1154 .probe = mv88e61xx_probe,
1155 .config = mv88e61xx_phy_config,
1156 .startup = mv88e61xx_phy_startup,
1157 .shutdown = &genphy_shutdown,
1158};
1159
1160static struct phy_driver mv88e6071_driver = {
1161 .name = "Marvell MV88E6071",
1162 .uid = 0x1410db0,
1163 .mask = 0xfffffff0,
1164 .features = PHY_BASIC_FEATURES | SUPPORTED_MII,
1165 .probe = mv88e61xx_probe,
1166 .config = mv88e61xx_phy_config,
1167 .startup = mv88e61xx_phy_startup,
1168 .shutdown = &genphy_shutdown,
1169};
1170
1171int phy_mv88e61xx_init(void)
1172{
1173 phy_register(&mv88e61xx_driver);
1174 phy_register(&mv88e609x_driver);
1175 phy_register(&mv88e6071_driver);
1176
1177 return 0;
1178}
1179
1180
1181
1182
1183
1184int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1185{
1186 struct phy_device temp_phy;
1187 struct mv88e61xx_phy_priv temp_priv;
1188 struct mii_dev temp_mii;
1189 int val;
1190
1191
1192
1193
1194
1195 temp_priv.mdio_bus = bus;
1196 temp_priv.smi_addr = smi_addr;
1197 temp_phy.priv = &temp_priv;
1198 temp_mii.priv = &temp_phy;
1199
1200
1201
1202
1203
1204
1205
1206 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1207 if (val < 0)
1208 return val;
1209
1210 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1211 if (val < 0)
1212 return -EIO;
1213
1214 *phy_id = val << 16;
1215
1216 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1217 if (val < 0)
1218 return -EIO;
1219
1220 *phy_id |= (val & 0xffff);
1221
1222 return 0;
1223}
1224