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18#include <common.h>
19#include <asm/io.h>
20#include <clk.h>
21#include <dm.h>
22#include <errno.h>
23#include <pci.h>
24#include <wait_bit.h>
25#include <linux/bitops.h>
26#include <linux/log2.h>
27
28#define PCIECAR 0x000010
29#define PCIECCTLR 0x000018
30#define CONFIG_SEND_ENABLE BIT(31)
31#define TYPE0 (0 << 8)
32#define TYPE1 BIT(8)
33#define PCIECDR 0x000020
34#define PCIEMSR 0x000028
35#define PCIEINTXR 0x000400
36#define PCIEPHYSR 0x0007f0
37#define PHYRDY BIT(0)
38#define PCIEMSITXR 0x000840
39
40
41#define PCIETCTLR 0x02000
42#define CFINIT 1
43#define PCIETSTR 0x02004
44#define DATA_LINK_ACTIVE 1
45#define PCIEERRFR 0x02020
46#define UNSUPPORTED_REQUEST BIT(4)
47#define PCIEMSIFR 0x02044
48#define PCIEMSIALR 0x02048
49#define MSIFE 1
50#define PCIEMSIAUR 0x0204c
51#define PCIEMSIIER 0x02050
52
53
54#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
55
56
57#define PCIELAR(x) (0x02200 + ((x) * 0x20))
58#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
59#define LAM_PREFETCH BIT(3)
60#define LAM_64BIT BIT(2)
61#define LAR_ENABLE BIT(1)
62
63
64#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
65#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
66#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
67#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
68#define PAR_ENABLE BIT(31)
69#define IO_SPACE BIT(8)
70
71
72#define PCICONF(x) (0x010000 + ((x) * 0x4))
73#define PMCAP(x) (0x010040 + ((x) * 0x4))
74#define EXPCAP(x) (0x010070 + ((x) * 0x4))
75#define VCCAP(x) (0x010100 + ((x) * 0x4))
76
77
78#define IDSETR1 0x011004
79#define TLCTLR 0x011048
80#define MACSR 0x011054
81#define SPCHGFIN BIT(4)
82#define SPCHGFAIL BIT(6)
83#define SPCHGSUC BIT(7)
84#define LINK_SPEED (0xf << 16)
85#define LINK_SPEED_2_5GTS (1 << 16)
86#define LINK_SPEED_5_0GTS (2 << 16)
87#define MACCTLR 0x011058
88#define SPEED_CHANGE BIT(24)
89#define SCRAMBLE_DISABLE BIT(27)
90#define MACS2R 0x011078
91#define MACCGSPSETR 0x011084
92#define SPCNGRSN BIT(31)
93
94
95#define H1_PCIEPHYADRR 0x04000c
96#define WRITE_CMD BIT(16)
97#define PHY_ACK BIT(24)
98#define RATE_POS 12
99#define LANE_POS 8
100#define ADR_POS 0
101#define H1_PCIEPHYDOUTR 0x040014
102
103
104#define GEN2_PCIEPHYADDR 0x780
105#define GEN2_PCIEPHYDATA 0x784
106#define GEN2_PCIEPHYCTRL 0x78c
107
108#define INT_PCI_MSI_NR 32
109
110#define RCONF(x) (PCICONF(0) + (x))
111#define RPMCAP(x) (PMCAP(0) + (x))
112#define REXPCAP(x) (EXPCAP(0) + (x))
113#define RVCCAP(x) (VCCAP(0) + (x))
114
115#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
116#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
117#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
118
119#define RCAR_PCI_MAX_RESOURCES 4
120#define MAX_NR_INBOUND_MAPS 6
121
122enum {
123 RCAR_PCI_ACCESS_READ,
124 RCAR_PCI_ACCESS_WRITE,
125};
126
127struct rcar_gen3_pcie_priv {
128 fdt_addr_t regs;
129};
130
131static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
132{
133 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
134 int shift = 8 * (where & 3);
135
136 clrsetbits_le32(priv->regs + (where & ~3),
137 mask << shift, data << shift);
138}
139
140static u32 rcar_read_conf(const struct udevice *dev, int where)
141{
142 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
143 int shift = 8 * (where & 3);
144
145 return readl(priv->regs + (where & ~3)) >> shift;
146}
147
148static int rcar_pcie_config_access(const struct udevice *udev,
149 unsigned char access_type,
150 pci_dev_t bdf, int where, ulong *data)
151{
152 struct rcar_gen3_pcie_priv *priv = dev_get_plat(udev);
153 u32 reg = where & ~3;
154
155
156 if (PCI_DEV(bdf) == 0) {
157 if (access_type == RCAR_PCI_ACCESS_READ)
158 *data = readl(priv->regs + PCICONF(where / 4));
159 else
160 writel(*data, priv->regs + PCICONF(where / 4));
161
162 return 0;
163 }
164
165
166 clrbits_le32(priv->regs + PCIEERRFR, 0);
167
168
169 writel((bdf << 8) | reg, priv->regs + PCIECAR);
170
171
172 if (!PCI_BUS(bdf))
173 writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
174 else
175 writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
176
177
178 if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
179 return -ENODEV;
180
181
182 if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
183 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
184 return -ENODEV;
185
186 if (access_type == RCAR_PCI_ACCESS_READ)
187 *data = readl(priv->regs + PCIECDR);
188 else
189 writel(*data, priv->regs + PCIECDR);
190
191
192 writel(0, priv->regs + PCIECCTLR);
193
194 return 0;
195}
196
197static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
198{
199 u32 slot;
200
201 if (PCI_BUS(d))
202 return -EINVAL;
203
204 if (PCI_FUNC(d))
205 return -EINVAL;
206
207 slot = PCI_DEV(d);
208 if (slot > 1)
209 return -EINVAL;
210
211 return 0;
212}
213
214static int rcar_gen3_pcie_read_config(const struct udevice *dev, pci_dev_t bdf,
215 uint where, ulong *val,
216 enum pci_size_t size)
217{
218 ulong reg;
219 int ret;
220
221 ret = rcar_gen3_pcie_addr_valid(bdf, where);
222 if (ret) {
223 *val = pci_get_ff(size);
224 return 0;
225 }
226
227 ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
228 bdf, where, ®);
229 if (ret != 0)
230 reg = 0xffffffffUL;
231
232 *val = pci_conv_32_to_size(reg, where, size);
233
234 return ret;
235}
236
237static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
238 uint where, ulong val,
239 enum pci_size_t size)
240{
241 ulong data;
242 int ret;
243
244 ret = rcar_gen3_pcie_addr_valid(bdf, where);
245 if (ret)
246 return ret;
247
248 data = pci_conv_32_to_size(val, where, size);
249
250 ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
251 bdf, where, &data);
252
253 return ret;
254}
255
256static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
257{
258 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
259
260 return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
261 true, 50, false);
262}
263
264static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
265{
266 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
267
268 return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
269 DATA_LINK_ACTIVE, true, 50, false);
270}
271
272static int rcar_gen3_pcie_hw_init(struct udevice *dev)
273{
274 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
275 int ret;
276
277
278 writel(0, priv->regs + PCIETCTLR);
279
280
281 writel(1, priv->regs + PCIEMSR);
282
283 ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
284 if (ret)
285 return ret;
286
287
288
289
290
291
292 writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
293
294
295
296
297
298 rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
299 rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
300
301
302 rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
303 rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
304 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
305 rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
306 PCI_HEADER_TYPE_BRIDGE);
307
308
309 rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
310 PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
311
312
313 rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
314 PCI_EXP_SLTCAP_PSN, 0);
315
316
317 rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
318
319
320 rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
321
322
323 writel(CFINIT, priv->regs + PCIETCTLR);
324
325 return rcar_gen3_pcie_wait_for_dl(dev);
326}
327
328static int rcar_gen3_pcie_probe(struct udevice *dev)
329{
330 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
331 struct pci_controller *hose = dev_get_uclass_priv(dev);
332 struct clk pci_clk;
333 u32 mask;
334 int i, cnt, ret;
335
336 ret = clk_get_by_index(dev, 0, &pci_clk);
337 if (ret)
338 return ret;
339
340 ret = clk_enable(&pci_clk);
341 if (ret)
342 return ret;
343
344 for (i = 0; i < hose->region_count; i++) {
345 if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
346 continue;
347
348 if (hose->regions[i].phys_start == 0)
349 continue;
350
351 mask = (roundup_pow_of_two(hose->regions[i].size) - 1) & ~0xf;
352 mask |= LAR_ENABLE;
353 writel(rounddown_pow_of_two(hose->regions[i].phys_start),
354 priv->regs + PCIEPRAR(0));
355 writel(rounddown_pow_of_two(hose->regions[i].phys_start),
356 priv->regs + PCIELAR(0));
357 writel(mask, priv->regs + PCIELAMR(0));
358 break;
359 }
360
361 writel(0, priv->regs + PCIEPRAR(1));
362 writel(0, priv->regs + PCIELAR(1));
363 writel(0, priv->regs + PCIELAMR(1));
364
365 ret = rcar_gen3_pcie_hw_init(dev);
366 if (ret)
367 return ret;
368
369 for (i = 0, cnt = 0; i < hose->region_count; i++) {
370 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
371 continue;
372
373 writel(0, priv->regs + PCIEPTCTLR(cnt));
374 writel((hose->regions[i].size - 1) & ~0x7f,
375 priv->regs + PCIEPAMR(cnt));
376 writel(upper_32_bits(hose->regions[i].phys_start),
377 priv->regs + PCIEPAUR(cnt));
378 writel(lower_32_bits(hose->regions[i].phys_start),
379 priv->regs + PCIEPALR(cnt));
380 mask = PAR_ENABLE;
381 if (hose->regions[i].flags == PCI_REGION_IO)
382 mask |= IO_SPACE;
383 writel(mask, priv->regs + PCIEPTCTLR(cnt));
384
385 cnt++;
386 }
387
388 return 0;
389}
390
391static int rcar_gen3_pcie_of_to_plat(struct udevice *dev)
392{
393 struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
394
395 priv->regs = devfdt_get_addr_index(dev, 0);
396 if (!priv->regs)
397 return -EINVAL;
398
399 return 0;
400}
401
402static const struct dm_pci_ops rcar_gen3_pcie_ops = {
403 .read_config = rcar_gen3_pcie_read_config,
404 .write_config = rcar_gen3_pcie_write_config,
405};
406
407static const struct udevice_id rcar_gen3_pcie_ids[] = {
408 { .compatible = "renesas,pcie-rcar-gen3" },
409 { }
410};
411
412U_BOOT_DRIVER(rcar_gen3_pcie) = {
413 .name = "rcar_gen3_pcie",
414 .id = UCLASS_PCI,
415 .of_match = rcar_gen3_pcie_ids,
416 .ops = &rcar_gen3_pcie_ops,
417 .probe = rcar_gen3_pcie_probe,
418 .of_to_plat = rcar_gen3_pcie_of_to_plat,
419 .plat_auto = sizeof(struct rcar_gen3_pcie_priv),
420};
421
