1
2
3
4
5
6
7#define LOG_CATEGORY UCLASS_PCI
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <init.h>
13#include <log.h>
14#include <malloc.h>
15#include <pci.h>
16#include <asm/global_data.h>
17#include <asm/io.h>
18#include <dm/device-internal.h>
19#include <dm/lists.h>
20#include <dm/uclass-internal.h>
21#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
22#include <asm/fsp/fsp_support.h>
23#endif
24#include <dt-bindings/pci/pci.h>
25#include <linux/delay.h>
26#include "pci_internal.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
30int pci_get_bus(int busnum, struct udevice **busp)
31{
32 int ret;
33
34 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
35
36
37 if (ret == -ENODEV) {
38 ret = uclass_first_device_err(UCLASS_PCI, busp);
39 if (ret)
40 return ret;
41 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 }
43
44 return ret;
45}
46
47struct udevice *pci_get_controller(struct udevice *dev)
48{
49 while (device_is_on_pci_bus(dev))
50 dev = dev->parent;
51
52 return dev;
53}
54
55pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
56{
57 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
58 struct udevice *bus = dev->parent;
59
60
61
62
63
64
65
66
67
68
69
70 if (!device_active(bus))
71 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
72 bus->name);
73 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
74}
75
76
77
78
79
80
81static int pci_get_bus_max(void)
82{
83 struct udevice *bus;
84 struct uclass *uc;
85 int ret = -1;
86
87 ret = uclass_get(UCLASS_PCI, &uc);
88 uclass_foreach_dev(bus, uc) {
89 if (dev_seq(bus) > ret)
90 ret = dev_seq(bus);
91 }
92
93 debug("%s: ret=%d\n", __func__, ret);
94
95 return ret;
96}
97
98int pci_last_busno(void)
99{
100 return pci_get_bus_max();
101}
102
103int pci_get_ff(enum pci_size_t size)
104{
105 switch (size) {
106 case PCI_SIZE_8:
107 return 0xff;
108 case PCI_SIZE_16:
109 return 0xffff;
110 default:
111 return 0xffffffff;
112 }
113}
114
115static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
116 ofnode *rnode)
117{
118 struct fdt_pci_addr addr;
119 ofnode node;
120 int ret;
121
122 dev_for_each_subnode(node, bus) {
123 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
124 &addr);
125 if (ret)
126 continue;
127
128 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
129 continue;
130
131 *rnode = node;
132 break;
133 }
134};
135
136int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
137 struct udevice **devp)
138{
139 struct udevice *dev;
140
141 for (device_find_first_child(bus, &dev);
142 dev;
143 device_find_next_child(&dev)) {
144 struct pci_child_plat *pplat;
145
146 pplat = dev_get_parent_plat(dev);
147 if (pplat && pplat->devfn == find_devfn) {
148 *devp = dev;
149 return 0;
150 }
151 }
152
153 return -ENODEV;
154}
155
156int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
157{
158 struct udevice *bus;
159 int ret;
160
161 ret = pci_get_bus(PCI_BUS(bdf), &bus);
162 if (ret)
163 return ret;
164 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
165}
166
167static int pci_device_matches_ids(struct udevice *dev,
168 const struct pci_device_id *ids)
169{
170 struct pci_child_plat *pplat;
171 int i;
172
173 pplat = dev_get_parent_plat(dev);
174 if (!pplat)
175 return -EINVAL;
176 for (i = 0; ids[i].vendor != 0; i++) {
177 if (pplat->vendor == ids[i].vendor &&
178 pplat->device == ids[i].device)
179 return i;
180 }
181
182 return -EINVAL;
183}
184
185int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
186 int *indexp, struct udevice **devp)
187{
188 struct udevice *dev;
189
190
191 for (device_find_first_child(bus, &dev);
192 dev;
193 device_find_next_child(&dev)) {
194 if (pci_device_matches_ids(dev, ids) >= 0) {
195 if ((*indexp)-- <= 0) {
196 *devp = dev;
197 return 0;
198 }
199 }
200 }
201
202 return -ENODEV;
203}
204
205int pci_find_device_id(const struct pci_device_id *ids, int index,
206 struct udevice **devp)
207{
208 struct udevice *bus;
209
210
211 for (uclass_first_device(UCLASS_PCI, &bus);
212 bus;
213 uclass_next_device(&bus)) {
214 if (!pci_bus_find_devices(bus, ids, &index, devp))
215 return 0;
216 }
217 *devp = NULL;
218
219 return -ENODEV;
220}
221
222static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
223 unsigned int device, int *indexp,
224 struct udevice **devp)
225{
226 struct pci_child_plat *pplat;
227 struct udevice *dev;
228
229 for (device_find_first_child(bus, &dev);
230 dev;
231 device_find_next_child(&dev)) {
232 pplat = dev_get_parent_plat(dev);
233 if (pplat->vendor == vendor && pplat->device == device) {
234 if (!(*indexp)--) {
235 *devp = dev;
236 return 0;
237 }
238 }
239 }
240
241 return -ENODEV;
242}
243
244int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
245 struct udevice **devp)
246{
247 struct udevice *bus;
248
249
250 for (uclass_first_device(UCLASS_PCI, &bus);
251 bus;
252 uclass_next_device(&bus)) {
253 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
254 return device_probe(*devp);
255 }
256 *devp = NULL;
257
258 return -ENODEV;
259}
260
261int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
262{
263 struct udevice *dev;
264
265
266 for (pci_find_first_device(&dev);
267 dev;
268 pci_find_next_device(&dev)) {
269 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
270
271 if (pplat->class == find_class && !index--) {
272 *devp = dev;
273 return device_probe(*devp);
274 }
275 }
276 *devp = NULL;
277
278 return -ENODEV;
279}
280
281int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
282 unsigned long value, enum pci_size_t size)
283{
284 struct dm_pci_ops *ops;
285
286 ops = pci_get_ops(bus);
287 if (!ops->write_config)
288 return -ENOSYS;
289 return ops->write_config(bus, bdf, offset, value, size);
290}
291
292int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
293 u32 clr, u32 set)
294{
295 ulong val;
296 int ret;
297
298 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
299 if (ret)
300 return ret;
301 val &= ~clr;
302 val |= set;
303
304 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
305}
306
307static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
308 enum pci_size_t size)
309{
310 struct udevice *bus;
311 int ret;
312
313 ret = pci_get_bus(PCI_BUS(bdf), &bus);
314 if (ret)
315 return ret;
316
317 return pci_bus_write_config(bus, bdf, offset, value, size);
318}
319
320int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
321 enum pci_size_t size)
322{
323 struct udevice *bus;
324
325 for (bus = dev; device_is_on_pci_bus(bus);)
326 bus = bus->parent;
327 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
328 size);
329}
330
331int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
332{
333 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
334}
335
336int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
337{
338 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
339}
340
341int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
342{
343 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
344}
345
346int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
347{
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
349}
350
351int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
352{
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
354}
355
356int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
357{
358 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
359}
360
361int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
362 unsigned long *valuep, enum pci_size_t size)
363{
364 struct dm_pci_ops *ops;
365
366 ops = pci_get_ops(bus);
367 if (!ops->read_config)
368 return -ENOSYS;
369 return ops->read_config(bus, bdf, offset, valuep, size);
370}
371
372static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
373 enum pci_size_t size)
374{
375 struct udevice *bus;
376 int ret;
377
378 ret = pci_get_bus(PCI_BUS(bdf), &bus);
379 if (ret)
380 return ret;
381
382 return pci_bus_read_config(bus, bdf, offset, valuep, size);
383}
384
385int dm_pci_read_config(const struct udevice *dev, int offset,
386 unsigned long *valuep, enum pci_size_t size)
387{
388 const struct udevice *bus;
389
390 for (bus = dev; device_is_on_pci_bus(bus);)
391 bus = bus->parent;
392 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
393 size);
394}
395
396int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
397{
398 unsigned long value;
399 int ret;
400
401 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
402 if (ret)
403 return ret;
404 *valuep = value;
405
406 return 0;
407}
408
409int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
410{
411 unsigned long value;
412 int ret;
413
414 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
415 if (ret)
416 return ret;
417 *valuep = value;
418
419 return 0;
420}
421
422int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
423{
424 unsigned long value;
425 int ret;
426
427 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
428 if (ret)
429 return ret;
430 *valuep = value;
431
432 return 0;
433}
434
435int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
436{
437 unsigned long value;
438 int ret;
439
440 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
441 if (ret)
442 return ret;
443 *valuep = value;
444
445 return 0;
446}
447
448int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
449{
450 unsigned long value;
451 int ret;
452
453 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
454 if (ret)
455 return ret;
456 *valuep = value;
457
458 return 0;
459}
460
461int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
462{
463 unsigned long value;
464 int ret;
465
466 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
467 if (ret)
468 return ret;
469 *valuep = value;
470
471 return 0;
472}
473
474int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
475{
476 u8 val;
477 int ret;
478
479 ret = dm_pci_read_config8(dev, offset, &val);
480 if (ret)
481 return ret;
482 val &= ~clr;
483 val |= set;
484
485 return dm_pci_write_config8(dev, offset, val);
486}
487
488int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
489{
490 u16 val;
491 int ret;
492
493 ret = dm_pci_read_config16(dev, offset, &val);
494 if (ret)
495 return ret;
496 val &= ~clr;
497 val |= set;
498
499 return dm_pci_write_config16(dev, offset, val);
500}
501
502int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
503{
504 u32 val;
505 int ret;
506
507 ret = dm_pci_read_config32(dev, offset, &val);
508 if (ret)
509 return ret;
510 val &= ~clr;
511 val |= set;
512
513 return dm_pci_write_config32(dev, offset, val);
514}
515
516static void set_vga_bridge_bits(struct udevice *dev)
517{
518 struct udevice *parent = dev->parent;
519 u16 bc;
520
521 while (dev_seq(parent) != 0) {
522 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
523 bc |= PCI_BRIDGE_CTL_VGA;
524 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
525 parent = parent->parent;
526 }
527}
528
529int pci_auto_config_devices(struct udevice *bus)
530{
531 struct pci_controller *hose = dev_get_uclass_priv(bus);
532 struct pci_child_plat *pplat;
533 unsigned int sub_bus;
534 struct udevice *dev;
535 int ret;
536
537 sub_bus = dev_seq(bus);
538 debug("%s: start\n", __func__);
539 pciauto_config_init(hose);
540 for (ret = device_find_first_child(bus, &dev);
541 !ret && dev;
542 ret = device_find_next_child(&dev)) {
543 unsigned int max_bus;
544 int ret;
545
546 debug("%s: device %s\n", __func__, dev->name);
547 if (dev_has_ofnode(dev) &&
548 dev_read_bool(dev, "pci,no-autoconfig"))
549 continue;
550 ret = dm_pciauto_config_device(dev);
551 if (ret < 0)
552 return log_msg_ret("auto", ret);
553 max_bus = ret;
554 sub_bus = max(sub_bus, max_bus);
555
556 if (dev_get_parent(dev) == bus)
557 continue;
558
559 pplat = dev_get_parent_plat(dev);
560 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
561 set_vga_bridge_bits(dev);
562 }
563 debug("%s: done\n", __func__);
564
565 return log_msg_ret("sub", sub_bus);
566}
567
568int pci_generic_mmap_write_config(
569 const struct udevice *bus,
570 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
571 void **addrp),
572 pci_dev_t bdf,
573 uint offset,
574 ulong value,
575 enum pci_size_t size)
576{
577 void *address;
578
579 if (addr_f(bus, bdf, offset, &address) < 0)
580 return 0;
581
582 switch (size) {
583 case PCI_SIZE_8:
584 writeb(value, address);
585 return 0;
586 case PCI_SIZE_16:
587 writew(value, address);
588 return 0;
589 case PCI_SIZE_32:
590 writel(value, address);
591 return 0;
592 default:
593 return -EINVAL;
594 }
595}
596
597int pci_generic_mmap_read_config(
598 const struct udevice *bus,
599 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
600 void **addrp),
601 pci_dev_t bdf,
602 uint offset,
603 ulong *valuep,
604 enum pci_size_t size)
605{
606 void *address;
607
608 if (addr_f(bus, bdf, offset, &address) < 0) {
609 *valuep = pci_get_ff(size);
610 return 0;
611 }
612
613 switch (size) {
614 case PCI_SIZE_8:
615 *valuep = readb(address);
616 return 0;
617 case PCI_SIZE_16:
618 *valuep = readw(address);
619 return 0;
620 case PCI_SIZE_32:
621 *valuep = readl(address);
622 return 0;
623 default:
624 return -EINVAL;
625 }
626}
627
628int dm_pci_hose_probe_bus(struct udevice *bus)
629{
630 u8 header_type;
631 int sub_bus;
632 int ret;
633 int ea_pos;
634 u8 reg;
635
636 debug("%s\n", __func__);
637
638 dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
639 header_type &= 0x7f;
640 if (header_type != PCI_HEADER_TYPE_BRIDGE) {
641 debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
642 __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
643 return log_msg_ret("probe", -EINVAL);
644 }
645
646 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
647 if (ea_pos) {
648 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
649 ®);
650 sub_bus = reg;
651 } else {
652 sub_bus = pci_get_bus_max() + 1;
653 }
654 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
655 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
656
657 ret = device_probe(bus);
658 if (ret) {
659 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
660 ret);
661 return log_msg_ret("probe", ret);
662 }
663
664 if (!ea_pos)
665 sub_bus = pci_get_bus_max();
666
667 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
668
669 return sub_bus;
670}
671
672
673
674
675
676
677
678
679
680
681static bool pci_match_one_id(const struct pci_device_id *id,
682 const struct pci_device_id *find)
683{
684 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
685 (id->device == PCI_ANY_ID || id->device == find->device) &&
686 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
687 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
688 !((id->class ^ find->class) & id->class_mask))
689 return true;
690
691 return false;
692}
693
694
695
696
697
698
699
700
701
702
703
704
705static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
706 uint device)
707{
708 u32 vendev;
709 int index;
710
711 for (index = 0;
712 !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
713 &vendev);
714 index++) {
715 if (vendev == PCI_VENDEV(vendor, device))
716 return true;
717 }
718
719 return false;
720}
721
722
723
724
725
726
727
728
729
730
731
732
733
734static int pci_find_and_bind_driver(struct udevice *parent,
735 struct pci_device_id *find_id,
736 pci_dev_t bdf, struct udevice **devp)
737{
738 struct pci_driver_entry *start, *entry;
739 ofnode node = ofnode_null();
740 const char *drv;
741 int n_ents;
742 int ret;
743 char name[30], *str;
744 bool bridge;
745
746 *devp = NULL;
747
748 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
749 find_id->vendor, find_id->device);
750
751
752 if (ofnode_valid(dev_ofnode(parent)))
753 pci_dev_find_ofnode(parent, bdf, &node);
754
755 if (ofnode_valid(node) && !ofnode_is_available(node)) {
756 debug("%s: Ignoring disabled device\n", __func__);
757 return log_msg_ret("dis", -EPERM);
758 }
759
760 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
761 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
762 for (entry = start; entry != start + n_ents; entry++) {
763 const struct pci_device_id *id;
764 struct udevice *dev;
765 const struct driver *drv;
766
767 for (id = entry->match;
768 id->vendor || id->subvendor || id->class_mask;
769 id++) {
770 if (!pci_match_one_id(id, find_id))
771 continue;
772
773 drv = entry->driver;
774
775
776
777
778
779
780
781 if (!(gd->flags & GD_FLG_RELOC) &&
782 !(drv->flags & DM_FLAG_PRE_RELOC))
783 return log_msg_ret("pre", -EPERM);
784
785
786
787
788
789
790
791
792
793 ret = device_bind(parent, drv, drv->name, NULL, node,
794 &dev);
795 if (ret)
796 goto error;
797 debug("%s: Match found: %s\n", __func__, drv->name);
798 dev->driver_data = id->driver_data;
799 *devp = dev;
800 return 0;
801 }
802 }
803
804 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
805
806
807
808
809
810 if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
811 !pci_need_device_pre_reloc(parent, find_id->vendor,
812 find_id->device))
813 return log_msg_ret("notbr", -EPERM);
814
815
816 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
817 PCI_FUNC(bdf));
818 str = strdup(name);
819 if (!str)
820 return -ENOMEM;
821 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
822
823 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
824 if (ret) {
825 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
826 free(str);
827 return ret;
828 }
829 debug("%s: No match found: bound generic driver instead\n", __func__);
830
831 return 0;
832
833error:
834 debug("%s: No match found: error %d\n", __func__, ret);
835 return ret;
836}
837
838__weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
839{
840}
841
842int pci_bind_bus_devices(struct udevice *bus)
843{
844 ulong vendor, device;
845 ulong header_type;
846 pci_dev_t bdf, end;
847 bool found_multi;
848 int ari_off;
849 int ret;
850
851 found_multi = false;
852 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
853 PCI_MAX_PCI_FUNCTIONS - 1);
854 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
855 bdf += PCI_BDF(0, 0, 1)) {
856 struct pci_child_plat *pplat;
857 struct udevice *dev;
858 ulong class;
859
860 if (!PCI_FUNC(bdf))
861 found_multi = false;
862 if (PCI_FUNC(bdf) && !found_multi)
863 continue;
864
865
866 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
867 PCI_SIZE_16);
868 if (ret || vendor == 0xffff || vendor == 0x0000)
869 continue;
870
871 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
872 &header_type, PCI_SIZE_8);
873
874 if (!PCI_FUNC(bdf))
875 found_multi = header_type & 0x80;
876
877 debug("%s: bus %d/%s: found device %x, function %d", __func__,
878 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
879 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
880 PCI_SIZE_16);
881 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
882 PCI_SIZE_32);
883 class >>= 8;
884
885
886 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
887 debug(": find ret=%d\n", ret);
888
889
890 if (ret == -ENODEV) {
891 struct pci_device_id find_id;
892 ulong val;
893
894 memset(&find_id, '\0', sizeof(find_id));
895 find_id.vendor = vendor;
896 find_id.device = device;
897 find_id.class = class;
898 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
899 pci_bus_read_config(bus, bdf,
900 PCI_SUBSYSTEM_VENDOR_ID,
901 &val, PCI_SIZE_32);
902 find_id.subvendor = val & 0xffff;
903 find_id.subdevice = val >> 16;
904 }
905 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
906 &dev);
907 }
908 if (ret == -EPERM)
909 continue;
910 else if (ret)
911 return ret;
912
913
914 pplat = dev_get_parent_plat(dev);
915 pplat->devfn = PCI_MASK_BUS(bdf);
916 pplat->vendor = vendor;
917 pplat->device = device;
918 pplat->class = class;
919
920 if (IS_ENABLED(CONFIG_PCI_ARID)) {
921 ari_off = dm_pci_find_ext_capability(dev,
922 PCI_EXT_CAP_ID_ARI);
923 if (ari_off) {
924 u16 ari_cap;
925
926
927
928
929
930 dm_pci_read_config16(dev, ari_off + 4,
931 &ari_cap);
932
933
934
935
936 if (ari_cap & 0xff00) {
937 bdf = PCI_BDF(PCI_BUS(bdf),
938 PCI_DEV(ari_cap),
939 PCI_FUNC(ari_cap));
940 bdf = bdf - 0x100;
941 }
942 }
943 }
944
945 board_pci_fixup_dev(bus, dev);
946 }
947
948 return 0;
949}
950
951static void decode_regions(struct pci_controller *hose, ofnode parent_node,
952 ofnode node)
953{
954 int pci_addr_cells, addr_cells, size_cells;
955 int cells_per_record;
956 struct bd_info *bd;
957 const u32 *prop;
958 int max_regions;
959 int len;
960 int i;
961
962 prop = ofnode_get_property(node, "ranges", &len);
963 if (!prop) {
964 debug("%s: Cannot decode regions\n", __func__);
965 return;
966 }
967
968 pci_addr_cells = ofnode_read_simple_addr_cells(node);
969 addr_cells = ofnode_read_simple_addr_cells(parent_node);
970 size_cells = ofnode_read_simple_size_cells(node);
971
972
973 len /= sizeof(u32);
974 cells_per_record = pci_addr_cells + addr_cells + size_cells;
975 hose->region_count = 0;
976 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
977 cells_per_record);
978
979
980 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
981 hose->regions = (struct pci_region *)
982 calloc(1, max_regions * sizeof(struct pci_region));
983
984 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
985 u64 pci_addr, addr, size;
986 int space_code;
987 u32 flags;
988 int type;
989 int pos;
990
991 if (len < cells_per_record)
992 break;
993 flags = fdt32_to_cpu(prop[0]);
994 space_code = (flags >> 24) & 3;
995 pci_addr = fdtdec_get_number(prop + 1, 2);
996 prop += pci_addr_cells;
997 addr = fdtdec_get_number(prop, addr_cells);
998 prop += addr_cells;
999 size = fdtdec_get_number(prop, size_cells);
1000 prop += size_cells;
1001 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
1002 __func__, hose->region_count, pci_addr, addr, size, space_code);
1003 if (space_code & 2) {
1004 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
1005 PCI_REGION_MEM;
1006 } else if (space_code & 1) {
1007 type = PCI_REGION_IO;
1008 } else {
1009 continue;
1010 }
1011
1012 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
1013 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
1014 debug(" - beyond the 32-bit boundary, ignoring\n");
1015 continue;
1016 }
1017
1018 pos = -1;
1019 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
1020 for (i = 0; i < hose->region_count; i++) {
1021 if (hose->regions[i].flags == type)
1022 pos = i;
1023 }
1024 }
1025
1026 if (pos == -1)
1027 pos = hose->region_count++;
1028 debug(" - type=%d, pos=%d\n", type, pos);
1029 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
1030 }
1031
1032
1033 bd = gd->bd;
1034 if (!bd)
1035 return;
1036
1037 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1038 if (bd->bi_dram[i].size) {
1039 phys_addr_t start = bd->bi_dram[i].start;
1040
1041 if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
1042 start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
1043
1044 pci_set_region(hose->regions + hose->region_count++,
1045 start, start, bd->bi_dram[i].size,
1046 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1047 }
1048 }
1049
1050 return;
1051}
1052
1053static int pci_uclass_pre_probe(struct udevice *bus)
1054{
1055 struct pci_controller *hose;
1056 struct uclass *uc;
1057 int ret;
1058
1059 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1060 bus->parent->name);
1061 hose = dev_get_uclass_priv(bus);
1062
1063
1064
1065
1066
1067
1068
1069 if (dev_seq(bus) == -1) {
1070 ret = uclass_get(UCLASS_PCI, &uc);
1071 if (ret)
1072 return ret;
1073 bus->seq_ = uclass_find_next_free_seq(uc);
1074 }
1075
1076
1077 if (!device_is_on_pci_bus(bus)) {
1078 hose->ctlr = bus;
1079 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
1080 } else {
1081 struct pci_controller *parent_hose;
1082
1083 parent_hose = dev_get_uclass_priv(bus->parent);
1084 hose->ctlr = parent_hose->bus;
1085 }
1086
1087 hose->bus = bus;
1088 hose->first_busno = dev_seq(bus);
1089 hose->last_busno = dev_seq(bus);
1090 if (dev_has_ofnode(bus)) {
1091 hose->skip_auto_config_until_reloc =
1092 dev_read_bool(bus,
1093 "u-boot,skip-auto-config-until-reloc");
1094 }
1095
1096 return 0;
1097}
1098
1099static int pci_uclass_post_probe(struct udevice *bus)
1100{
1101 struct pci_controller *hose = dev_get_uclass_priv(bus);
1102 int ret;
1103
1104 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1105 ret = pci_bind_bus_devices(bus);
1106 if (ret)
1107 return log_msg_ret("bind", ret);
1108
1109 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1110 (!hose->skip_auto_config_until_reloc ||
1111 (gd->flags & GD_FLG_RELOC))) {
1112 ret = pci_auto_config_devices(bus);
1113 if (ret < 0)
1114 return log_msg_ret("cfg", ret);
1115 }
1116
1117#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1132 ret = fsp_init_phase_pci();
1133 if (ret)
1134 return log_msg_ret("fsp", ret);
1135 }
1136#endif
1137
1138 return 0;
1139}
1140
1141static int pci_uclass_child_post_bind(struct udevice *dev)
1142{
1143 struct pci_child_plat *pplat;
1144
1145 if (!dev_has_ofnode(dev))
1146 return 0;
1147
1148 pplat = dev_get_parent_plat(dev);
1149
1150
1151 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1152
1153
1154 pplat->devfn = pci_get_devfn(dev);
1155
1156 return 0;
1157}
1158
1159static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1160 uint offset, ulong *valuep,
1161 enum pci_size_t size)
1162{
1163 struct pci_controller *hose = dev_get_uclass_priv(bus);
1164
1165 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1166}
1167
1168static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1169 uint offset, ulong value,
1170 enum pci_size_t size)
1171{
1172 struct pci_controller *hose = dev_get_uclass_priv(bus);
1173
1174 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1175}
1176
1177static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1178{
1179 struct udevice *dev;
1180 int ret = 0;
1181
1182
1183
1184
1185
1186 do {
1187 device_find_first_child(bus, &dev);
1188 if (dev) {
1189 *devp = dev;
1190 return 0;
1191 }
1192 ret = uclass_next_device(&bus);
1193 if (ret)
1194 return ret;
1195 } while (bus);
1196
1197 return 0;
1198}
1199
1200int pci_find_next_device(struct udevice **devp)
1201{
1202 struct udevice *child = *devp;
1203 struct udevice *bus = child->parent;
1204 int ret;
1205
1206
1207 *devp = NULL;
1208 while (child) {
1209 device_find_next_child(&child);
1210 if (child) {
1211 *devp = child;
1212 return 0;
1213 }
1214 }
1215
1216
1217 ret = uclass_next_device(&bus);
1218 if (ret)
1219 return ret;
1220
1221 return bus ? skip_to_next_device(bus, devp) : 0;
1222}
1223
1224int pci_find_first_device(struct udevice **devp)
1225{
1226 struct udevice *bus;
1227 int ret;
1228
1229 *devp = NULL;
1230 ret = uclass_first_device(UCLASS_PCI, &bus);
1231 if (ret)
1232 return ret;
1233
1234 return skip_to_next_device(bus, devp);
1235}
1236
1237ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1238{
1239 switch (size) {
1240 case PCI_SIZE_8:
1241 return (value >> ((offset & 3) * 8)) & 0xff;
1242 case PCI_SIZE_16:
1243 return (value >> ((offset & 2) * 8)) & 0xffff;
1244 default:
1245 return value;
1246 }
1247}
1248
1249ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1250 enum pci_size_t size)
1251{
1252 uint off_mask;
1253 uint val_mask, shift;
1254 ulong ldata, mask;
1255
1256 switch (size) {
1257 case PCI_SIZE_8:
1258 off_mask = 3;
1259 val_mask = 0xff;
1260 break;
1261 case PCI_SIZE_16:
1262 off_mask = 2;
1263 val_mask = 0xffff;
1264 break;
1265 default:
1266 return value;
1267 }
1268 shift = (offset & off_mask) * 8;
1269 ldata = (value & val_mask) << shift;
1270 mask = val_mask << shift;
1271 value = (old & ~mask) | ldata;
1272
1273 return value;
1274}
1275
1276int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1277{
1278 int pci_addr_cells, addr_cells, size_cells;
1279 int cells_per_record;
1280 const u32 *prop;
1281 int len;
1282 int i = 0;
1283
1284 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1285 if (!prop) {
1286 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1287 dev->name);
1288 return -EINVAL;
1289 }
1290
1291 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1292 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1293 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1294
1295
1296 len /= sizeof(u32);
1297 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1298 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1299 cells_per_record);
1300
1301 while (len) {
1302 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1303 prop += pci_addr_cells;
1304 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1305 prop += addr_cells;
1306 memp->size = fdtdec_get_number(prop, size_cells);
1307 prop += size_cells;
1308
1309 if (i == index)
1310 return 0;
1311 i++;
1312 len -= cells_per_record;
1313 }
1314
1315 return -EINVAL;
1316}
1317
1318int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1319 struct pci_region **memp, struct pci_region **prefp)
1320{
1321 struct udevice *bus = pci_get_controller(dev);
1322 struct pci_controller *hose = dev_get_uclass_priv(bus);
1323 int i;
1324
1325 *iop = NULL;
1326 *memp = NULL;
1327 *prefp = NULL;
1328 for (i = 0; i < hose->region_count; i++) {
1329 switch (hose->regions[i].flags) {
1330 case PCI_REGION_IO:
1331 if (!*iop || (*iop)->size < hose->regions[i].size)
1332 *iop = hose->regions + i;
1333 break;
1334 case PCI_REGION_MEM:
1335 if (!*memp || (*memp)->size < hose->regions[i].size)
1336 *memp = hose->regions + i;
1337 break;
1338 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1339 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1340 *prefp = hose->regions + i;
1341 break;
1342 }
1343 }
1344
1345 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1346}
1347
1348u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1349{
1350 u32 addr;
1351 int bar;
1352
1353 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1354 dm_pci_read_config32(dev, bar, &addr);
1355
1356
1357
1358
1359
1360 if (addr == 0xffffffff)
1361 return addr;
1362 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1363 return addr & PCI_BASE_ADDRESS_IO_MASK;
1364 else
1365 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1366}
1367
1368void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1369{
1370 int bar;
1371
1372 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1373 dm_pci_write_config32(dev, bar, addr);
1374}
1375
1376static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1377 pci_addr_t bus_addr, unsigned long flags,
1378 unsigned long skip_mask, phys_addr_t *pa)
1379{
1380 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1381 struct pci_region *res;
1382 int i;
1383
1384 if (hose->region_count == 0) {
1385 *pa = bus_addr;
1386 return 0;
1387 }
1388
1389 for (i = 0; i < hose->region_count; i++) {
1390 res = &hose->regions[i];
1391
1392 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1393 continue;
1394
1395 if (res->flags & skip_mask)
1396 continue;
1397
1398 if (bus_addr >= res->bus_start &&
1399 (bus_addr - res->bus_start) < res->size) {
1400 *pa = (bus_addr - res->bus_start + res->phys_start);
1401 return 0;
1402 }
1403 }
1404
1405 return 1;
1406}
1407
1408phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1409 unsigned long flags)
1410{
1411 phys_addr_t phys_addr = 0;
1412 struct udevice *ctlr;
1413 int ret;
1414
1415
1416 ctlr = pci_get_controller(dev);
1417
1418
1419
1420
1421
1422 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1423 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1424 flags, PCI_REGION_SYS_MEMORY,
1425 &phys_addr);
1426 if (!ret)
1427 return phys_addr;
1428 }
1429
1430 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1431
1432 if (ret)
1433 puts("pci_hose_bus_to_phys: invalid physical address\n");
1434
1435 return phys_addr;
1436}
1437
1438static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1439 unsigned long flags, unsigned long skip_mask,
1440 pci_addr_t *ba)
1441{
1442 struct pci_region *res;
1443 struct udevice *ctlr;
1444 pci_addr_t bus_addr;
1445 int i;
1446 struct pci_controller *hose;
1447
1448
1449 ctlr = pci_get_controller(dev);
1450 hose = dev_get_uclass_priv(ctlr);
1451
1452 if (hose->region_count == 0) {
1453 *ba = phys_addr;
1454 return 0;
1455 }
1456
1457 for (i = 0; i < hose->region_count; i++) {
1458 res = &hose->regions[i];
1459
1460 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1461 continue;
1462
1463 if (res->flags & skip_mask)
1464 continue;
1465
1466 bus_addr = phys_addr - res->phys_start + res->bus_start;
1467
1468 if (bus_addr >= res->bus_start &&
1469 (bus_addr - res->bus_start) < res->size) {
1470 *ba = bus_addr;
1471 return 0;
1472 }
1473 }
1474
1475 return 1;
1476}
1477
1478pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1479 unsigned long flags)
1480{
1481 pci_addr_t bus_addr = 0;
1482 int ret;
1483
1484
1485
1486
1487
1488 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1489 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1490 PCI_REGION_SYS_MEMORY, &bus_addr);
1491 if (!ret)
1492 return bus_addr;
1493 }
1494
1495 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1496
1497 if (ret)
1498 puts("pci_hose_phys_to_bus: invalid physical address\n");
1499
1500 return bus_addr;
1501}
1502
1503static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1504 struct pci_child_plat *pdata)
1505{
1506 phys_addr_t addr = 0;
1507
1508
1509
1510
1511
1512 if (pdata->is_virtfn) {
1513 size_t sz;
1514 u32 ea_entry;
1515
1516
1517 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1518 sz = ea_entry & PCI_EA_FIELD_MASK;
1519
1520 sz |= (~PCI_EA_FIELD_MASK);
1521
1522 if (ea_entry & PCI_EA_IS_64) {
1523
1524 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1525 sz |= ((u64)ea_entry) << 32;
1526 }
1527
1528 addr = (pdata->virtid - 1) * (sz + 1);
1529 }
1530
1531 return addr;
1532}
1533
1534static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1535 int ea_off, struct pci_child_plat *pdata)
1536{
1537 int ea_cnt, i, entry_size;
1538 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1539 u32 ea_entry;
1540 phys_addr_t addr;
1541
1542 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1543
1544
1545
1546
1547
1548 if (pdata->is_virtfn)
1549 bar_id += PCI_EA_BEI_VF_BAR0;
1550 }
1551
1552
1553 dm_pci_read_config32(dev, ea_off, &ea_entry);
1554 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1555 ea_off += PCI_EA_FIRST_ENT;
1556
1557 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1558
1559 dm_pci_read_config32(dev, ea_off, &ea_entry);
1560 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1561
1562 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1563 continue;
1564
1565
1566 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1567 addr = ea_entry & PCI_EA_FIELD_MASK;
1568 if (ea_entry & PCI_EA_IS_64) {
1569
1570 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1571 addr |= ((u64)ea_entry) << 32;
1572 }
1573
1574 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1575 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1576
1577
1578 return map_physmem(addr, 0, flags);
1579 }
1580
1581 return 0;
1582}
1583
1584void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1585{
1586 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1587 struct udevice *udev = dev;
1588 pci_addr_t pci_bus_addr;
1589 u32 bar_response;
1590 int ea_off;
1591
1592 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1593
1594
1595
1596
1597 if (pdata->is_virtfn)
1598 udev = pdata->pfdev;
1599 }
1600
1601
1602
1603
1604
1605
1606
1607 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1608 if (ea_off)
1609 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1610
1611
1612 dm_pci_read_config32(udev, bar, &bar_response);
1613 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1614
1615
1616
1617
1618
1619
1620
1621 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1622}
1623
1624static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1625{
1626 int ttl = PCI_FIND_CAP_TTL;
1627 u8 id;
1628 u16 ent;
1629
1630 dm_pci_read_config8(dev, pos, &pos);
1631
1632 while (ttl--) {
1633 if (pos < PCI_STD_HEADER_SIZEOF)
1634 break;
1635 pos &= ~3;
1636 dm_pci_read_config16(dev, pos, &ent);
1637
1638 id = ent & 0xff;
1639 if (id == 0xff)
1640 break;
1641 if (id == cap)
1642 return pos;
1643 pos = (ent >> 8);
1644 }
1645
1646 return 0;
1647}
1648
1649int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1650{
1651 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1652 cap);
1653}
1654
1655int dm_pci_find_capability(struct udevice *dev, int cap)
1656{
1657 u16 status;
1658 u8 header_type;
1659 u8 pos;
1660
1661 dm_pci_read_config16(dev, PCI_STATUS, &status);
1662 if (!(status & PCI_STATUS_CAP_LIST))
1663 return 0;
1664
1665 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1666 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1667 pos = PCI_CB_CAPABILITY_LIST;
1668 else
1669 pos = PCI_CAPABILITY_LIST;
1670
1671 return _dm_pci_find_next_capability(dev, pos, cap);
1672}
1673
1674int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1675{
1676 u32 header;
1677 int ttl;
1678 int pos = PCI_CFG_SPACE_SIZE;
1679
1680
1681 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1682
1683 if (start)
1684 pos = start;
1685
1686 dm_pci_read_config32(dev, pos, &header);
1687
1688
1689
1690
1691 if (header == 0)
1692 return 0;
1693
1694 while (ttl--) {
1695 if (PCI_EXT_CAP_ID(header) == cap)
1696 return pos;
1697
1698 pos = PCI_EXT_CAP_NEXT(header);
1699 if (pos < PCI_CFG_SPACE_SIZE)
1700 break;
1701
1702 dm_pci_read_config32(dev, pos, &header);
1703 }
1704
1705 return 0;
1706}
1707
1708int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1709{
1710 return dm_pci_find_next_ext_capability(dev, 0, cap);
1711}
1712
1713int dm_pci_flr(struct udevice *dev)
1714{
1715 int pcie_off;
1716 u32 cap;
1717
1718
1719 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1720 if (!pcie_off)
1721 return -ENOENT;
1722
1723
1724 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1725 if (!(cap & PCI_EXP_DEVCAP_FLR))
1726 return -ENOENT;
1727
1728 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1729 PCI_EXP_DEVCTL_BCR_FLR);
1730
1731
1732 mdelay(100);
1733
1734 return 0;
1735}
1736
1737#if defined(CONFIG_PCI_SRIOV)
1738int pci_sriov_init(struct udevice *pdev, int vf_en)
1739{
1740 u16 vendor, device;
1741 struct udevice *bus;
1742 struct udevice *dev;
1743 pci_dev_t bdf;
1744 u16 ctrl;
1745 u16 num_vfs;
1746 u16 total_vf;
1747 u16 vf_offset;
1748 u16 vf_stride;
1749 int vf, ret;
1750 int pos;
1751
1752 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1753 if (!pos) {
1754 debug("Error: SRIOV capability not found\n");
1755 return -ENOENT;
1756 }
1757
1758 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1759
1760 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1761 if (vf_en > total_vf)
1762 vf_en = total_vf;
1763 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1764
1765 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1766 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1767
1768 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1769 if (num_vfs > vf_en)
1770 num_vfs = vf_en;
1771
1772 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1773 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1774
1775 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1776 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1777
1778 bdf = dm_pci_get_bdf(pdev);
1779
1780 pci_get_bus(PCI_BUS(bdf), &bus);
1781
1782 if (!bus)
1783 return -ENODEV;
1784
1785 bdf += PCI_BDF(0, 0, vf_offset);
1786
1787 for (vf = 0; vf < num_vfs; vf++) {
1788 struct pci_child_plat *pplat;
1789 ulong class;
1790
1791 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1792 &class, PCI_SIZE_16);
1793
1794 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1795 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1796
1797
1798 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1799
1800 if (ret == -ENODEV) {
1801 struct pci_device_id find_id;
1802
1803 memset(&find_id, '\0', sizeof(find_id));
1804 find_id.vendor = vendor;
1805 find_id.device = device;
1806 find_id.class = class;
1807
1808 ret = pci_find_and_bind_driver(bus, &find_id,
1809 bdf, &dev);
1810
1811 if (ret)
1812 return ret;
1813 }
1814
1815
1816 pplat = dev_get_parent_plat(dev);
1817 pplat->devfn = PCI_MASK_BUS(bdf);
1818 pplat->vendor = vendor;
1819 pplat->device = device;
1820 pplat->class = class;
1821 pplat->is_virtfn = true;
1822 pplat->pfdev = pdev;
1823 pplat->virtid = vf * vf_stride + vf_offset;
1824
1825 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1826 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1827 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1828 bdf += PCI_BDF(0, 0, vf_stride);
1829 }
1830
1831 return 0;
1832}
1833
1834int pci_sriov_get_totalvfs(struct udevice *pdev)
1835{
1836 u16 total_vf;
1837 int pos;
1838
1839 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1840 if (!pos) {
1841 debug("Error: SRIOV capability not found\n");
1842 return -ENOENT;
1843 }
1844
1845 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1846
1847 return total_vf;
1848}
1849#endif
1850
1851UCLASS_DRIVER(pci) = {
1852 .id = UCLASS_PCI,
1853 .name = "pci",
1854 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1855 .post_bind = dm_scan_fdt_dev,
1856 .pre_probe = pci_uclass_pre_probe,
1857 .post_probe = pci_uclass_post_probe,
1858 .child_post_bind = pci_uclass_child_post_bind,
1859 .per_device_auto = sizeof(struct pci_controller),
1860 .per_child_plat_auto = sizeof(struct pci_child_plat),
1861};
1862
1863static const struct dm_pci_ops pci_bridge_ops = {
1864 .read_config = pci_bridge_read_config,
1865 .write_config = pci_bridge_write_config,
1866};
1867
1868static const struct udevice_id pci_bridge_ids[] = {
1869 { .compatible = "pci-bridge" },
1870 { }
1871};
1872
1873U_BOOT_DRIVER(pci_bridge_drv) = {
1874 .name = "pci_bridge_drv",
1875 .id = UCLASS_PCI,
1876 .of_match = pci_bridge_ids,
1877 .ops = &pci_bridge_ops,
1878};
1879
1880UCLASS_DRIVER(pci_generic) = {
1881 .id = UCLASS_PCI_GENERIC,
1882 .name = "pci_generic",
1883};
1884
1885static const struct udevice_id pci_generic_ids[] = {
1886 { .compatible = "pci-generic" },
1887 { }
1888};
1889
1890U_BOOT_DRIVER(pci_generic_drv) = {
1891 .name = "pci_generic_drv",
1892 .id = UCLASS_PCI_GENERIC,
1893 .of_match = pci_generic_ids,
1894};
1895
1896int pci_init(void)
1897{
1898 struct udevice *bus;
1899
1900
1901
1902
1903
1904 for (uclass_first_device_check(UCLASS_PCI, &bus);
1905 bus;
1906 uclass_next_device_check(&bus)) {
1907 ;
1908 }
1909
1910 return 0;
1911}
1912