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7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <generic-phy.h>
11#include <pci.h>
12#include <malloc.h>
13#include <asm/io.h>
14#include <dm/device_compat.h>
15#include <linux/delay.h>
16#include <linux/log2.h>
17
18#define EP_PERST_SOURCE_SELECT_SHIFT 2
19#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
20#define EP_MODE_SURVIVE_PERST_SHIFT 1
21#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
22#define RC_PCIE_RST_OUTPUT_SHIFT 0
23#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
24
25#define CFG_IND_ADDR_MASK 0x00001ffc
26
27#define CFG_ADDR_BUS_NUM_SHIFT 20
28#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
29#define CFG_ADDR_DEV_NUM_SHIFT 15
30#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
31#define CFG_ADDR_FUNC_NUM_SHIFT 12
32#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
33#define CFG_ADDR_REG_NUM_SHIFT 2
34#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
35#define CFG_ADDR_CFG_TYPE_SHIFT 0
36#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
37
38#define IPROC_PCI_PM_CAP 0x48
39#define IPROC_PCI_PM_CAP_MASK 0xffff
40#define IPROC_PCI_EXP_CAP 0xac
41
42#define IPROC_PCIE_REG_INVALID 0xffff
43
44#define PCI_EXP_TYPE_ROOT_PORT 0x4
45#define PCI_EXP_RTCTL 28
46
47#define PCI_EXP_RTCAP_CRSVIS 0x0001
48
49#define PCI_EXP_LNKSTA 18
50#define PCI_EXP_LNKSTA_NLW 0x03f0
51
52#define PCIE_PHYLINKUP_SHIFT 3
53#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
54#define PCIE_DL_ACTIVE_SHIFT 2
55#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
56
57
58#define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
59
60
61
62
63
64#define MAX_NUM_OB_WINDOW_SIZES 4
65
66#define OARR_VALID_SHIFT 0
67#define OARR_VALID BIT(OARR_VALID_SHIFT)
68#define OARR_SIZE_CFG_SHIFT 1
69
70
71
72
73
74#define MAX_NUM_IB_REGION_SIZES 9
75
76#define IMAP_VALID_SHIFT 0
77#define IMAP_VALID BIT(IMAP_VALID_SHIFT)
78
79#define APB_ERR_EN_SHIFT 0
80#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
81
82
83
84
85enum iproc_pcie_reg {
86
87 IPROC_PCIE_CLK_CTRL = 0,
88
89
90
91
92
93 IPROC_PCIE_MSI_GIC_MODE,
94
95
96
97
98
99
100 IPROC_PCIE_MSI_BASE_ADDR,
101 IPROC_PCIE_MSI_WINDOW_SIZE,
102
103
104
105
106
107
108 IPROC_PCIE_MSI_ADDR_LO,
109 IPROC_PCIE_MSI_ADDR_HI,
110
111
112 IPROC_PCIE_MSI_EN_CFG,
113
114
115 IPROC_PCIE_CFG_IND_ADDR,
116 IPROC_PCIE_CFG_IND_DATA,
117
118
119 IPROC_PCIE_CFG_ADDR,
120 IPROC_PCIE_CFG_DATA,
121
122
123 IPROC_PCIE_INTX_EN,
124 IPROC_PCIE_INTX_CSR,
125
126
127 IPROC_PCIE_OARR0,
128 IPROC_PCIE_OMAP0,
129 IPROC_PCIE_OARR1,
130 IPROC_PCIE_OMAP1,
131 IPROC_PCIE_OARR2,
132 IPROC_PCIE_OMAP2,
133 IPROC_PCIE_OARR3,
134 IPROC_PCIE_OMAP3,
135
136
137 IPROC_PCIE_IARR0,
138 IPROC_PCIE_IMAP0,
139 IPROC_PCIE_IARR1,
140 IPROC_PCIE_IMAP1,
141 IPROC_PCIE_IARR2,
142 IPROC_PCIE_IMAP2,
143 IPROC_PCIE_IARR3,
144 IPROC_PCIE_IMAP3,
145 IPROC_PCIE_IARR4,
146 IPROC_PCIE_IMAP4,
147
148
149 IPROC_PCIE_CFG_RD_STATUS,
150
151
152 IPROC_PCIE_LINK_STATUS,
153
154
155 IPROC_PCIE_APB_ERR_EN,
156
157
158 IPROC_PCIE_ORDERING_CFG,
159 IPROC_PCIE_IMAP0_RO_CONTROL,
160 IPROC_PCIE_IMAP1_RO_CONTROL,
161 IPROC_PCIE_IMAP2_RO_CONTROL,
162 IPROC_PCIE_IMAP3_RO_CONTROL,
163 IPROC_PCIE_IMAP4_RO_CONTROL,
164
165
166 IPROC_PCIE_MAX_NUM_REG,
167};
168
169
170static const u16 iproc_pcie_reg_paxb_v2[] = {
171 [IPROC_PCIE_CLK_CTRL] = 0x000,
172 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
173 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
174 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
175 [IPROC_PCIE_CFG_DATA] = 0x1fc,
176 [IPROC_PCIE_INTX_EN] = 0x330,
177 [IPROC_PCIE_INTX_CSR] = 0x334,
178 [IPROC_PCIE_OARR0] = 0xd20,
179 [IPROC_PCIE_OMAP0] = 0xd40,
180 [IPROC_PCIE_OARR1] = 0xd28,
181 [IPROC_PCIE_OMAP1] = 0xd48,
182 [IPROC_PCIE_OARR2] = 0xd60,
183 [IPROC_PCIE_OMAP2] = 0xd68,
184 [IPROC_PCIE_OARR3] = 0xdf0,
185 [IPROC_PCIE_OMAP3] = 0xdf8,
186 [IPROC_PCIE_IARR0] = 0xd00,
187 [IPROC_PCIE_IMAP0] = 0xc00,
188 [IPROC_PCIE_IARR2] = 0xd10,
189 [IPROC_PCIE_IMAP2] = 0xcc0,
190 [IPROC_PCIE_IARR3] = 0xe00,
191 [IPROC_PCIE_IMAP3] = 0xe08,
192 [IPROC_PCIE_IARR4] = 0xe68,
193 [IPROC_PCIE_IMAP4] = 0xe70,
194 [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
195 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
196 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
197 [IPROC_PCIE_ORDERING_CFG] = 0x2000,
198 [IPROC_PCIE_IMAP0_RO_CONTROL] = 0x201c,
199 [IPROC_PCIE_IMAP1_RO_CONTROL] = 0x2020,
200 [IPROC_PCIE_IMAP2_RO_CONTROL] = 0x2024,
201 [IPROC_PCIE_IMAP3_RO_CONTROL] = 0x2028,
202 [IPROC_PCIE_IMAP4_RO_CONTROL] = 0x202c,
203};
204
205
206static const u16 iproc_pcie_reg_paxc_v2[] = {
207 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
208 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
209 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
210 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
211 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
212 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
213 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
214 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
215 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
216 [IPROC_PCIE_CFG_DATA] = 0x1fc,
217};
218
219
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221
222
223static const u16 iproc_pcie_corrupt_cap_did[] = {
224 0x16cd,
225 0x16f0,
226 0xd802,
227 0xd804
228};
229
230enum iproc_pcie_type {
231 IPROC_PCIE_PAXB_V2,
232 IPROC_PCIE_PAXC,
233 IPROC_PCIE_PAXC_V2,
234};
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242
243struct iproc_pcie_ob {
244 resource_size_t axi_offset;
245 unsigned int nr_windows;
246};
247
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251
252
253struct iproc_pcie_ib {
254 unsigned int nr_regions;
255};
256
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261
262
263struct iproc_pcie_ob_map {
264 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
265 unsigned int nr_sizes;
266};
267
268static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
269 {
270
271 .window_sizes = { 128, 256 },
272 .nr_sizes = 2,
273 },
274 {
275
276 .window_sizes = { 128, 256 },
277 .nr_sizes = 2,
278 },
279 {
280
281 .window_sizes = { 128, 256, 512, 1024 },
282 .nr_sizes = 4,
283 },
284 {
285
286 .window_sizes = { 128, 256, 512, 1024 },
287 .nr_sizes = 4,
288 },
289};
290
291
292
293
294enum iproc_pcie_ib_map_type {
295
296 IPROC_PCIE_IB_MAP_MEM = 0,
297
298
299 IPROC_PCIE_IB_MAP_IO,
300
301
302 IPROC_PCIE_IB_MAP_INVALID
303};
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317
318struct iproc_pcie_ib_map {
319 enum iproc_pcie_ib_map_type type;
320 unsigned int size_unit;
321 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
322 unsigned int nr_sizes;
323 unsigned int nr_windows;
324 u16 imap_addr_offset;
325 u16 imap_window_offset;
326};
327
328static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
329 {
330
331 .type = IPROC_PCIE_IB_MAP_IO,
332 .size_unit = SZ_1K,
333 .region_sizes = { 32 },
334 .nr_sizes = 1,
335 .nr_windows = 8,
336 .imap_addr_offset = 0x40,
337 .imap_window_offset = 0x4,
338 },
339 {
340
341 .type = IPROC_PCIE_IB_MAP_INVALID,
342 },
343 {
344
345 .type = IPROC_PCIE_IB_MAP_MEM,
346 .size_unit = SZ_1M,
347 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
348 16384 },
349 .nr_sizes = 9,
350 .nr_windows = 1,
351 .imap_addr_offset = 0x4,
352 .imap_window_offset = 0x8,
353 },
354 {
355
356 .type = IPROC_PCIE_IB_MAP_MEM,
357 .size_unit = SZ_1G,
358 .region_sizes = { 1, 2, 4, 8, 16, 32 },
359 .nr_sizes = 6,
360 .nr_windows = 8,
361 .imap_addr_offset = 0x4,
362 .imap_window_offset = 0x8,
363 },
364 {
365
366 .type = IPROC_PCIE_IB_MAP_MEM,
367 .size_unit = SZ_1G,
368 .region_sizes = { 32, 64, 128, 256, 512 },
369 .nr_sizes = 5,
370 .nr_windows = 8,
371 .imap_addr_offset = 0x4,
372 .imap_window_offset = 0x8,
373 },
374};
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394
395struct iproc_pcie {
396 struct udevice *dev;
397 void __iomem *base;
398 enum iproc_pcie_type type;
399 u16 *reg_offsets;
400 bool fix_paxc_cap;
401 bool need_ob_cfg;
402 struct iproc_pcie_ob ob;
403 const struct iproc_pcie_ob_map *ob_map;
404 bool need_ib_cfg;
405 struct iproc_pcie_ib ib;
406 const struct iproc_pcie_ib_map *ib_map;
407 bool ep_is_internal;
408 struct phy phy;
409 bool link_is_active;
410 bool has_apb_err_disable;
411};
412
413static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
414{
415 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
416}
417
418static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
419 enum iproc_pcie_reg reg)
420{
421 return pcie->reg_offsets[reg];
422}
423
424static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
425 enum iproc_pcie_reg reg)
426{
427 u16 offset = iproc_pcie_reg_offset(pcie, reg);
428
429 if (iproc_pcie_reg_is_invalid(offset))
430 return 0;
431
432 return readl(pcie->base + offset);
433}
434
435static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
436 enum iproc_pcie_reg reg, u32 val)
437{
438 u16 offset = iproc_pcie_reg_offset(pcie, reg);
439
440 if (iproc_pcie_reg_is_invalid(offset))
441 return;
442
443 writel(val, pcie->base + offset);
444}
445
446static int iproc_pcie_map_ep_cfg_reg(const struct udevice *udev, pci_dev_t bdf,
447 uint where, void **paddress)
448{
449 struct iproc_pcie *pcie = dev_get_priv(udev);
450 unsigned int busno = PCI_BUS(bdf);
451 unsigned int slot = PCI_DEV(bdf);
452 unsigned int fn = PCI_FUNC(bdf);
453
454 u16 offset;
455 u32 val;
456
457
458 if (busno == 0) {
459 if (slot > 0 || fn > 0)
460 return -ENODEV;
461
462 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
463 where & CFG_IND_ADDR_MASK);
464 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
465 if (iproc_pcie_reg_is_invalid(offset))
466 return -ENODEV;
467
468 *paddress = (pcie->base + offset);
469 return 0;
470 }
471
472 if (!pcie->link_is_active)
473 return -ENODEV;
474
475
476 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
477 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
478 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
479 (where & CFG_ADDR_REG_NUM_MASK) |
480 (1 & CFG_ADDR_CFG_TYPE_MASK);
481
482 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
483 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
484
485 if (iproc_pcie_reg_is_invalid(offset))
486 return -ENODEV;
487
488 *paddress = (pcie->base + offset);
489
490 return 0;
491}
492
493static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, ulong *val)
494{
495 u32 i, dev_id;
496
497 switch (where & ~0x3) {
498 case PCI_VENDOR_ID:
499 dev_id = *val >> 16;
500
501
502
503
504
505 for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)
506 if (dev_id == iproc_pcie_corrupt_cap_did[i])
507 pcie->fix_paxc_cap = true;
508 break;
509
510 case IPROC_PCI_PM_CAP:
511 if (pcie->fix_paxc_cap) {
512
513 *val &= ~IPROC_PCI_PM_CAP_MASK;
514 *val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM;
515 }
516 break;
517
518 case IPROC_PCI_EXP_CAP:
519 if (pcie->fix_paxc_cap) {
520
521 *val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 |
522 PCI_CAP_ID_EXP;
523 }
524 break;
525
526 case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL:
527
528 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
529 break;
530
531 default:
532 break;
533 }
534}
535
536static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
537 unsigned int devfn, int where,
538 int size, u32 *val)
539{
540 void __iomem *addr;
541 int ret;
542
543 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
544 if (ret) {
545 *val = ~0;
546 return -EINVAL;
547 }
548
549 *val = readl(addr);
550
551 if (size <= 2)
552 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
553
554 return 0;
555}
556
557static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
558 unsigned int devfn, int where,
559 int size, u32 val)
560{
561 void __iomem *addr;
562 int ret;
563 u32 mask, tmp;
564
565 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
566 if (ret)
567 return -EINVAL;
568
569 if (size == 4) {
570 writel(val, addr);
571 return 0;
572 }
573
574 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
575 tmp = readl(addr) & mask;
576 tmp |= val << ((where & 0x3) * 8);
577 writel(tmp, addr);
578 return 0;
579}
580
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591
592
593static inline void iproc_pcie_apb_err_disable(const struct udevice *bus,
594 pci_dev_t bdf, bool disable)
595{
596 struct iproc_pcie *pcie = dev_get_priv(bus);
597 u32 val;
598
599 if (PCI_BUS(bdf) && pcie->has_apb_err_disable) {
600 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
601 if (disable)
602 val &= ~APB_ERR_EN;
603 else
604 val |= APB_ERR_EN;
605 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
606 }
607}
608
609static int iproc_pcie_config_read32(const struct udevice *bus, pci_dev_t bdf,
610 uint offset, ulong *valuep,
611 enum pci_size_t size)
612{
613 struct iproc_pcie *pcie = dev_get_priv(bus);
614 int ret;
615 ulong data;
616
617 iproc_pcie_apb_err_disable(bus, bdf, true);
618 ret = pci_generic_mmap_read_config(bus, iproc_pcie_map_ep_cfg_reg,
619 bdf, offset, &data, PCI_SIZE_32);
620 iproc_pcie_apb_err_disable(bus, bdf, false);
621 if (size <= PCI_SIZE_16)
622 *valuep = (data >> (8 * (offset & 3))) &
623 ((1 << (BIT(size) * 8)) - 1);
624 else
625 *valuep = data;
626
627 if (!ret && PCI_BUS(bdf) == 0)
628 iproc_pcie_fix_cap(pcie, offset, valuep);
629
630 return ret;
631}
632
633static int iproc_pcie_config_write32(struct udevice *bus, pci_dev_t bdf,
634 uint offset, ulong value,
635 enum pci_size_t size)
636{
637 void *addr;
638 ulong mask, tmp;
639 int ret;
640
641 ret = iproc_pcie_map_ep_cfg_reg(bus, bdf, offset, &addr);
642 if (ret)
643 return ret;
644
645 if (size == PCI_SIZE_32) {
646 writel(value, addr);
647 return ret;
648 }
649
650 iproc_pcie_apb_err_disable(bus, bdf, true);
651 mask = ~(((1 << (BIT(size) * 8)) - 1) << ((offset & 0x3) * 8));
652 tmp = readl(addr) & mask;
653 tmp |= (value << ((offset & 0x3) * 8));
654 writel(tmp, addr);
655 iproc_pcie_apb_err_disable(bus, bdf, false);
656
657 return ret;
658}
659
660const static struct dm_pci_ops iproc_pcie_ops = {
661 .read_config = iproc_pcie_config_read32,
662 .write_config = iproc_pcie_config_write32,
663};
664
665static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
666{
667 unsigned int reg_idx;
668 const u16 *regs;
669 u16 num_elements;
670
671 switch (pcie->type) {
672 case IPROC_PCIE_PAXC_V2:
673 pcie->ep_is_internal = true;
674 regs = iproc_pcie_reg_paxc_v2;
675 num_elements = ARRAY_SIZE(iproc_pcie_reg_paxc_v2);
676 break;
677 case IPROC_PCIE_PAXB_V2:
678 regs = iproc_pcie_reg_paxb_v2;
679 num_elements = ARRAY_SIZE(iproc_pcie_reg_paxb_v2);
680 pcie->has_apb_err_disable = true;
681 if (pcie->need_ob_cfg) {
682 pcie->ob.axi_offset = 0;
683 pcie->ob_map = paxb_v2_ob_map;
684 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
685 }
686 pcie->need_ib_cfg = true;
687 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
688 pcie->ib_map = paxb_v2_ib_map;
689 break;
690 default:
691 dev_dbg(pcie->dev, "incompatible iProc PCIe interface\n");
692 return -EINVAL;
693 }
694
695 pcie->reg_offsets = calloc(IPROC_PCIE_MAX_NUM_REG,
696 sizeof(*pcie->reg_offsets));
697 if (!pcie->reg_offsets)
698 return -ENOMEM;
699
700
701 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
702 IPROC_PCIE_REG_INVALID : regs[0];
703 for (reg_idx = 1; reg_idx < num_elements; reg_idx++)
704 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
705 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
706
707 return 0;
708}
709
710static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
711 int window_idx)
712{
713 u32 val;
714
715 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
716
717 return !!(val & OARR_VALID);
718}
719
720static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
721 int size_idx, u64 axi_addr, u64 pci_addr)
722{
723 u16 oarr_offset, omap_offset;
724
725
726
727
728
729 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
730 window_idx));
731 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
732 window_idx));
733 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
734 iproc_pcie_reg_is_invalid(omap_offset))
735 return -EINVAL;
736
737
738
739
740
741 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
742 OARR_VALID, pcie->base + oarr_offset);
743 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
744
745
746 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
747 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
748
749 debug("ob window [%d]: offset 0x%x axi %pap pci %pap\n",
750 window_idx, oarr_offset, &axi_addr, &pci_addr);
751 debug("oarr lo 0x%x oarr hi 0x%x\n",
752 readl(pcie->base + oarr_offset),
753 readl(pcie->base + oarr_offset + 4));
754 debug("omap lo 0x%x omap hi 0x%x\n",
755 readl(pcie->base + omap_offset),
756 readl(pcie->base + omap_offset + 4));
757
758 return 0;
759}
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
780 u64 pci_addr, resource_size_t size)
781{
782 struct iproc_pcie_ob *ob = &pcie->ob;
783 int ret = -EINVAL, window_idx, size_idx;
784
785 if (axi_addr < ob->axi_offset) {
786 pr_err("axi address %pap less than offset %pap\n",
787 &axi_addr, &ob->axi_offset);
788 return -EINVAL;
789 }
790
791
792
793
794
795 axi_addr -= ob->axi_offset;
796
797
798 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
799 const struct iproc_pcie_ob_map *ob_map =
800 &pcie->ob_map[window_idx];
801
802
803
804
805
806 if (iproc_pcie_ob_is_valid(pcie, window_idx))
807 continue;
808
809
810
811
812
813
814 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
815 size_idx--) {
816 resource_size_t window_size =
817 ob_map->window_sizes[size_idx] * SZ_1M;
818
819
820
821
822
823
824
825 if (size < window_size) {
826 if (size_idx > 0 || window_idx > 0)
827 continue;
828
829
830
831
832
833
834 axi_addr = ALIGN_DOWN(axi_addr, window_size);
835 pci_addr = ALIGN_DOWN(pci_addr, window_size);
836 size = window_size;
837 }
838
839 if (!IS_ALIGNED(axi_addr, window_size) ||
840 !IS_ALIGNED(pci_addr, window_size)) {
841 pr_err("axi %pap or pci %pap not aligned\n",
842 &axi_addr, &pci_addr);
843 return -EINVAL;
844 }
845
846
847
848
849
850 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
851 axi_addr, pci_addr);
852 if (ret)
853 goto err_ob;
854
855 size -= window_size;
856 if (size == 0)
857 return 0;
858
859
860
861
862
863
864 axi_addr += window_size;
865 pci_addr += window_size;
866 break;
867 }
868 }
869
870err_ob:
871 pr_err("unable to configure outbound mapping\n");
872 pr_err("axi %pap, axi offset %pap, pci %pap, res size %pap\n",
873 &axi_addr, &ob->axi_offset, &pci_addr, &size);
874
875 return ret;
876}
877
878static int iproc_pcie_map_ranges(struct udevice *dev)
879{
880 struct iproc_pcie *pcie = dev_get_priv(dev);
881 struct udevice *bus = pci_get_controller(dev);
882 struct pci_controller *hose = dev_get_uclass_priv(bus);
883 int i, ret;
884
885 for (i = 0; i < hose->region_count; i++) {
886 if (hose->regions[i].flags == PCI_REGION_MEM ||
887 hose->regions[i].flags == PCI_REGION_PREFETCH) {
888 debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n",
889 i, &hose->regions[i].bus_start,
890 &hose->regions[i].phys_start,
891 hose->regions[i].size);
892 ret = iproc_pcie_setup_ob(pcie,
893 hose->regions[i].phys_start,
894 hose->regions[i].bus_start,
895 hose->regions[i].size);
896 if (ret)
897 return ret;
898 }
899 }
900
901 return 0;
902}
903
904static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
905 int region_idx)
906{
907 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
908 u32 val;
909
910 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
911
912 return !!(val & (BIT(ib_map->nr_sizes) - 1));
913}
914
915static inline bool
916iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
917 enum iproc_pcie_ib_map_type type)
918{
919 return !!(ib_map->type == type);
920}
921
922static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
923 int size_idx, int nr_windows, u64 axi_addr,
924 u64 pci_addr, resource_size_t size)
925{
926 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
927 u16 iarr_offset, imap_offset;
928 u32 val;
929 int window_idx;
930
931 iarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IARR0,
932 region_idx));
933 imap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IMAP0,
934 region_idx));
935 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
936 iproc_pcie_reg_is_invalid(imap_offset))
937 return -EINVAL;
938
939 debug("ib region [%d]: offset 0x%x axi %pap pci %pap\n",
940 region_idx, iarr_offset, &axi_addr, &pci_addr);
941
942
943
944
945
946 writel(lower_32_bits(pci_addr) | BIT(size_idx),
947 pcie->base + iarr_offset);
948 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
949
950 debug("iarr lo 0x%x iarr hi 0x%x\n",
951 readl(pcie->base + iarr_offset),
952 readl(pcie->base + iarr_offset + 4));
953
954
955
956
957
958 size >>= ilog2(nr_windows);
959 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
960 val = readl(pcie->base + imap_offset);
961 val |= lower_32_bits(axi_addr) | IMAP_VALID;
962 writel(val, pcie->base + imap_offset);
963 writel(upper_32_bits(axi_addr),
964 pcie->base + imap_offset + ib_map->imap_addr_offset);
965
966 debug("imap window [%d] lo 0x%x hi 0x%x\n",
967 window_idx, readl(pcie->base + imap_offset),
968 readl(pcie->base + imap_offset +
969 ib_map->imap_addr_offset));
970
971 imap_offset += ib_map->imap_window_offset;
972 axi_addr += size;
973 }
974
975 return 0;
976}
977
978
979
980
981
982
983
984
985
986
987
988
989static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, u64 axi_addr,
990 u64 pci_addr, resource_size_t size,
991 enum iproc_pcie_ib_map_type type)
992{
993 struct iproc_pcie_ib *ib = &pcie->ib;
994 int ret;
995 unsigned int region_idx, size_idx;
996
997
998 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
999 const struct iproc_pcie_ib_map *ib_map =
1000 &pcie->ib_map[region_idx];
1001
1002
1003
1004
1005
1006 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1007 !iproc_pcie_ib_check_type(ib_map, type))
1008 continue;
1009
1010
1011 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1012 resource_size_t region_size =
1013 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1014
1015 if (size != region_size)
1016 continue;
1017
1018 if (!IS_ALIGNED(axi_addr, region_size) ||
1019 !IS_ALIGNED(pci_addr, region_size)) {
1020 pr_err("axi %pap or pci %pap not aligned\n",
1021 &axi_addr, &pci_addr);
1022 return -EINVAL;
1023 }
1024
1025
1026 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1027 ib_map->nr_windows, axi_addr,
1028 pci_addr, size);
1029 if (ret)
1030 goto err_ib;
1031 else
1032 return 0;
1033 }
1034 }
1035 ret = -EINVAL;
1036
1037err_ib:
1038 pr_err("unable to configure inbound mapping\n");
1039 pr_err("axi %pap, pci %pap, res size %pap\n",
1040 &axi_addr, &pci_addr, &size);
1041
1042 return ret;
1043}
1044
1045static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1046{
1047 int ret;
1048 struct pci_region regions;
1049 int i = 0;
1050
1051 while (!pci_get_dma_regions(pcie->dev, ®ions, i)) {
1052 dev_dbg(pcie->dev,
1053 "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n",
1054 i, regions.bus_start, regions.phys_start, regions.size);
1055
1056
1057 ret = iproc_pcie_setup_ib(pcie, regions.phys_start,
1058 regions.bus_start,
1059 regions.size,
1060 IPROC_PCIE_IB_MAP_MEM);
1061 if (ret)
1062 return ret;
1063 i++;
1064 }
1065 return 0;
1066}
1067
1068static void iproc_pcie_reset_map_regs(struct iproc_pcie *pcie)
1069{
1070 struct iproc_pcie_ib *ib = &pcie->ib;
1071 struct iproc_pcie_ob *ob = &pcie->ob;
1072 int window_idx, region_idx;
1073
1074 if (pcie->ep_is_internal)
1075 return;
1076
1077
1078 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
1079 iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_OARR0,
1080 window_idx), 0);
1081 }
1082
1083
1084 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1085 iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_IARR0,
1086 region_idx), 0);
1087 }
1088}
1089
1090static void iproc_pcie_reset(struct iproc_pcie *pcie)
1091{
1092 u32 val;
1093
1094
1095
1096
1097
1098
1099 if (pcie->ep_is_internal)
1100 return;
1101
1102
1103
1104
1105
1106 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
1107 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
1108 ~RC_PCIE_RST_OUTPUT;
1109 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
1110 udelay(250);
1111
1112 val |= RC_PCIE_RST_OUTPUT;
1113 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
1114 mdelay(100);
1115}
1116
1117static inline bool iproc_pcie_link_is_active(struct iproc_pcie *pcie)
1118{
1119 u32 val;
1120
1121 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
1122 return !!((val & PCIE_PHYLINKUP) && (val & PCIE_DL_ACTIVE));
1123}
1124
1125static int iproc_pcie_check_link(struct iproc_pcie *pcie)
1126{
1127 u32 link_status, class;
1128
1129 pcie->link_is_active = false;
1130
1131#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
1132#define PCI_CLASS_BRIDGE_MASK 0xffff00
1133#define PCI_CLASS_BRIDGE_SHIFT 8
1134 iproc_pci_raw_config_read32(pcie, 0,
1135 PCI_BRIDGE_CTRL_REG_OFFSET,
1136 4, &class);
1137 class &= ~PCI_CLASS_BRIDGE_MASK;
1138 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
1139 iproc_pci_raw_config_write32(pcie, 0,
1140 PCI_BRIDGE_CTRL_REG_OFFSET,
1141 4, class);
1142
1143
1144
1145
1146
1147 if (pcie->ep_is_internal) {
1148 pcie->link_is_active = true;
1149 return 0;
1150 }
1151
1152 if (!iproc_pcie_link_is_active(pcie)) {
1153 pr_err("PHY or data link is INACTIVE!\n");
1154 return -ENODEV;
1155 }
1156
1157#define PCI_TARGET_LINK_SPEED_MASK 0xf
1158#define PCI_TARGET_LINK_WIDTH_MASK 0x3f
1159#define PCI_TARGET_LINK_WIDTH_OFFSET 0x4
1160
1161
1162 iproc_pci_raw_config_read32(pcie, 0,
1163 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
1164 2, &link_status);
1165 if (link_status & PCI_EXP_LNKSTA_NLW)
1166 pcie->link_is_active = true;
1167
1168 if (pcie->link_is_active)
1169 pr_info("link UP @ Speed Gen-%d and width-x%d\n",
1170 link_status & PCI_TARGET_LINK_SPEED_MASK,
1171 (link_status >> PCI_TARGET_LINK_WIDTH_OFFSET) &
1172 PCI_TARGET_LINK_WIDTH_MASK);
1173 else
1174 pr_info("link DOWN\n");
1175
1176 return 0;
1177}
1178
1179static int iproc_pcie_probe(struct udevice *dev)
1180{
1181 struct iproc_pcie *pcie = dev_get_priv(dev);
1182 int ret;
1183
1184 pcie->type = (enum iproc_pcie_type)dev_get_driver_data(dev);
1185 debug("PAX type %d\n", pcie->type);
1186 pcie->base = dev_read_addr_ptr(dev);
1187 debug("PAX reg base %p\n", pcie->base);
1188
1189 if (!pcie->base)
1190 return -ENODEV;
1191
1192 if (dev_read_bool(dev, "brcm,pcie-ob"))
1193 pcie->need_ob_cfg = true;
1194
1195 pcie->dev = dev;
1196 ret = iproc_pcie_rev_init(pcie);
1197 if (ret)
1198 return ret;
1199
1200 if (!pcie->ep_is_internal) {
1201 ret = generic_phy_get_by_name(dev, "pcie-phy", &pcie->phy);
1202 if (!ret) {
1203 ret = generic_phy_init(&pcie->phy);
1204 if (ret) {
1205 pr_err("failed to init %s PHY\n", dev->name);
1206 return ret;
1207 }
1208
1209 ret = generic_phy_power_on(&pcie->phy);
1210 if (ret) {
1211 pr_err("power on %s PHY failed\n", dev->name);
1212 goto err_exit_phy;
1213 }
1214 }
1215 }
1216
1217 iproc_pcie_reset(pcie);
1218
1219 if (pcie->need_ob_cfg) {
1220 ret = iproc_pcie_map_ranges(dev);
1221 if (ret) {
1222 pr_err("outbound map failed\n");
1223 goto err_power_off_phy;
1224 }
1225 }
1226
1227 if (pcie->need_ib_cfg) {
1228 ret = iproc_pcie_map_dma_ranges(pcie);
1229 if (ret) {
1230 pr_err("inbound map failed\n");
1231 goto err_power_off_phy;
1232 }
1233 }
1234
1235 if (iproc_pcie_check_link(pcie))
1236 pr_info("no PCIe EP device detected\n");
1237
1238 return 0;
1239
1240err_power_off_phy:
1241 generic_phy_power_off(&pcie->phy);
1242err_exit_phy:
1243 generic_phy_exit(&pcie->phy);
1244 return ret;
1245}
1246
1247static int iproc_pcie_remove(struct udevice *dev)
1248{
1249 struct iproc_pcie *pcie = dev_get_priv(dev);
1250 int ret;
1251
1252 iproc_pcie_reset_map_regs(pcie);
1253
1254 if (generic_phy_valid(&pcie->phy)) {
1255 ret = generic_phy_power_off(&pcie->phy);
1256 if (ret) {
1257 pr_err("failed to power off PCIe phy\n");
1258 return ret;
1259 }
1260
1261 ret = generic_phy_exit(&pcie->phy);
1262 if (ret) {
1263 pr_err("failed to power off PCIe phy\n");
1264 return ret;
1265 }
1266 }
1267
1268 return 0;
1269}
1270
1271static const struct udevice_id pci_iproc_ids[] = {
1272 { .compatible = "brcm,iproc-pcie-paxb-v2",
1273 .data = IPROC_PCIE_PAXB_V2 },
1274 { .compatible = "brcm,iproc-pcie-paxc-v2",
1275 .data = IPROC_PCIE_PAXC_V2 },
1276 { }
1277};
1278
1279U_BOOT_DRIVER(pci_iproc) = {
1280 .name = "pci_iproc",
1281 .id = UCLASS_PCI,
1282 .of_match = pci_iproc_ids,
1283 .ops = &iproc_pcie_ops,
1284 .probe = iproc_pcie_probe,
1285 .remove = iproc_pcie_remove,
1286 .priv_auto = sizeof(struct iproc_pcie),
1287 .flags = DM_FLAG_OS_PREPARE,
1288};
1289