LXR uboot/drivers/phy/allwinner/phy-sun50i-usb3.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Allwinner sun50i(H6) USB 3.0 phy driver
   4 *
   5 * Copyright (C) 2020 Samuel Holland <samuel@sholland.org>
   6 *
   7 * Based on the Linux driver, which is:
   8 *
   9 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  10 *
  11 * Based on phy-sun9i-usb.c, which is:
  12 *
  13 * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
  14 *
  15 * Based on code from Allwinner BSP, which is:
  16 *
  17 * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
  18 */
  19
  20#include <asm/io.h>
  21#include <clk.h>
  22#include <dm.h>
  23#include <dm/device_compat.h>
  24#include <generic-phy.h>
  25#include <linux/bitops.h>
  26#include <reset.h>
  27
  28/* Interface Status and Control Registers */
  29#define SUNXI_ISCR                      0x00
  30#define SUNXI_PIPE_CLOCK_CONTROL        0x14
  31#define SUNXI_PHY_TUNE_LOW              0x18
  32#define SUNXI_PHY_TUNE_HIGH             0x1c
  33#define SUNXI_PHY_EXTERNAL_CONTROL      0x20
  34
  35/* USB2.0 Interface Status and Control Register */
  36#define SUNXI_ISCR_FORCE_VBUS           (3 << 12)
  37
  38/* PIPE Clock Control Register */
  39#define SUNXI_PCC_PIPE_CLK_OPEN         (1 << 6)
  40
  41/* PHY External Control Register */
  42#define SUNXI_PEC_EXTERN_VBUS           (3 << 1)
  43#define SUNXI_PEC_SSC_EN                (1 << 24)
  44#define SUNXI_PEC_REF_SSP_EN            (1 << 26)
  45
  46/* PHY Tune High Register */
  47#define SUNXI_TX_DEEMPH_3P5DB(n)        ((n) << 19)
  48#define SUNXI_TX_DEEMPH_3P5DB_MASK      GENMASK(24, 19)
  49#define SUNXI_TX_DEEMPH_6DB(n)          ((n) << 13)
  50#define SUNXI_TX_DEEMPH_6GB_MASK        GENMASK(18, 13)
  51#define SUNXI_TX_SWING_FULL(n)          ((n) << 6)
  52#define SUNXI_TX_SWING_FULL_MASK        GENMASK(12, 6)
  53#define SUNXI_LOS_BIAS(n)               ((n) << 3)
  54#define SUNXI_LOS_BIAS_MASK             GENMASK(5, 3)
  55#define SUNXI_TXVBOOSTLVL(n)            ((n) << 0)
  56#define SUNXI_TXVBOOSTLVL_MASK          GENMASK(2, 0)
  57
  58struct sun50i_usb3_phy_priv {
  59        void __iomem *regs;
  60        struct reset_ctl reset;
  61        struct clk clk;
  62};
  63
  64static void sun50i_usb3_phy_open(struct sun50i_usb3_phy_priv *phy)
  65{
  66        u32 val;
  67
  68        val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  69        val |= SUNXI_PEC_EXTERN_VBUS;
  70        val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
  71        writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  72
  73        val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  74        val |= SUNXI_PCC_PIPE_CLK_OPEN;
  75        writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  76
  77        val = readl(phy->regs + SUNXI_ISCR);
  78        val |= SUNXI_ISCR_FORCE_VBUS;
  79        writel(val, phy->regs + SUNXI_ISCR);
  80
  81        /*
  82         * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
  83         * registers are directly taken from the BSP USB3 driver from
  84         * Allwiner.
  85         */
  86        writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
  87
  88        val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
  89        val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
  90                 SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
  91                 SUNXI_TX_DEEMPH_3P5DB_MASK);
  92        val |= SUNXI_TXVBOOSTLVL(0x7);
  93        val |= SUNXI_LOS_BIAS(0x7);
  94        val |= SUNXI_TX_SWING_FULL(0x55);
  95        val |= SUNXI_TX_DEEMPH_6DB(0x20);
  96        val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
  97        writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
  98}
  99
 100static int sun50i_usb3_phy_init(struct phy *phy)
 101{
 102        struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
 103        int ret;
 104
 105        ret = clk_prepare_enable(&priv->clk);
 106        if (ret)
 107                return ret;
 108
 109        ret = reset_deassert(&priv->reset);
 110        if (ret) {
 111                clk_disable_unprepare(&priv->clk);
 112                return ret;
 113        }
 114
 115        sun50i_usb3_phy_open(priv);
 116
 117        return 0;
 118}
 119
 120static int sun50i_usb3_phy_exit(struct phy *phy)
 121{
 122        struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
 123
 124        reset_assert(&priv->reset);
 125        clk_disable_unprepare(&priv->clk);
 126
 127        return 0;
 128}
 129
 130static const struct phy_ops sun50i_usb3_phy_ops = {
 131        .init           = sun50i_usb3_phy_init,
 132        .exit           = sun50i_usb3_phy_exit,
 133};
 134
 135static int sun50i_usb3_phy_probe(struct udevice *dev)
 136{
 137        struct sun50i_usb3_phy_priv *priv = dev_get_priv(dev);
 138        int ret;
 139
 140        ret = clk_get_by_index(dev, 0, &priv->clk);
 141        if (ret) {
 142                dev_err(dev, "failed to get phy clock\n");
 143                return ret;
 144        }
 145
 146        ret = reset_get_by_index(dev, 0, &priv->reset);
 147        if (ret) {
 148                dev_err(dev, "failed to get reset control\n");
 149                return ret;
 150        }
 151
 152        priv->regs = (void __iomem *)dev_read_addr(dev);
 153        if (IS_ERR(priv->regs))
 154                return PTR_ERR(priv->regs);
 155
 156        return 0;
 157}
 158
 159static const struct udevice_id sun50i_usb3_phy_ids[] = {
 160        { .compatible = "allwinner,sun50i-h6-usb3-phy" },
 161        { },
 162};
 163
 164U_BOOT_DRIVER(sun50i_usb3_phy) = {
 165        .name           = "sun50i-usb3-phy",
 166        .id             = UCLASS_PHY,
 167        .of_match       = sun50i_usb3_phy_ids,
 168        .ops            = &sun50i_usb3_phy_ops,
 169        .probe          = sun50i_usb3_phy_probe,
 170        .priv_auto      = sizeof(struct sun50i_usb3_phy_priv),
 171};
 172