1
2
3
4
5
6
7#include <common.h>
8#include <dm.h>
9#include <dm/device.h>
10#include <generic-phy.h>
11#include <asm/global_data.h>
12#include <asm/io.h>
13#include <asm/arch/sys_proto.h>
14#include <syscon.h>
15#include <regmap.h>
16#include <linux/bitops.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19
20
21#define PLL_STATUS 0x00000004
22#define PLL_GO 0x00000008
23#define PLL_CONFIGURATION1 0x0000000C
24#define PLL_CONFIGURATION2 0x00000010
25#define PLL_CONFIGURATION3 0x00000014
26#define PLL_CONFIGURATION4 0x00000020
27
28#define PLL_REGM_MASK 0x001FFE00
29#define PLL_REGM_SHIFT 9
30#define PLL_REGM_F_MASK 0x0003FFFF
31#define PLL_REGM_F_SHIFT 0
32#define PLL_REGN_MASK 0x000001FE
33#define PLL_REGN_SHIFT 1
34#define PLL_SELFREQDCO_MASK 0x0000000E
35#define PLL_SELFREQDCO_SHIFT 1
36#define PLL_SD_MASK 0x0003FC00
37#define PLL_SD_SHIFT 10
38#define SET_PLL_GO 0x1
39#define PLL_TICOPWDN BIT(16)
40#define PLL_LDOPWDN BIT(15)
41#define PLL_LOCK 0x2
42#define PLL_IDLE 0x1
43
44
45#define SATA_PLL_SOFT_RESET (1<<18)
46
47
48#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
49#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
50
51#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
52#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
53
54#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
55#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
56
57
58#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
59#define INTERFACE_MASK GENMASK(31, 27)
60#define INTERFACE_SHIFT 27
61#define INTERFACE_MODE_USBSS BIT(4)
62#define INTERFACE_MODE_SATA_1P5 BIT(3)
63#define INTERFACE_MODE_SATA_3P0 BIT(2)
64#define INTERFACE_MODE_PCIE BIT(0)
65
66#define LOSD_MASK GENMASK(17, 14)
67#define LOSD_SHIFT 14
68#define MEM_PLLDIV GENMASK(6, 5)
69
70#define PIPE3_PHY_RX_TRIM 0x0000001C
71#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
72#define MEM_DLL_TRIM_SHIFT 30
73
74#define PIPE3_PHY_RX_DLL 0x00000024
75#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
76#define MEM_DLL_PHINT_RATE_SHIFT 30
77
78#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
79#define MEM_HS_RATE_MASK GENMASK(28, 27)
80#define MEM_HS_RATE_SHIFT 27
81#define MEM_OVRD_HS_RATE BIT(26)
82#define MEM_OVRD_HS_RATE_SHIFT 26
83#define MEM_CDR_FASTLOCK BIT(23)
84#define MEM_CDR_FASTLOCK_SHIFT 23
85#define MEM_CDR_LBW_MASK GENMASK(22, 21)
86#define MEM_CDR_LBW_SHIFT 21
87#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
88#define MEM_CDR_STEPCNT_SHIFT 19
89#define MEM_CDR_STL_MASK GENMASK(18, 16)
90#define MEM_CDR_STL_SHIFT 16
91#define MEM_CDR_THR_MASK GENMASK(15, 13)
92#define MEM_CDR_THR_SHIFT 13
93#define MEM_CDR_THR_MODE BIT(12)
94#define MEM_CDR_THR_MODE_SHIFT 12
95#define MEM_CDR_2NDO_SDM_MODE BIT(11)
96#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
97
98#define PIPE3_PHY_RX_EQUALIZER 0x00000038
99#define MEM_EQLEV_MASK GENMASK(31, 16)
100#define MEM_EQLEV_SHIFT 16
101#define MEM_EQFTC_MASK GENMASK(15, 11)
102#define MEM_EQFTC_SHIFT 11
103#define MEM_EQCTL_MASK GENMASK(10, 7)
104#define MEM_EQCTL_SHIFT 7
105#define MEM_OVRD_EQLEV BIT(2)
106#define MEM_OVRD_EQLEV_SHIFT 2
107#define MEM_OVRD_EQFTC BIT(1)
108#define MEM_OVRD_EQFTC_SHIFT 1
109
110#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
111#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
112#define MEM_CDR_LOS_SOURCE_SHIFT 9
113
114#define PLL_IDLE_TIME 100
115#define PLL_LOCK_TIME 100
116
117enum pipe3_mode { PIPE3_MODE_PCIE = 1,
118 PIPE3_MODE_SATA,
119 PIPE3_MODE_USBSS };
120
121struct pipe3_settings {
122 u8 ana_interface;
123 u8 ana_losd;
124 u8 dig_fastlock;
125 u8 dig_lbw;
126 u8 dig_stepcnt;
127 u8 dig_stl;
128 u8 dig_thr;
129 u8 dig_thr_mode;
130 u8 dig_2ndo_sdm_mode;
131 u8 dig_hs_rate;
132 u8 dig_ovrd_hs_rate;
133 u8 dll_trim_sel;
134 u8 dll_phint_rate;
135 u8 eq_lev;
136 u8 eq_ftc;
137 u8 eq_ctl;
138 u8 eq_ovrd_lev;
139 u8 eq_ovrd_ftc;
140};
141
142struct omap_pipe3 {
143 void __iomem *pll_ctrl_base;
144 void __iomem *phy_rx;
145 void __iomem *power_reg;
146 void __iomem *pll_reset_reg;
147 struct pipe3_dpll_map *dpll_map;
148 enum pipe3_mode mode;
149 struct pipe3_settings settings;
150};
151
152struct pipe3_dpll_params {
153 u16 m;
154 u8 n;
155 u8 freq:3;
156 u8 sd;
157 u32 mf;
158};
159
160struct pipe3_dpll_map {
161 unsigned long rate;
162 struct pipe3_dpll_params params;
163};
164
165struct pipe3_data {
166 enum pipe3_mode mode;
167 struct pipe3_dpll_map *dpll_map;
168 struct pipe3_settings settings;
169};
170
171static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
172{
173 return readl(addr + offset);
174}
175
176static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
177 u32 data)
178{
179 writel(data, addr + offset);
180}
181
182static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
183 *pipe3)
184{
185 u32 rate;
186 struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
187
188 rate = get_sys_clk_freq();
189
190 for (; dpll_map->rate; dpll_map++) {
191 if (rate == dpll_map->rate)
192 return &dpll_map->params;
193 }
194
195 printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
196 __func__, rate);
197 return NULL;
198}
199
200static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
201{
202 u32 val;
203 int timeout = PLL_LOCK_TIME;
204
205 do {
206 mdelay(1);
207 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
208 if (val & PLL_LOCK)
209 break;
210 } while (--timeout);
211
212 if (!(val & PLL_LOCK)) {
213 printf("%s: DPLL failed to lock\n", __func__);
214 return -EBUSY;
215 }
216
217 return 0;
218}
219
220static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
221{
222 u32 val;
223 struct pipe3_dpll_params *dpll_params;
224
225 dpll_params = omap_pipe3_get_dpll_params(pipe3);
226 if (!dpll_params) {
227 printf("%s: Invalid DPLL parameters\n", __func__);
228 return -EINVAL;
229 }
230
231 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
232 val &= ~PLL_REGN_MASK;
233 val |= dpll_params->n << PLL_REGN_SHIFT;
234 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
235
236 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
237 val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
238 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
239 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
240
241 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
242 val &= ~PLL_REGM_MASK;
243 val |= dpll_params->m << PLL_REGM_SHIFT;
244 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
245
246 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
247 val &= ~PLL_REGM_F_MASK;
248 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
249 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
250
251 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
252 val &= ~PLL_SD_MASK;
253 val |= dpll_params->sd << PLL_SD_SHIFT;
254 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
255
256 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
257
258 return omap_pipe3_wait_lock(pipe3);
259}
260
261static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
262{
263 u32 val, rate;
264
265 val = readl(pipe3->power_reg);
266
267 rate = get_sys_clk_freq();
268 rate = rate/1000000;
269
270 if (on) {
271 val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
272 PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
273 val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
274 writel(val, pipe3->power_reg);
275
276
277 val |= PIPE3_PHY_TX_POWERON;
278 writel(val, pipe3->power_reg);
279
280 val |= PIPE3_PHY_RX_POWERON;
281 writel(val, pipe3->power_reg);
282 } else {
283 val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
284 writel(val, pipe3->power_reg);
285 }
286}
287
288static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
289{
290 u32 val;
291 struct pipe3_settings *s = &phy->settings;
292
293 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
294 val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
295 val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
296 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
297
298 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
299 val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
300 MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
301 MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
302 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
303 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
304 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
305 s->dig_lbw << MEM_CDR_LBW_SHIFT |
306 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
307 s->dig_stl << MEM_CDR_STL_SHIFT |
308 s->dig_thr << MEM_CDR_THR_SHIFT |
309 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
310 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
311 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
312
313 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
314 val &= ~MEM_DLL_TRIM_SEL_MASK;
315 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
316 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
317
318 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
319 val &= ~MEM_DLL_PHINT_RATE_MASK;
320 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
321 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
322
323 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
324 val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
325 MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
326 val |= s->eq_lev << MEM_EQLEV_SHIFT |
327 s->eq_ftc << MEM_EQFTC_SHIFT |
328 s->eq_ctl << MEM_EQCTL_SHIFT |
329 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
330 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
331 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
332
333 if (phy->mode == PIPE3_MODE_SATA) {
334 val = omap_pipe3_readl(phy->phy_rx,
335 SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
336 val &= ~MEM_CDR_LOS_SOURCE_MASK;
337 omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
338 val);
339 }
340}
341
342static int pipe3_init(struct phy *phy)
343{
344 int ret;
345 u32 val;
346 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
347
348
349 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
350 if (!(val & PLL_LOCK)) {
351 ret = omap_pipe3_dpll_program(pipe3);
352 if (ret)
353 return ret;
354
355 ti_pipe3_calibrate(pipe3);
356 } else {
357
358 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
359 PLL_CONFIGURATION2);
360 if (val & PLL_IDLE) {
361 val &= ~PLL_IDLE;
362 omap_pipe3_writel(pipe3->pll_ctrl_base,
363 PLL_CONFIGURATION2, val);
364 ret = omap_pipe3_wait_lock(pipe3);
365 if (ret)
366 return ret;
367 }
368 }
369 return 0;
370}
371
372static int pipe3_power_on(struct phy *phy)
373{
374 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
375
376
377 omap_control_pipe3_power(pipe3, 1);
378
379 return 0;
380}
381
382static int pipe3_power_off(struct phy *phy)
383{
384 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
385
386
387 omap_control_pipe3_power(pipe3, 0);
388
389 return 0;
390}
391
392static int pipe3_exit(struct phy *phy)
393{
394 u32 val;
395 int timeout = PLL_IDLE_TIME;
396 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
397
398 pipe3_power_off(phy);
399
400
401 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
402 val |= PLL_IDLE;
403 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
404
405
406 do {
407 mdelay(1);
408 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
409 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
410 break;
411 } while (--timeout);
412
413 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
414 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
415 __func__, val);
416 return -EBUSY;
417 }
418
419 if (pipe3->pll_reset_reg) {
420 val = readl(pipe3->pll_reset_reg);
421 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
422 mdelay(1);
423 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
424 }
425
426 return 0;
427}
428
429static void *get_reg(struct udevice *dev, const char *name)
430{
431 struct udevice *syscon;
432 struct regmap *regmap;
433 const fdt32_t *cell;
434 int len, err;
435 void *base;
436
437 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
438 name, &syscon);
439 if (err) {
440 pr_err("unable to find syscon device for %s (%d)\n",
441 name, err);
442 return NULL;
443 }
444
445 regmap = syscon_get_regmap(syscon);
446 if (IS_ERR(regmap)) {
447 pr_err("unable to find regmap for %s (%ld)\n",
448 name, PTR_ERR(regmap));
449 return NULL;
450 }
451
452 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
453 &len);
454 if (len < 2*sizeof(fdt32_t)) {
455 pr_err("offset not available for %s\n", name);
456 return NULL;
457 }
458
459 base = regmap_get_range(regmap, 0);
460 if (!base)
461 return NULL;
462
463 return fdtdec_get_number(cell + 1, 1) + base;
464}
465
466static int pipe3_phy_probe(struct udevice *dev)
467{
468 fdt_addr_t addr;
469 fdt_size_t sz;
470 struct omap_pipe3 *pipe3 = dev_get_priv(dev);
471 struct pipe3_data *data;
472
473
474 addr = devfdt_get_addr_size_index(dev, 0, &sz);
475 if (addr == FDT_ADDR_T_NONE) {
476 pr_err("missing phy_rx address\n");
477 return -EINVAL;
478 }
479
480 pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
481 if (!pipe3->phy_rx) {
482 pr_err("unable to remap phy_rx\n");
483 return -EINVAL;
484 }
485
486
487 addr = devfdt_get_addr_size_index(dev, 2, &sz);
488 if (addr == FDT_ADDR_T_NONE) {
489 pr_err("missing pll ctrl address\n");
490 return -EINVAL;
491 }
492
493 pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
494 if (!pipe3->pll_ctrl_base) {
495 pr_err("unable to remap pll ctrl\n");
496 return -EINVAL;
497 }
498
499 pipe3->power_reg = get_reg(dev, "syscon-phy-power");
500 if (!pipe3->power_reg)
501 return -EINVAL;
502
503 data = (struct pipe3_data *)dev_get_driver_data(dev);
504 pipe3->mode = data->mode;
505 pipe3->dpll_map = data->dpll_map;
506 pipe3->settings = data->settings;
507
508 if (pipe3->mode == PIPE3_MODE_SATA) {
509 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
510 if (!pipe3->pll_reset_reg)
511 return -EINVAL;
512 }
513
514 return 0;
515}
516
517static struct pipe3_dpll_map dpll_map_sata[] = {
518 {12000000, {625, 4, 4, 6, 0} },
519 {16800000, {625, 6, 4, 7, 0} },
520 {19200000, {625, 7, 4, 6, 0} },
521 {20000000, {750, 9, 4, 6, 0} },
522 {26000000, {750, 12, 4, 6, 0} },
523 {38400000, {625, 15, 4, 6, 0} },
524 { },
525};
526
527static struct pipe3_dpll_map dpll_map_usb[] = {
528 {12000000, {1250, 5, 4, 20, 0} },
529 {16800000, {3125, 20, 4, 20, 0} },
530 {19200000, {1172, 8, 4, 20, 65537} },
531 {20000000, {1000, 7, 4, 10, 0} },
532 {26000000, {1250, 12, 4, 20, 0} },
533 {38400000, {3125, 47, 4, 20, 92843} },
534 { },
535};
536
537static struct pipe3_data data_usb = {
538 .mode = PIPE3_MODE_USBSS,
539 .dpll_map = dpll_map_usb,
540 .settings = {
541
542 .ana_interface = INTERFACE_MODE_USBSS,
543 .ana_losd = 0xa,
544 .dig_fastlock = 1,
545 .dig_lbw = 3,
546 .dig_stepcnt = 0,
547 .dig_stl = 0x3,
548 .dig_thr = 1,
549 .dig_thr_mode = 1,
550 .dig_2ndo_sdm_mode = 0,
551 .dig_hs_rate = 0,
552 .dig_ovrd_hs_rate = 1,
553 .dll_trim_sel = 0x2,
554 .dll_phint_rate = 0x3,
555 .eq_lev = 0,
556 .eq_ftc = 0,
557 .eq_ctl = 0x9,
558 .eq_ovrd_lev = 0,
559 .eq_ovrd_ftc = 0,
560 },
561};
562
563static struct pipe3_data data_sata = {
564 .mode = PIPE3_MODE_SATA,
565 .dpll_map = dpll_map_sata,
566 .settings = {
567
568 .ana_interface = INTERFACE_MODE_SATA_3P0,
569 .ana_losd = 0x5,
570 .dig_fastlock = 1,
571 .dig_lbw = 3,
572 .dig_stepcnt = 0,
573 .dig_stl = 0x3,
574 .dig_thr = 1,
575 .dig_thr_mode = 1,
576 .dig_2ndo_sdm_mode = 0,
577 .dig_hs_rate = 0,
578 .dig_ovrd_hs_rate = 0,
579 .dll_trim_sel = 0x1,
580 .dll_phint_rate = 0x2,
581 .eq_lev = 0,
582 .eq_ftc = 0x1f,
583 .eq_ctl = 0,
584 .eq_ovrd_lev = 1,
585 .eq_ovrd_ftc = 1,
586 },
587};
588
589static const struct udevice_id pipe3_phy_ids[] = {
590 { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
591 { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
592 { }
593};
594
595static struct phy_ops pipe3_phy_ops = {
596 .init = pipe3_init,
597 .power_on = pipe3_power_on,
598 .power_off = pipe3_power_off,
599 .exit = pipe3_exit,
600};
601
602U_BOOT_DRIVER(pipe3_phy) = {
603 .name = "pipe3_phy",
604 .id = UCLASS_PHY,
605 .of_match = pipe3_phy_ids,
606 .ops = &pipe3_phy_ops,
607 .probe = pipe3_phy_probe,
608 .priv_auto = sizeof(struct omap_pipe3),
609};
610
