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6#define LOG_CATEGORY UCLASS_PINCTRL
7
8#include <common.h>
9#include <dm.h>
10#include <hwspinlock.h>
11#include <log.h>
12#include <malloc.h>
13#include <asm/gpio.h>
14#include <asm/io.h>
15#include <dm/device_compat.h>
16#include <dm/lists.h>
17#include <dm/pinctrl.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/libfdt.h>
21
22#include "../gpio/stm32_gpio_priv.h"
23
24#define MAX_PINS_ONE_IP 70
25#define MODE_BITS_MASK 3
26#define OSPEED_MASK 3
27#define PUPD_MASK 3
28#define OTYPE_MSK 1
29#define AFR_MASK 0xF
30
31struct stm32_pinctrl_priv {
32 struct hwspinlock hws;
33 int pinctrl_ngpios;
34 struct list_head gpio_dev;
35};
36
37struct stm32_gpio_bank {
38 struct udevice *gpio_dev;
39 struct list_head list;
40};
41
42#ifndef CONFIG_SPL_BUILD
43
44static char pin_name[PINNAME_SIZE];
45#define PINMUX_MODE_COUNT 5
46static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
47 "gpio input",
48 "gpio output",
49 "analog",
50 "unknown",
51 "alt function",
52};
53
54static const char * const pinmux_bias[] = {
55 [STM32_GPIO_PUPD_NO] = "",
56 [STM32_GPIO_PUPD_UP] = "pull-up",
57 [STM32_GPIO_PUPD_DOWN] = "pull-down",
58};
59
60static const char * const pinmux_otype[] = {
61 [STM32_GPIO_OTYPE_PP] = "push-pull",
62 [STM32_GPIO_OTYPE_OD] = "open-drain",
63};
64
65static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
66{
67 struct stm32_gpio_priv *priv = dev_get_priv(dev);
68 struct stm32_gpio_regs *regs = priv->regs;
69 u32 af;
70 u32 alt_shift = (offset % 8) * 4;
71 u32 alt_index = offset / 8;
72
73 af = (readl(®s->afr[alt_index]) &
74 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
75
76 return af;
77}
78
79static int stm32_populate_gpio_dev_list(struct udevice *dev)
80{
81 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
82 struct udevice *gpio_dev;
83 struct udevice *child;
84 struct stm32_gpio_bank *gpio_bank;
85 int ret;
86
87
88
89
90
91
92
93 list_for_each_entry(child, &dev->child_head, sibling_node) {
94 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
95 &gpio_dev);
96 if (ret < 0)
97 continue;
98
99 gpio_bank = malloc(sizeof(*gpio_bank));
100 if (!gpio_bank) {
101 dev_err(dev, "Not enough memory\n");
102 return -ENOMEM;
103 }
104
105 gpio_bank->gpio_dev = gpio_dev;
106 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
107 }
108
109 return 0;
110}
111
112static int stm32_pinctrl_get_pins_count(struct udevice *dev)
113{
114 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
115 struct gpio_dev_priv *uc_priv;
116 struct stm32_gpio_bank *gpio_bank;
117
118
119
120
121
122 if (priv->pinctrl_ngpios)
123 return priv->pinctrl_ngpios;
124
125 if (list_empty(&priv->gpio_dev))
126 stm32_populate_gpio_dev_list(dev);
127
128
129
130
131 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
132 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
133
134 priv->pinctrl_ngpios += uc_priv->gpio_count;
135 }
136
137 return priv->pinctrl_ngpios;
138}
139
140static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
141 unsigned int selector,
142 unsigned int *idx)
143{
144 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
145 struct stm32_gpio_bank *gpio_bank;
146 struct gpio_dev_priv *uc_priv;
147 int pin_count = 0;
148
149 if (list_empty(&priv->gpio_dev))
150 stm32_populate_gpio_dev_list(dev);
151
152
153 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
154 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
155
156 if (selector < (pin_count + uc_priv->gpio_count)) {
157
158
159
160
161 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
162 selector - pin_count);
163 if (IS_ERR_VALUE(*idx))
164 return NULL;
165
166 return gpio_bank->gpio_dev;
167 }
168 pin_count += uc_priv->gpio_count;
169 }
170
171 return NULL;
172}
173
174static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
175 unsigned int selector)
176{
177 struct gpio_dev_priv *uc_priv;
178 struct udevice *gpio_dev;
179 unsigned int gpio_idx;
180
181
182 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
183 if (!gpio_dev) {
184 snprintf(pin_name, PINNAME_SIZE, "Error");
185 } else {
186 uc_priv = dev_get_uclass_priv(gpio_dev);
187
188 snprintf(pin_name, PINNAME_SIZE, "%s%d",
189 uc_priv->bank_name,
190 gpio_idx);
191 }
192
193 return pin_name;
194}
195
196static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
197 unsigned int selector,
198 char *buf,
199 int size)
200{
201 struct udevice *gpio_dev;
202 struct stm32_gpio_priv *priv;
203 const char *label;
204 int mode;
205 int af_num;
206 unsigned int gpio_idx;
207 u32 pupd, otype;
208
209
210 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
211
212 if (!gpio_dev)
213 return -ENODEV;
214
215 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
216 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
217 selector, gpio_idx, mode);
218 priv = dev_get_priv(gpio_dev);
219 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
220 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
221
222 switch (mode) {
223 case GPIOF_UNKNOWN:
224
225 return -EINVAL;
226 case GPIOF_UNUSED:
227 snprintf(buf, size, "%s", pinmux_mode[mode]);
228 break;
229 case GPIOF_FUNC:
230 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
231 snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
232 pinmux_otype[otype], pinmux_bias[pupd]);
233 break;
234 case GPIOF_OUTPUT:
235 snprintf(buf, size, "%s %s %s %s",
236 pinmux_mode[mode], pinmux_otype[otype],
237 pinmux_bias[pupd], label ? label : "");
238 break;
239 case GPIOF_INPUT:
240 snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
241 pinmux_bias[pupd], label ? label : "");
242 break;
243 }
244
245 return 0;
246}
247
248#endif
249
250static int stm32_pinctrl_probe(struct udevice *dev)
251{
252 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
253 int ret;
254
255 INIT_LIST_HEAD(&priv->gpio_dev);
256
257
258 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
259 if (ret)
260 dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
261 ret);
262
263 return 0;
264}
265
266static int stm32_gpio_config(struct gpio_desc *desc,
267 const struct stm32_gpio_ctl *ctl)
268{
269 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
270 struct stm32_gpio_regs *regs = priv->regs;
271 struct stm32_pinctrl_priv *ctrl_priv;
272 int ret;
273 u32 index;
274
275 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
276 ctl->pupd > 2 || ctl->speed > 3)
277 return -EINVAL;
278
279 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
280 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
281 if (ret == -ETIME) {
282 dev_err(desc->dev, "HWSpinlock timeout\n");
283 return ret;
284 }
285
286 index = (desc->offset & 0x07) * 4;
287 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
288 ctl->af << index);
289
290 index = desc->offset * 2;
291 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
292 ctl->mode << index);
293 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
294 ctl->speed << index);
295 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
296
297 index = desc->offset;
298 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
299
300 hwspinlock_unlock(&ctrl_priv->hws);
301
302 return 0;
303}
304
305static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
306{
307 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
308 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
309 log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
310
311 return 0;
312}
313
314static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
315 ofnode node)
316{
317 gpio_fn &= 0x00FF;
318 gpio_ctl->af = 0;
319
320 switch (gpio_fn) {
321 case 0:
322 gpio_ctl->mode = STM32_GPIO_MODE_IN;
323 break;
324 case 1 ... 16:
325 gpio_ctl->mode = STM32_GPIO_MODE_AF;
326 gpio_ctl->af = gpio_fn - 1;
327 break;
328 case 17:
329 gpio_ctl->mode = STM32_GPIO_MODE_AN;
330 break;
331 default:
332 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
333 break;
334 }
335
336 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
337
338 if (ofnode_read_bool(node, "drive-open-drain"))
339 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
340 else
341 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
342
343 if (ofnode_read_bool(node, "bias-pull-up"))
344 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
345 else if (ofnode_read_bool(node, "bias-pull-down"))
346 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
347 else
348 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
349
350 log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
351 gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
352 gpio_ctl->pupd);
353
354 return 0;
355}
356
357static int stm32_pinctrl_config(ofnode node)
358{
359 u32 pin_mux[MAX_PINS_ONE_IP];
360 int rv, len;
361 ofnode subnode;
362
363
364
365
366
367 ofnode_for_each_subnode(subnode, node) {
368 struct stm32_gpio_dsc gpio_dsc;
369 struct stm32_gpio_ctl gpio_ctl;
370 int i;
371
372 rv = ofnode_read_size(subnode, "pinmux");
373 if (rv < 0)
374 return rv;
375 len = rv / sizeof(pin_mux[0]);
376 log_debug("No of pinmux entries= %d\n", len);
377 if (len > MAX_PINS_ONE_IP)
378 return -EINVAL;
379 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
380 if (rv < 0)
381 return rv;
382 for (i = 0; i < len; i++) {
383 struct gpio_desc desc;
384
385 log_debug("pinmux = %x\n", *(pin_mux + i));
386 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
387 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
388 rv = uclass_get_device_by_seq(UCLASS_GPIO,
389 gpio_dsc.port,
390 &desc.dev);
391 if (rv)
392 return rv;
393 desc.offset = gpio_dsc.pin;
394 rv = stm32_gpio_config(&desc, &gpio_ctl);
395 log_debug("rv = %d\n\n", rv);
396 if (rv)
397 return rv;
398 }
399 }
400
401 return 0;
402}
403
404static int stm32_pinctrl_bind(struct udevice *dev)
405{
406 ofnode node;
407 const char *name;
408 int ret;
409
410 dev_for_each_subnode(node, dev) {
411 dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
412
413 if (!ofnode_is_enabled(node))
414 continue;
415
416 ofnode_get_property(node, "gpio-controller", &ret);
417 if (ret < 0)
418 continue;
419
420 name = ofnode_get_name(node);
421 if (!name)
422 return -EINVAL;
423
424
425 ret = device_bind_driver_to_node(dev, "gpio_stm32",
426 name, node, NULL);
427 if (ret)
428 return ret;
429
430 dev_dbg(dev, "bind %s\n", name);
431 }
432
433 return 0;
434}
435
436#if CONFIG_IS_ENABLED(PINCTRL_FULL)
437static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
438{
439 return stm32_pinctrl_config(dev_ofnode(config));
440}
441#else
442static int stm32_pinctrl_set_state_simple(struct udevice *dev,
443 struct udevice *periph)
444{
445 const fdt32_t *list;
446 uint32_t phandle;
447 ofnode config_node;
448 int size, i, ret;
449
450 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
451 if (!list)
452 return -EINVAL;
453
454 dev_dbg(dev, "periph->name = %s\n", periph->name);
455
456 size /= sizeof(*list);
457 for (i = 0; i < size; i++) {
458 phandle = fdt32_to_cpu(*list++);
459
460 config_node = ofnode_get_by_phandle(phandle);
461 if (!ofnode_valid(config_node)) {
462 dev_err(periph,
463 "prop pinctrl-0 index %d invalid phandle\n", i);
464 return -EINVAL;
465 }
466
467 ret = stm32_pinctrl_config(config_node);
468 if (ret)
469 return ret;
470 }
471
472 return 0;
473}
474#endif
475
476static struct pinctrl_ops stm32_pinctrl_ops = {
477#if CONFIG_IS_ENABLED(PINCTRL_FULL)
478 .set_state = stm32_pinctrl_set_state,
479#else
480 .set_state_simple = stm32_pinctrl_set_state_simple,
481#endif
482#ifndef CONFIG_SPL_BUILD
483 .get_pin_name = stm32_pinctrl_get_pin_name,
484 .get_pins_count = stm32_pinctrl_get_pins_count,
485 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
486#endif
487};
488
489static const struct udevice_id stm32_pinctrl_ids[] = {
490 { .compatible = "st,stm32f429-pinctrl" },
491 { .compatible = "st,stm32f469-pinctrl" },
492 { .compatible = "st,stm32f746-pinctrl" },
493 { .compatible = "st,stm32f769-pinctrl" },
494 { .compatible = "st,stm32h743-pinctrl" },
495 { .compatible = "st,stm32mp157-pinctrl" },
496 { .compatible = "st,stm32mp157-z-pinctrl" },
497 { }
498};
499
500U_BOOT_DRIVER(pinctrl_stm32) = {
501 .name = "pinctrl_stm32",
502 .id = UCLASS_PINCTRL,
503 .of_match = stm32_pinctrl_ids,
504 .ops = &stm32_pinctrl_ops,
505 .bind = stm32_pinctrl_bind,
506 .probe = stm32_pinctrl_probe,
507 .priv_auto = sizeof(struct stm32_pinctrl_priv),
508};
509