LXR uboot/drivers/qe/uec

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
   4 *
   5 * Author: Shlomi Gridish <gridish@freescale.com>
   6 *
   7 * Description: UCC ethernet driver -- PHY handling
   8 *              Driver for UEC on QE
   9 *              Based on 8260_io/fcc_enet.c
  10 */
  11#ifndef __UEC_PHY_H__
  12#define __UEC_PHY_H__
  13
  14#include <linux/bitops.h>
  15
  16#define MII_end ((u32)-2)
  17#define MII_read ((u32)-1)
  18
  19#define MIIMIND_BUSY            0x00000001
  20#define MIIMIND_NOTVALID        0x00000004
  21
  22#define UGETH_AN_TIMEOUT        2000
  23
  24/* Cicada Extended Control Register 1 */
  25#define MII_CIS8201_EXT_CON1        0x17
  26#define MII_CIS8201_EXTCON1_INIT    0x0000
  27
  28/* Cicada Interrupt Mask Register */
  29#define MII_CIS8201_IMASK           0x19
  30#define MII_CIS8201_IMASK_IEN       0x8000
  31#define MII_CIS8201_IMASK_SPEED     0x4000
  32#define MII_CIS8201_IMASK_LINK      0x2000
  33#define MII_CIS8201_IMASK_DUPLEX    0x1000
  34#define MII_CIS8201_IMASK_MASK      0xf000
  35
  36/* Cicada Interrupt Status Register */
  37#define MII_CIS8201_ISTAT           0x1a
  38#define MII_CIS8201_ISTAT_STATUS    0x8000
  39#define MII_CIS8201_ISTAT_SPEED     0x4000
  40#define MII_CIS8201_ISTAT_LINK      0x2000
  41#define MII_CIS8201_ISTAT_DUPLEX    0x1000
  42
  43/* Cicada Auxiliary Control/Status Register */
  44#define MII_CIS8201_AUX_CONSTAT        0x1c
  45#define MII_CIS8201_AUXCONSTAT_INIT    0x0004
  46#define MII_CIS8201_AUXCONSTAT_DUPLEX  0x0020
  47#define MII_CIS8201_AUXCONSTAT_SPEED   0x0018
  48#define MII_CIS8201_AUXCONSTAT_GBIT    0x0010
  49#define MII_CIS8201_AUXCONSTAT_100     0x0008
  50
  51/* 88E1011 PHY Status Register */
  52#define MII_M1011_PHY_SPEC_STATUS               0x11
  53#define MII_M1011_PHY_SPEC_STATUS_1000          0x8000
  54#define MII_M1011_PHY_SPEC_STATUS_100           0x4000
  55#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK      0xc000
  56#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX    0x2000
  57#define MII_M1011_PHY_SPEC_STATUS_RESOLVED      0x0800
  58#define MII_M1011_PHY_SPEC_STATUS_LINK          0x0400
  59
  60#define MII_M1011_IEVENT                0x13
  61#define MII_M1011_IEVENT_CLEAR          0x0000
  62
  63#define MII_M1011_IMASK                 0x12
  64#define MII_M1011_IMASK_INIT            0x6400
  65#define MII_M1011_IMASK_CLEAR           0x0000
  66
  67/* 88E1111 PHY Register */
  68#define MII_M1111_PHY_EXT_CR            0x14
  69#define MII_M1111_RX_DELAY              0x80
  70#define MII_M1111_TX_DELAY              0x2
  71#define MII_M1111_PHY_EXT_SR            0x1b
  72#define MII_M1111_HWCFG_MODE_MASK       0xf
  73#define MII_M1111_HWCFG_MODE_RGMII      0xb
  74
  75#define MII_DM9161_SCR                  0x10
  76#define MII_DM9161_SCR_INIT             0x0610
  77#define MII_DM9161_SCR_RMII_INIT        0x0710
  78
  79/* DM9161 Specified Configuration and Status Register */
  80#define MII_DM9161_SCSR                 0x11
  81#define MII_DM9161_SCSR_100F            0x8000
  82#define MII_DM9161_SCSR_100H            0x4000
  83#define MII_DM9161_SCSR_10F             0x2000
  84#define MII_DM9161_SCSR_10H             0x1000
  85
  86/* DM9161 Interrupt Register */
  87#define MII_DM9161_INTR                 0x15
  88#define MII_DM9161_INTR_PEND            0x8000
  89#define MII_DM9161_INTR_DPLX_MASK       0x0800
  90#define MII_DM9161_INTR_SPD_MASK        0x0400
  91#define MII_DM9161_INTR_LINK_MASK       0x0200
  92#define MII_DM9161_INTR_MASK            0x0100
  93#define MII_DM9161_INTR_DPLX_CHANGE     0x0010
  94#define MII_DM9161_INTR_SPD_CHANGE      0x0008
  95#define MII_DM9161_INTR_LINK_CHANGE     0x0004
  96#define MII_DM9161_INTR_INIT            0x0000
  97#define MII_DM9161_INTR_STOP    \
  98                (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
  99                 MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
 100
 101/* DM9161 10BT Configuration/Status */
 102#define MII_DM9161_10BTCSR              0x12
 103#define MII_DM9161_10BTCSR_INIT         0x7800
 104
 105#define MII_BASIC_FEATURES    (SUPPORTED_10baseT_Half | \
 106                 SUPPORTED_10baseT_Full | \
 107                 SUPPORTED_100baseT_Half | \
 108                 SUPPORTED_100baseT_Full | \
 109                 SUPPORTED_Autoneg | \
 110                 SUPPORTED_TP | \
 111                 SUPPORTED_MII)
 112
 113#define MII_GBIT_FEATURES    (MII_BASIC_FEATURES | \
 114                 SUPPORTED_1000baseT_Half | \
 115                 SUPPORTED_1000baseT_Full)
 116
 117#define MII_READ_COMMAND                0x00000001
 118
 119#define MII_INTERRUPT_DISABLED          0x0
 120#define MII_INTERRUPT_ENABLED           0x1
 121
 122#define SPEED_10    10
 123#define SPEED_100   100
 124#define SPEED_1000  1000
 125
 126/* Duplex, half or full. */
 127#define DUPLEX_HALF             0x00
 128#define DUPLEX_FULL             0x01
 129
 130/* Taken from mii_if_info and sungem_phy.h */
 131struct uec_mii_info {
 132        /* Information about the PHY type */
 133        /* And management functions */
 134        struct phy_info *phyinfo;
 135
 136        struct eth_device *dev;
 137
 138        /* forced speed & duplex (no autoneg)
 139         * partner speed & duplex & pause (autoneg)
 140         */
 141        int speed;
 142        int duplex;
 143        int pause;
 144
 145        /* The most recently read link state */
 146        int link;
 147
 148        /* Enabled Interrupts */
 149        u32 interrupts;
 150
 151        u32 advertising;
 152        int autoneg;
 153        int mii_id;
 154
 155        /* private data pointer */
 156        /* For use by PHYs to maintain extra state */
 157        void *priv;
 158
 159        /* Provided by ethernet driver */
 160        int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
 161        void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
 162                           int val);
 163};
 164
 165/* struct phy_info: a structure which defines attributes for a PHY
 166 *
 167 * id will contain a number which represents the PHY.  During
 168 * startup, the driver will poll the PHY to find out what its
 169 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 170 * gotten from the PHY will be ANDed with phy_id_mask to
 171 * discard any bits which may change based on revision numbers
 172 * unimportant to functionality
 173 *
 174 * There are 6 commands which take a ugeth_mii_info structure.
 175 * Each PHY must declare config_aneg, and read_status.
 176 */
 177struct phy_info {
 178        u32 phy_id;
 179        char *name;
 180        unsigned int phy_id_mask;
 181        u32 features;
 182
 183        /* Called to initialize the PHY */
 184        int (*init)(struct uec_mii_info *mii_info);
 185
 186        /* Called to suspend the PHY for power */
 187        int (*suspend)(struct uec_mii_info *mii_info);
 188
 189        /* Reconfigures autonegotiation (or disables it) */
 190        int (*config_aneg)(struct uec_mii_info *mii_info);
 191
 192        /* Determines the negotiated speed and duplex */
 193        int (*read_status)(struct uec_mii_info *mii_info);
 194
 195        /* Clears any pending interrupts */
 196        int (*ack_interrupt)(struct uec_mii_info *mii_info);
 197
 198        /* Enables or disables interrupts */
 199        int (*config_intr)(struct uec_mii_info *mii_info);
 200
 201        /* Clears up any memory if needed */
 202        void (*close)(struct uec_mii_info *mii_info);
 203};
 204
 205struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
 206void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
 207                       int value);
 208int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
 209void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
 210void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
 211                                 u32 interrupts);
 212void change_phy_interface_mode(struct eth_device *dev,
 213                               phy_interface_t type, int speed);
 214#endif /* __UEC_PHY_H__ */
 215