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8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <errno.h>
12#include <malloc.h>
13#include <watchdog.h>
14#include <serial.h>
15#include <debug_uart.h>
16#include <asm/global_data.h>
17#include <linux/compiler.h>
18#include <linux/delay.h>
19
20#include <asm/io.h>
21#ifdef CONFIG_DM_SERIAL
22#include <asm/arch/atmel_serial.h>
23#endif
24#include <asm/arch/clk.h>
25#include <asm/arch/hardware.h>
26
27#include "atmel_usart.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#ifndef CONFIG_DM_SERIAL
32static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
33 int baudrate)
34{
35 unsigned long divisor;
36 unsigned long usart_hz;
37
38
39
40
41
42
43 usart_hz = get_usart_clk_rate(id);
44 divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
45 writel(USART3_BF(CD, divisor), &usart->brgr);
46}
47
48static void atmel_serial_init_internal(atmel_usart3_t *usart)
49{
50
51
52
53
54 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
55 __udelay(1000);
56
57 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
58}
59
60static void atmel_serial_activate(atmel_usart3_t *usart)
61{
62 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
63 | USART3_BF(USCLKS, USART3_USCLKS_MCK)
64 | USART3_BF(CHRL, USART3_CHRL_8)
65 | USART3_BF(PAR, USART3_PAR_NONE)
66 | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
67 &usart->mr);
68 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
69
70 __udelay(100);
71}
72
73static void atmel_serial_setbrg(void)
74{
75 atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
76 CONFIG_USART_ID, gd->baudrate);
77}
78
79static int atmel_serial_init(void)
80{
81 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
82
83 atmel_serial_init_internal(usart);
84 serial_setbrg();
85 atmel_serial_activate(usart);
86
87 return 0;
88}
89
90static void atmel_serial_putc(char c)
91{
92 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
93
94 if (c == '\n')
95 serial_putc('\r');
96
97 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
98 writel(c, &usart->thr);
99}
100
101static int atmel_serial_getc(void)
102{
103 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
104
105 while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
106 WATCHDOG_RESET();
107 return readl(&usart->rhr);
108}
109
110static int atmel_serial_tstc(void)
111{
112 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
113 return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
114}
115
116static struct serial_device atmel_serial_drv = {
117 .name = "atmel_serial",
118 .start = atmel_serial_init,
119 .stop = NULL,
120 .setbrg = atmel_serial_setbrg,
121 .putc = atmel_serial_putc,
122 .puts = default_serial_puts,
123 .getc = atmel_serial_getc,
124 .tstc = atmel_serial_tstc,
125};
126
127void atmel_serial_initialize(void)
128{
129 serial_register(&atmel_serial_drv);
130}
131
132__weak struct serial_device *default_serial_console(void)
133{
134 return &atmel_serial_drv;
135}
136#endif
137
138#ifdef CONFIG_DM_SERIAL
139enum serial_clk_type {
140 CLK_TYPE_NORMAL = 0,
141 CLK_TYPE_DBGU,
142};
143
144struct atmel_serial_priv {
145 atmel_usart3_t *usart;
146 ulong usart_clk_rate;
147};
148
149static void _atmel_serial_set_brg(atmel_usart3_t *usart,
150 ulong usart_clk_rate, int baudrate)
151{
152 unsigned long divisor;
153
154 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
155 writel(USART3_BF(CD, divisor), &usart->brgr);
156}
157
158void _atmel_serial_init(atmel_usart3_t *usart,
159 ulong usart_clk_rate, int baudrate)
160{
161 writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
162
163 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
164 USART3_BF(USCLKS, USART3_USCLKS_MCK) |
165 USART3_BF(CHRL, USART3_CHRL_8) |
166 USART3_BF(PAR, USART3_PAR_NONE) |
167 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
168
169 _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
170
171 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
172 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
173}
174
175int atmel_serial_setbrg(struct udevice *dev, int baudrate)
176{
177 struct atmel_serial_priv *priv = dev_get_priv(dev);
178
179 _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
180
181 return 0;
182}
183
184static int atmel_serial_getc(struct udevice *dev)
185{
186 struct atmel_serial_priv *priv = dev_get_priv(dev);
187
188 if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
189 return -EAGAIN;
190
191 return readl(&priv->usart->rhr);
192}
193
194static int atmel_serial_putc(struct udevice *dev, const char ch)
195{
196 struct atmel_serial_priv *priv = dev_get_priv(dev);
197
198 if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
199 return -EAGAIN;
200
201 writel(ch, &priv->usart->thr);
202
203 return 0;
204}
205
206static int atmel_serial_pending(struct udevice *dev, bool input)
207{
208 struct atmel_serial_priv *priv = dev_get_priv(dev);
209 uint32_t csr = readl(&priv->usart->csr);
210
211 if (input)
212 return csr & USART3_BIT(RXRDY) ? 1 : 0;
213 else
214 return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
215}
216
217static const struct dm_serial_ops atmel_serial_ops = {
218 .putc = atmel_serial_putc,
219 .pending = atmel_serial_pending,
220 .getc = atmel_serial_getc,
221 .setbrg = atmel_serial_setbrg,
222};
223
224#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
225static int atmel_serial_enable_clk(struct udevice *dev)
226{
227 struct atmel_serial_priv *priv = dev_get_priv(dev);
228
229
230 priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
231
232 return 0;
233}
234#else
235static int atmel_serial_enable_clk(struct udevice *dev)
236{
237 struct atmel_serial_priv *priv = dev_get_priv(dev);
238 struct clk clk;
239 ulong clk_rate;
240 int ret;
241
242 ret = clk_get_by_index(dev, 0, &clk);
243 if (ret)
244 return -EINVAL;
245
246 if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
247 ret = clk_enable(&clk);
248 if (ret)
249 return ret;
250 }
251
252 clk_rate = clk_get_rate(&clk);
253 if (!clk_rate)
254 return -EINVAL;
255
256 priv->usart_clk_rate = clk_rate;
257
258 clk_free(&clk);
259
260 return 0;
261}
262#endif
263
264static int atmel_serial_probe(struct udevice *dev)
265{
266 struct atmel_serial_plat *plat = dev_get_plat(dev);
267 struct atmel_serial_priv *priv = dev_get_priv(dev);
268 int ret;
269#if CONFIG_IS_ENABLED(OF_CONTROL)
270 fdt_addr_t addr_base;
271
272 addr_base = dev_read_addr(dev);
273 if (addr_base == FDT_ADDR_T_NONE)
274 return -ENODEV;
275
276 plat->base_addr = (uint32_t)addr_base;
277#endif
278 priv->usart = (atmel_usart3_t *)plat->base_addr;
279
280 ret = atmel_serial_enable_clk(dev);
281 if (ret)
282 return ret;
283
284 _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
285
286 return 0;
287}
288
289#if CONFIG_IS_ENABLED(OF_CONTROL)
290static const struct udevice_id atmel_serial_ids[] = {
291 {
292 .compatible = "atmel,at91sam9260-dbgu",
293 .data = CLK_TYPE_DBGU,
294 },
295 {
296 .compatible = "atmel,at91sam9260-usart",
297 .data = CLK_TYPE_NORMAL,
298 },
299 { }
300};
301#endif
302
303U_BOOT_DRIVER(serial_atmel) = {
304 .name = "serial_atmel",
305 .id = UCLASS_SERIAL,
306#if CONFIG_IS_ENABLED(OF_CONTROL)
307 .of_match = atmel_serial_ids,
308 .plat_auto = sizeof(struct atmel_serial_plat),
309#endif
310 .probe = atmel_serial_probe,
311 .ops = &atmel_serial_ops,
312#if !CONFIG_IS_ENABLED(OF_CONTROL)
313 .flags = DM_FLAG_PRE_RELOC,
314#endif
315 .priv_auto = sizeof(struct atmel_serial_priv),
316};
317#endif
318
319#ifdef CONFIG_DEBUG_UART_ATMEL
320static inline void _debug_uart_init(void)
321{
322 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
323
324 _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
325}
326
327static inline void _debug_uart_putc(int ch)
328{
329 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
330
331 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
332 ;
333
334 writel(ch, &usart->thr);
335}
336
337DEBUG_UART_FUNCS
338#endif
339
