LXR uboot/drivers/serial/serial

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
   4 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
   5 *
   6 * Modified to add device model (DM) support
   7 * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
   8 *
   9 * Modified to add DM and fdt support, removed non DM code
  10 * (C) Copyright 2018  Angelo Dureghello <angelo@sysam.it>
  11 */
  12
  13/*
  14 * Minimal serial functions needed to use one of the uart ports
  15 * as serial console interface.
  16 */
  17
  18#include <common.h>
  19#include <dm.h>
  20#include <asm/global_data.h>
  21#include <dm/platform_data/serial_coldfire.h>
  22#include <serial.h>
  23#include <linux/compiler.h>
  24#include <asm/immap.h>
  25#include <asm/uart.h>
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29extern void uart_port_conf(int port);
  30
  31static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
  32{
  33        u32 counter;
  34
  35        uart_port_conf(port_idx);
  36
  37        /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  38        writeb(UART_UCR_RESET_RX, &uart->ucr);
  39        writeb(UART_UCR_RESET_TX, &uart->ucr);
  40        writeb(UART_UCR_RESET_ERROR, &uart->ucr);
  41        writeb(UART_UCR_RESET_MR, &uart->ucr);
  42        __asm__("nop");
  43
  44        writeb(0, &uart->uimr);
  45
  46        /* write to CSR: RX/TX baud rate from timers */
  47        writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
  48
  49        writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
  50        writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
  51
  52        /* Setting up BaudRate */
  53        counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  54        counter = counter / baudrate;
  55
  56        /* write to CTUR: divide counter upper byte */
  57        writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
  58        /* write to CTLR: divide counter lower byte */
  59        writeb((u8)(counter & 0x00ff), &uart->ubg2);
  60
  61        writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  62
  63        return (0);
  64}
  65
  66static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
  67{
  68        u32 counter;
  69
  70        /* Setting up BaudRate */
  71        counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  72        counter = counter / baudrate;
  73
  74        /* write to CTUR: divide counter upper byte */
  75        writeb(((counter & 0xff00) >> 8), &uart->ubg1);
  76        /* write to CTLR: divide counter lower byte */
  77        writeb((counter & 0x00ff), &uart->ubg2);
  78
  79        writeb(UART_UCR_RESET_RX, &uart->ucr);
  80        writeb(UART_UCR_RESET_TX, &uart->ucr);
  81
  82        writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  83}
  84
  85static int coldfire_serial_probe(struct udevice *dev)
  86{
  87        struct coldfire_serial_plat *plat = dev_get_plat(dev);
  88
  89        plat->port = dev_seq(dev);
  90
  91        return mcf_serial_init_common((uart_t *)plat->base,
  92                                                plat->port, plat->baudrate);
  93}
  94
  95static int coldfire_serial_putc(struct udevice *dev, const char ch)
  96{
  97        struct coldfire_serial_plat *plat = dev_get_plat(dev);
  98        uart_t *uart = (uart_t *)plat->base;
  99
 100        /* Wait for last character to go. */
 101        if (!(readb(&uart->usr) & UART_USR_TXRDY))
 102                return -EAGAIN;
 103
 104        writeb(ch, &uart->utb);
 105
 106        return 0;
 107}
 108
 109static int coldfire_serial_getc(struct udevice *dev)
 110{
 111        struct coldfire_serial_plat *plat = dev_get_plat(dev);
 112        uart_t *uart = (uart_t *)(plat->base);
 113
 114        /* Wait for a character to arrive. */
 115        if (!(readb(&uart->usr) & UART_USR_RXRDY))
 116                return -EAGAIN;
 117
 118        return readb(&uart->urb);
 119}
 120
 121int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
 122{
 123        struct coldfire_serial_plat *plat = dev_get_plat(dev);
 124        uart_t *uart = (uart_t *)(plat->base);
 125
 126        mcf_serial_setbrg_common(uart, baudrate);
 127
 128        return 0;
 129}
 130
 131static int coldfire_serial_pending(struct udevice *dev, bool input)
 132{
 133        struct coldfire_serial_plat *plat = dev_get_plat(dev);
 134        uart_t *uart = (uart_t *)(plat->base);
 135
 136        if (input)
 137                return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
 138        else
 139                return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
 140
 141        return 0;
 142}
 143
 144static int coldfire_of_to_plat(struct udevice *dev)
 145{
 146        struct coldfire_serial_plat *plat = dev_get_plat(dev);
 147        fdt_addr_t addr_base;
 148
 149        addr_base = dev_read_addr(dev);
 150        if (addr_base == FDT_ADDR_T_NONE)
 151                return -ENODEV;
 152
 153        plat->base = (uint32_t)addr_base;
 154        plat->baudrate = gd->baudrate;
 155
 156        return 0;
 157}
 158
 159static const struct dm_serial_ops coldfire_serial_ops = {
 160        .putc = coldfire_serial_putc,
 161        .pending = coldfire_serial_pending,
 162        .getc = coldfire_serial_getc,
 163        .setbrg = coldfire_serial_setbrg,
 164};
 165
 166static const struct udevice_id coldfire_serial_ids[] = {
 167        { .compatible = "fsl,mcf-uart" },
 168        { }
 169};
 170
 171U_BOOT_DRIVER(serial_coldfire) = {
 172        .name = "serial_coldfire",
 173        .id = UCLASS_SERIAL,
 174        .of_match = coldfire_serial_ids,
 175        .of_to_plat = coldfire_of_to_plat,
 176        .plat_auto      = sizeof(struct coldfire_serial_plat),
 177        .probe = coldfire_serial_probe,
 178        .ops = &coldfire_serial_ops,
 179        .flags = DM_FLAG_PRE_RELOC,
 180};
 181