LXR uboot/drivers/serial/serial

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Qualcomm UART driver
   4 *
   5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
   6 *
   7 * UART will work in Data Mover mode.
   8 * Based on Linux driver.
   9 */
  10
  11#include <common.h>
  12#include <clk.h>
  13#include <dm.h>
  14#include <errno.h>
  15#include <malloc.h>
  16#include <serial.h>
  17#include <watchdog.h>
  18#include <asm/global_data.h>
  19#include <asm/io.h>
  20#include <linux/compiler.h>
  21#include <linux/delay.h>
  22#include <dm/pinctrl.h>
  23
  24/* Serial registers - this driver works in uartdm mode*/
  25
  26#define UARTDM_DMRX             0x34 /* Max RX transfer length */
  27#define UARTDM_DMEN             0x3C /* DMA/data-packing mode */
  28#define UARTDM_NCF_TX           0x40 /* Number of chars to TX */
  29
  30#define UARTDM_RXFS             0x50 /* RX channel status register */
  31#define UARTDM_RXFS_BUF_SHIFT   0x7  /* Number of bytes in the packing buffer */
  32#define UARTDM_RXFS_BUF_MASK    0x7
  33#define UARTDM_MR1                               0x00
  34#define UARTDM_MR2                               0x04
  35#define UARTDM_CSR                               0xA0
  36
  37#define UARTDM_SR                0xA4 /* Status register */
  38#define UARTDM_SR_RX_READY       (1 << 0) /* Word is the receiver FIFO */
  39#define UARTDM_SR_TX_EMPTY       (1 << 3) /* Transmitter underrun */
  40#define UARTDM_SR_UART_OVERRUN   (1 << 4) /* Receive overrun */
  41
  42#define UARTDM_CR                         0xA8 /* Command register */
  43#define UARTDM_CR_CMD_RESET_ERR           (3 << 4) /* Clear overrun error */
  44#define UARTDM_CR_CMD_RESET_STALE_INT     (8 << 4) /* Clears stale irq */
  45#define UARTDM_CR_CMD_RESET_TX_READY      (3 << 8) /* Clears TX Ready irq*/
  46#define UARTDM_CR_CMD_FORCE_STALE         (4 << 8) /* Causes stale event */
  47#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
  48
  49#define UARTDM_IMR                0xB0 /* Interrupt mask register */
  50#define UARTDM_ISR                0xB4 /* Interrupt status register */
  51#define UARTDM_ISR_TX_READY       0x80 /* TX FIFO empty */
  52
  53#define UARTDM_TF               0x100 /* UART Transmit FIFO register */
  54#define UARTDM_RF               0x140 /* UART Receive FIFO register */
  55
  56#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
  57#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
  58#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
  59#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
  60
  61DECLARE_GLOBAL_DATA_PTR;
  62
  63struct msm_serial_data {
  64        phys_addr_t base;
  65        unsigned chars_cnt; /* number of buffered chars */
  66        uint32_t chars_buf; /* buffered chars */
  67        uint32_t clk_bit_rate; /* data mover mode bit rate register value */
  68};
  69
  70static int msm_serial_fetch(struct udevice *dev)
  71{
  72        struct msm_serial_data *priv = dev_get_priv(dev);
  73        unsigned sr;
  74
  75        if (priv->chars_cnt)
  76                return priv->chars_cnt;
  77
  78        /* Clear error in case of buffer overrun */
  79        if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
  80                writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
  81
  82        /* We need to fetch new character */
  83        sr = readl(priv->base + UARTDM_SR);
  84
  85        if (sr & UARTDM_SR_RX_READY) {
  86                /* There are at least 4 bytes in fifo */
  87                priv->chars_buf = readl(priv->base + UARTDM_RF);
  88                priv->chars_cnt = 4;
  89        } else {
  90                /* Check if there is anything in fifo */
  91                priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
  92                /* Extract number of characters in UART packing buffer*/
  93                priv->chars_cnt = (priv->chars_cnt >>
  94                                   UARTDM_RXFS_BUF_SHIFT) &
  95                                  UARTDM_RXFS_BUF_MASK;
  96                if (!priv->chars_cnt)
  97                        return 0;
  98
  99                /* There is at least one charcter, move it to fifo */
 100                writel(UARTDM_CR_CMD_FORCE_STALE,
 101                       priv->base + UARTDM_CR);
 102
 103                priv->chars_buf = readl(priv->base + UARTDM_RF);
 104                writel(UARTDM_CR_CMD_RESET_STALE_INT,
 105                       priv->base + UARTDM_CR);
 106                writel(0x7, priv->base + UARTDM_DMRX);
 107        }
 108
 109        return priv->chars_cnt;
 110}
 111
 112static int msm_serial_getc(struct udevice *dev)
 113{
 114        struct msm_serial_data *priv = dev_get_priv(dev);
 115        char c;
 116
 117        if (!msm_serial_fetch(dev))
 118                return -EAGAIN;
 119
 120        c = priv->chars_buf & 0xFF;
 121        priv->chars_buf >>= 8;
 122        priv->chars_cnt--;
 123
 124        return c;
 125}
 126
 127static int msm_serial_putc(struct udevice *dev, const char ch)
 128{
 129        struct msm_serial_data *priv = dev_get_priv(dev);
 130
 131        if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
 132            !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
 133                return -EAGAIN;
 134
 135        writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
 136
 137        writel(1, priv->base + UARTDM_NCF_TX);
 138        writel(ch, priv->base + UARTDM_TF);
 139
 140        return 0;
 141}
 142
 143static int msm_serial_pending(struct udevice *dev, bool input)
 144{
 145        if (input) {
 146                if (msm_serial_fetch(dev))
 147                        return 1;
 148        }
 149
 150        return 0;
 151}
 152
 153static const struct dm_serial_ops msm_serial_ops = {
 154        .putc = msm_serial_putc,
 155        .pending = msm_serial_pending,
 156        .getc = msm_serial_getc,
 157};
 158
 159static int msm_uart_clk_init(struct udevice *dev)
 160{
 161        uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 162                                        "clock-frequency", 115200);
 163        uint clkd[2]; /* clk_id and clk_no */
 164        int clk_offset;
 165        struct udevice *clk_dev;
 166        struct clk clk;
 167        int ret;
 168
 169        ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
 170                                   clkd, 2);
 171        if (ret)
 172                return ret;
 173
 174        clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
 175        if (clk_offset < 0)
 176                return clk_offset;
 177
 178        ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 179        if (ret)
 180                return ret;
 181
 182        clk.id = clkd[1];
 183        ret = clk_request(clk_dev, &clk);
 184        if (ret < 0)
 185                return ret;
 186
 187        ret = clk_set_rate(&clk, clk_rate);
 188        clk_free(&clk);
 189        if (ret < 0)
 190                return ret;
 191
 192        return 0;
 193}
 194
 195static void uart_dm_init(struct msm_serial_data *priv)
 196{
 197        /* Delay initialization for a bit to let pins stabilize if necessary */
 198        mdelay(5);
 199
 200        writel(priv->clk_bit_rate, priv->base + UARTDM_CSR);
 201        writel(0x0, priv->base + UARTDM_MR1);
 202        writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
 203        writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
 204        writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
 205
 206        /* Make sure BAM/single character mode is disabled */
 207        writel(0x0, priv->base + UARTDM_DMEN);
 208}
 209static int msm_serial_probe(struct udevice *dev)
 210{
 211        int ret;
 212        struct msm_serial_data *priv = dev_get_priv(dev);
 213
 214        /* No need to reinitialize the UART after relocation */
 215        if (gd->flags & GD_FLG_RELOC)
 216                return 0;
 217
 218        ret = msm_uart_clk_init(dev);
 219        if (ret)
 220                return ret;
 221
 222        pinctrl_select_state(dev, "uart");
 223        uart_dm_init(priv);
 224
 225        return 0;
 226}
 227
 228static int msm_serial_of_to_plat(struct udevice *dev)
 229{
 230        struct msm_serial_data *priv = dev_get_priv(dev);
 231
 232        priv->base = dev_read_addr(dev);
 233        if (priv->base == FDT_ADDR_T_NONE)
 234                return -EINVAL;
 235
 236        priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 237                                                        "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE);
 238
 239        return 0;
 240}
 241
 242static const struct udevice_id msm_serial_ids[] = {
 243        { .compatible = "qcom,msm-uartdm-v1.4" },
 244        { }
 245};
 246
 247U_BOOT_DRIVER(serial_msm) = {
 248        .name   = "serial_msm",
 249        .id     = UCLASS_SERIAL,
 250        .of_match = msm_serial_ids,
 251        .of_to_plat = msm_serial_of_to_plat,
 252        .priv_auto      = sizeof(struct msm_serial_data),
 253        .probe = msm_serial_probe,
 254        .ops    = &msm_serial_ops,
 255};
 256