LXR uboot/drivers/serial/serial

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
   4 */
   5
   6#include <common.h>
   7#include <dm.h>
   8#include <errno.h>
   9#include <watchdog.h>
  10#include <asm/arch/imx-regs.h>
  11#include <asm/arch/clock.h>
  12#include <asm/global_data.h>
  13#include <dm/platform_data/serial_mxc.h>
  14#include <serial.h>
  15#include <linux/compiler.h>
  16
  17/* UART Control Register Bit Fields.*/
  18#define URXD_CHARRDY    (1<<15)
  19#define URXD_ERR        (1<<14)
  20#define URXD_OVRRUN     (1<<13)
  21#define URXD_FRMERR     (1<<12)
  22#define URXD_BRK        (1<<11)
  23#define URXD_PRERR      (1<<10)
  24#define URXD_RX_DATA    (0xFF)
  25#define UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
  26#define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  27#define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  28#define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  29#define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  30#define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  31#define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  32#define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  33#define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  34#define UCR1_SNDBRK     (1<<4)  /* Send break */
  35#define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  36#define UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
  37#define UCR1_DOZE       (1<<1)  /* Doze */
  38#define UCR1_UARTEN     (1<<0)  /* UART enabled */
  39#define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  40#define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  41#define UCR2_CTSC       (1<<13) /* CTS pin control */
  42#define UCR2_CTS        (1<<12) /* Clear to send */
  43#define UCR2_ESCEN      (1<<11) /* Escape enable */
  44#define UCR2_PREN       (1<<8)  /* Parity enable */
  45#define UCR2_PROE       (1<<7)  /* Parity odd/even */
  46#define UCR2_STPB       (1<<6)  /* Stop */
  47#define UCR2_WS         (1<<5)  /* Word size */
  48#define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  49#define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  50#define UCR2_RXEN       (1<<1)  /* Receiver enabled */
  51#define UCR2_SRST       (1<<0)  /* SW reset */
  52#define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
  53#define UCR3_PARERREN   (1<<12) /* Parity enable */
  54#define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
  55#define UCR3_DSR        (1<<10) /* Data set ready */
  56#define UCR3_DCD        (1<<9)  /* Data carrier detect */
  57#define UCR3_RI         (1<<8)  /* Ring indicator */
  58#define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
  59#define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
  60#define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
  61#define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
  62#define UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
  63#define UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
  64#define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
  65#define UCR3_BPEN       (1<<0)  /* Preset registers enable */
  66#define UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
  67#define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
  68#define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
  69#define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
  70#define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
  71#define UCR4_IRSC       (1<<5)  /* IR special case */
  72#define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
  73#define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
  74#define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
  75#define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
  76#define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
  77#define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
  78#define UFCR_RFDIV_SHF  7       /* Reference freq divider shift */
  79#define RFDIV           4       /* divide input clock by 2 */
  80#define UFCR_DCEDTE     (1<<6)  /* DTE mode select */
  81#define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
  82#define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
  83#define USR1_RTSS       (1<<14) /* RTS pin status */
  84#define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
  85#define USR1_RTSD       (1<<12) /* RTS delta */
  86#define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
  87#define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
  88#define USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
  89#define USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
  90#define USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
  91#define USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
  92#define USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
  93#define USR2_ADET       (1<<15) /* Auto baud rate detect complete */
  94#define USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
  95#define USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
  96#define USR2_IDLE       (1<<12) /* Idle condition */
  97#define USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
  98#define USR2_WAKE       (1<<7)  /* Wake */
  99#define USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
 100#define USR2_TXDC       (1<<3)  /* Transmitter complete */
 101#define USR2_BRCD       (1<<2)  /* Break condition */
 102#define USR2_ORE        (1<<1)  /* Overrun error */
 103#define USR2_RDR        (1<<0)  /* Recv data ready */
 104#define UTS_FRCPERR     (1<<13) /* Force parity error */
 105#define UTS_LOOP        (1<<12) /* Loop tx and rx */
 106#define UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
 107#define UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
 108#define UTS_TXFULL      (1<<4)  /* TxFIFO full */
 109#define UTS_RXFULL      (1<<3)  /* RxFIFO full */
 110#define UTS_SOFTRS      (1<<0)  /* Software reset */
 111#define TXTL            2  /* reset default */
 112#define RXTL            1  /* reset default */
 113
 114DECLARE_GLOBAL_DATA_PTR;
 115
 116struct mxc_uart {
 117        u32 rxd;
 118        u32 spare0[15];
 119
 120        u32 txd;
 121        u32 spare1[15];
 122
 123        u32 cr1;
 124        u32 cr2;
 125        u32 cr3;
 126        u32 cr4;
 127
 128        u32 fcr;
 129        u32 sr1;
 130        u32 sr2;
 131        u32 esc;
 132
 133        u32 tim;
 134        u32 bir;
 135        u32 bmr;
 136        u32 brc;
 137
 138        u32 onems;
 139        u32 ts;
 140};
 141
 142static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
 143{
 144        writel(0, &base->cr1);
 145        writel(0, &base->cr2);
 146
 147        while (!(readl(&base->cr2) & UCR2_SRST));
 148
 149        if (use_dte)
 150                writel(0x404 | UCR3_ADNIMP, &base->cr3);
 151        else
 152                writel(0x704 | UCR3_ADNIMP, &base->cr3);
 153
 154        writel(0x704 | UCR3_ADNIMP, &base->cr3);
 155        writel(0x8000, &base->cr4);
 156        writel(0x2b, &base->esc);
 157        writel(0, &base->tim);
 158
 159        writel(0, &base->ts);
 160}
 161
 162static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
 163                               unsigned long baudrate, bool use_dte)
 164{
 165        u32 tmp;
 166
 167        tmp = RFDIV << UFCR_RFDIV_SHF;
 168        if (use_dte)
 169                tmp |= UFCR_DCEDTE;
 170        else
 171                tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
 172        writel(tmp, &base->fcr);
 173
 174        writel(0xf, &base->bir);
 175        writel(clk / (2 * baudrate), &base->bmr);
 176
 177        writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
 178               &base->cr2);
 179        writel(UCR1_UARTEN, &base->cr1);
 180}
 181
 182#if !CONFIG_IS_ENABLED(DM_SERIAL)
 183
 184#ifndef CONFIG_MXC_UART_BASE
 185#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
 186#endif
 187
 188#define mxc_base        ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
 189
 190static void mxc_serial_setbrg(void)
 191{
 192        u32 clk = imx_get_uartclk();
 193
 194        if (!gd->baudrate)
 195                gd->baudrate = CONFIG_BAUDRATE;
 196
 197        _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
 198}
 199
 200static int mxc_serial_getc(void)
 201{
 202        while (readl(&mxc_base->ts) & UTS_RXEMPTY)
 203                WATCHDOG_RESET();
 204        return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
 205}
 206
 207static void mxc_serial_putc(const char c)
 208{
 209        /* If \n, also do \r */
 210        if (c == '\n')
 211                serial_putc('\r');
 212
 213        writel(c, &mxc_base->txd);
 214
 215        /* wait for transmitter to be ready */
 216        while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
 217                WATCHDOG_RESET();
 218}
 219
 220/* Test whether a character is in the RX buffer */
 221static int mxc_serial_tstc(void)
 222{
 223        /* If receive fifo is empty, return false */
 224        if (readl(&mxc_base->ts) & UTS_RXEMPTY)
 225                return 0;
 226        return 1;
 227}
 228
 229/*
 230 * Initialise the serial port with the given baudrate. The settings
 231 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 232 */
 233static int mxc_serial_init(void)
 234{
 235        _mxc_serial_init(mxc_base, false);
 236
 237        serial_setbrg();
 238
 239        return 0;
 240}
 241
 242static struct serial_device mxc_serial_drv = {
 243        .name   = "mxc_serial",
 244        .start  = mxc_serial_init,
 245        .stop   = NULL,
 246        .setbrg = mxc_serial_setbrg,
 247        .putc   = mxc_serial_putc,
 248        .puts   = default_serial_puts,
 249        .getc   = mxc_serial_getc,
 250        .tstc   = mxc_serial_tstc,
 251};
 252
 253void mxc_serial_initialize(void)
 254{
 255        serial_register(&mxc_serial_drv);
 256}
 257
 258__weak struct serial_device *default_serial_console(void)
 259{
 260        return &mxc_serial_drv;
 261}
 262#endif
 263
 264#if CONFIG_IS_ENABLED(DM_SERIAL)
 265
 266int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 267{
 268        struct mxc_serial_plat *plat = dev_get_plat(dev);
 269        u32 clk = imx_get_uartclk();
 270
 271        _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
 272
 273        return 0;
 274}
 275
 276static int mxc_serial_probe(struct udevice *dev)
 277{
 278        struct mxc_serial_plat *plat = dev_get_plat(dev);
 279
 280        _mxc_serial_init(plat->reg, plat->use_dte);
 281
 282        return 0;
 283}
 284
 285static int mxc_serial_getc(struct udevice *dev)
 286{
 287        struct mxc_serial_plat *plat = dev_get_plat(dev);
 288        struct mxc_uart *const uart = plat->reg;
 289
 290        if (readl(&uart->ts) & UTS_RXEMPTY)
 291                return -EAGAIN;
 292
 293        return readl(&uart->rxd) & URXD_RX_DATA;
 294}
 295
 296static int mxc_serial_putc(struct udevice *dev, const char ch)
 297{
 298        struct mxc_serial_plat *plat = dev_get_plat(dev);
 299        struct mxc_uart *const uart = plat->reg;
 300
 301        if (!(readl(&uart->ts) & UTS_TXEMPTY))
 302                return -EAGAIN;
 303
 304        writel(ch, &uart->txd);
 305
 306        return 0;
 307}
 308
 309static int mxc_serial_pending(struct udevice *dev, bool input)
 310{
 311        struct mxc_serial_plat *plat = dev_get_plat(dev);
 312        struct mxc_uart *const uart = plat->reg;
 313        uint32_t sr2 = readl(&uart->sr2);
 314
 315        if (input)
 316                return sr2 & USR2_RDR ? 1 : 0;
 317        else
 318                return sr2 & USR2_TXDC ? 0 : 1;
 319}
 320
 321static const struct dm_serial_ops mxc_serial_ops = {
 322        .putc = mxc_serial_putc,
 323        .pending = mxc_serial_pending,
 324        .getc = mxc_serial_getc,
 325        .setbrg = mxc_serial_setbrg,
 326};
 327
 328#if CONFIG_IS_ENABLED(OF_CONTROL)
 329static int mxc_serial_of_to_plat(struct udevice *dev)
 330{
 331        struct mxc_serial_plat *plat = dev_get_plat(dev);
 332        fdt_addr_t addr;
 333
 334        addr = dev_read_addr(dev);
 335        if (addr == FDT_ADDR_T_NONE)
 336                return -EINVAL;
 337
 338        plat->reg = (struct mxc_uart *)addr;
 339
 340        plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
 341                                        "fsl,dte-mode");
 342        return 0;
 343}
 344
 345static const struct udevice_id mxc_serial_ids[] = {
 346        { .compatible = "fsl,imx21-uart" },
 347        { .compatible = "fsl,imx53-uart" },
 348        { .compatible = "fsl,imx6sx-uart" },
 349        { .compatible = "fsl,imx6ul-uart" },
 350        { .compatible = "fsl,imx7d-uart" },
 351        { .compatible = "fsl,imx6q-uart" },
 352        { }
 353};
 354#endif
 355
 356U_BOOT_DRIVER(serial_mxc) = {
 357        .name   = "serial_mxc",
 358        .id     = UCLASS_SERIAL,
 359#if CONFIG_IS_ENABLED(OF_CONTROL)
 360        .of_match = mxc_serial_ids,
 361        .of_to_plat = mxc_serial_of_to_plat,
 362        .plat_auto      = sizeof(struct mxc_serial_plat),
 363#endif
 364        .probe = mxc_serial_probe,
 365        .ops    = &mxc_serial_ops,
 366        .flags = DM_FLAG_PRE_RELOC,
 367};
 368#endif
 369
 370#ifdef CONFIG_DEBUG_UART_MXC
 371#include <debug_uart.h>
 372
 373static inline void _debug_uart_init(void)
 374{
 375        struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
 376
 377        _mxc_serial_init(base, false);
 378        _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
 379                           CONFIG_BAUDRATE, false);
 380}
 381
 382static inline void _debug_uart_putc(int ch)
 383{
 384        struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
 385
 386        while (!(readl(&base->ts) & UTS_TXEMPTY))
 387                WATCHDOG_RESET();
 388
 389        writel(ch, &base->txd);
 390}
 391
 392DEBUG_UART_FUNCS
 393
 394#endif
 395