LXR uboot/drivers/soc/soc_xilinx

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Xilinx ZynqMP SOC driver
   4 *
   5 * Copyright (C) 2021 Xilinx, Inc.
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <asm/cache.h>
  11#include <soc.h>
  12#include <zynqmp_firmware.h>
  13#include <asm/arch/sys_proto.h>
  14#include <asm/arch/hardware.h>
  15
  16/*
  17 * Zynqmp has 4 silicon revisions
  18 * v0 -> 0(XCZU9EG-ES1)
  19 * v1 -> 1(XCZU3EG-ES1, XCZU15EG-ES1)
  20 * v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1)
  21 * v3 -> 3(Production Level)
  22 */
  23static const char zynqmp_family[] = "ZynqMP";
  24
  25struct soc_xilinx_zynqmp_priv {
  26        const char *family;
  27        char revision;
  28};
  29
  30static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size)
  31{
  32        struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
  33
  34        return snprintf(buf, size, "%s", priv->family);
  35}
  36
  37static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size)
  38{
  39        struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
  40
  41        return snprintf(buf, size, "v%d", priv->revision);
  42}
  43
  44static const struct soc_ops soc_xilinx_zynqmp_ops = {
  45        .get_family = soc_xilinx_zynqmp_get_family,
  46        .get_revision = soc_xilinx_zynqmp_get_revision,
  47};
  48
  49static int soc_xilinx_zynqmp_probe(struct udevice *dev)
  50{
  51        struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
  52        u32 ret_payload[4];
  53        int ret;
  54
  55        priv->family = zynqmp_family;
  56
  57        if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 ||
  58            !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
  59                ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]);
  60        else
  61                ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
  62                                        ret_payload);
  63        if (ret < 0)
  64                return ret;
  65
  66        priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK;
  67
  68        return 0;
  69}
  70
  71U_BOOT_DRIVER(soc_xilinx_zynqmp) = {
  72        .name           = "soc_xilinx_zynqmp",
  73        .id             = UCLASS_SOC,
  74        .ops            = &soc_xilinx_zynqmp_ops,
  75        .probe          = soc_xilinx_zynqmp_probe,
  76        .priv_auto      = sizeof(struct soc_xilinx_zynqmp_priv),
  77        .flags          = DM_FLAG_PRE_RELOC,
  78};
  79