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26#include <common.h>
27#include <dm.h>
28#include <dm/device_compat.h>
29#include <log.h>
30#include <spi.h>
31#include <spi-mem.h>
32#include <asm/global_data.h>
33#include <linux/bitops.h>
34#include <linux/delay.h>
35#include <linux/libfdt.h>
36#include <linux/sizes.h>
37#include <linux/iopoll.h>
38#include <linux/iopoll.h>
39#include <linux/sizes.h>
40#include <linux/err.h>
41#include <asm/io.h>
42
43DECLARE_GLOBAL_DATA_PTR;
44
45
46
47
48
49
50#define SEQID_LUT 15
51#define SEQID_LUT_AHB 14
52
53
54#define QUADSPI_MCR 0x00
55#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
56#define QUADSPI_MCR_MDIS_MASK BIT(14)
57#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
58#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
59#define QUADSPI_MCR_DDR_EN_MASK BIT(7)
60#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
61#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
62#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
63
64#define QUADSPI_IPCR 0x08
65#define QUADSPI_IPCR_SEQID(x) ((x) << 24)
66#define QUADSPI_FLSHCR 0x0c
67#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
68#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
69#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
70
71#define QUADSPI_BUF3CR 0x1c
72#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
73#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
74#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
75
76#define QUADSPI_BFGENCR 0x20
77#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
78
79#define QUADSPI_BUF0IND 0x30
80#define QUADSPI_BUF1IND 0x34
81#define QUADSPI_BUF2IND 0x38
82#define QUADSPI_SFAR 0x100
83
84#define QUADSPI_SMPR 0x108
85#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
86#define QUADSPI_SMPR_FSDLY_MASK BIT(6)
87#define QUADSPI_SMPR_FSPHS_MASK BIT(5)
88#define QUADSPI_SMPR_HSENA_MASK BIT(0)
89
90#define QUADSPI_RBCT 0x110
91#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
92#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
93
94#define QUADSPI_TBDR 0x154
95
96#define QUADSPI_SR 0x15c
97#define QUADSPI_SR_IP_ACC_MASK BIT(1)
98#define QUADSPI_SR_AHB_ACC_MASK BIT(2)
99
100#define QUADSPI_FR 0x160
101#define QUADSPI_FR_TFF_MASK BIT(0)
102
103#define QUADSPI_RSER 0x164
104#define QUADSPI_RSER_TFIE BIT(0)
105
106#define QUADSPI_SPTRCLR 0x16c
107#define QUADSPI_SPTRCLR_IPPTRC BIT(8)
108#define QUADSPI_SPTRCLR_BFPTRC BIT(0)
109
110#define QUADSPI_SFA1AD 0x180
111#define QUADSPI_SFA2AD 0x184
112#define QUADSPI_SFB1AD 0x188
113#define QUADSPI_SFB2AD 0x18c
114#define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
115
116#define QUADSPI_LUTKEY 0x300
117#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
118
119#define QUADSPI_LCKCR 0x304
120#define QUADSPI_LCKER_LOCK BIT(0)
121#define QUADSPI_LCKER_UNLOCK BIT(1)
122
123#define QUADSPI_LUT_BASE 0x310
124#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
125#define QUADSPI_LUT_REG(idx) \
126 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
127
128#define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
129#define QUADSPI_AHB_LUT_REG(idx) \
130 (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
131
132
133#define LUT_STOP 0
134#define LUT_CMD 1
135#define LUT_ADDR 2
136#define LUT_DUMMY 3
137#define LUT_MODE 4
138#define LUT_MODE2 5
139#define LUT_MODE4 6
140#define LUT_FSL_READ 7
141#define LUT_FSL_WRITE 8
142#define LUT_JMP_ON_CS 9
143#define LUT_ADDR_DDR 10
144#define LUT_MODE_DDR 11
145#define LUT_MODE2_DDR 12
146#define LUT_MODE4_DDR 13
147#define LUT_FSL_READ_DDR 14
148#define LUT_FSL_WRITE_DDR 15
149#define LUT_DATA_LEARN 16
150
151
152
153
154
155
156
157
158#define LUT_PAD(x) (fls(x) - 1)
159
160
161
162
163
164
165
166
167
168#define LUT_DEF(idx, ins, pad, opr) \
169 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
170
171
172#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
173
174
175#define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
176
177
178
179
180
181
182#define QUADSPI_QUIRK_TKT253890 BIT(2)
183
184
185#define QUADSPI_QUIRK_TKT245618 BIT(3)
186
187
188
189
190
191#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
192
193
194
195
196
197#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
198
199
200
201
202#define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
203
204struct fsl_qspi_devtype_data {
205 unsigned int rxfifo;
206 unsigned int txfifo;
207 unsigned int ahb_buf_size;
208 unsigned int quirks;
209 bool little_endian;
210};
211
212static const struct fsl_qspi_devtype_data vybrid_data = {
213 .rxfifo = SZ_128,
214 .txfifo = SZ_64,
215 .ahb_buf_size = SZ_1K,
216 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
217 .little_endian = true,
218};
219
220static const struct fsl_qspi_devtype_data imx6sx_data = {
221 .rxfifo = SZ_128,
222 .txfifo = SZ_512,
223 .ahb_buf_size = SZ_1K,
224 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
225 .little_endian = true,
226};
227
228static const struct fsl_qspi_devtype_data imx7d_data = {
229 .rxfifo = SZ_128,
230 .txfifo = SZ_512,
231 .ahb_buf_size = SZ_1K,
232 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
233 QUADSPI_QUIRK_USE_TDH_SETTING,
234 .little_endian = true,
235};
236
237static const struct fsl_qspi_devtype_data imx6ul_data = {
238 .rxfifo = SZ_128,
239 .txfifo = SZ_512,
240 .ahb_buf_size = SZ_1K,
241 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
242 QUADSPI_QUIRK_USE_TDH_SETTING,
243 .little_endian = true,
244};
245
246static const struct fsl_qspi_devtype_data imx7ulp_data = {
247 .rxfifo = SZ_64,
248 .txfifo = SZ_64,
249 .ahb_buf_size = SZ_128,
250 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
251 QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
252 .little_endian = true,
253};
254
255static const struct fsl_qspi_devtype_data ls1021a_data = {
256 .rxfifo = SZ_128,
257 .txfifo = SZ_64,
258 .ahb_buf_size = SZ_1K,
259 .quirks = 0,
260 .little_endian = false,
261};
262
263static const struct fsl_qspi_devtype_data ls2080a_data = {
264 .rxfifo = SZ_128,
265 .txfifo = SZ_64,
266 .ahb_buf_size = SZ_1K,
267 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
268 .little_endian = true,
269};
270
271struct fsl_qspi {
272 struct udevice *dev;
273 void __iomem *iobase;
274 void __iomem *ahb_addr;
275 u32 memmap_phy;
276 u32 memmap_size;
277 const struct fsl_qspi_devtype_data *devtype_data;
278 int selected;
279};
280
281static inline int needs_swap_endian(struct fsl_qspi *q)
282{
283 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
284}
285
286static inline int needs_4x_clock(struct fsl_qspi *q)
287{
288 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
289}
290
291static inline int needs_fill_txfifo(struct fsl_qspi *q)
292{
293 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
294}
295
296static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
297{
298 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
299}
300
301static inline int needs_amba_base_offset(struct fsl_qspi *q)
302{
303 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
304}
305
306static inline int needs_tdh_setting(struct fsl_qspi *q)
307{
308 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
309}
310
311static inline int needs_single_bus(struct fsl_qspi *q)
312{
313 return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
314}
315
316
317
318
319
320static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
321{
322 return needs_swap_endian(q) ? __swab32(a) : a;
323}
324
325
326
327
328
329
330
331
332static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
333{
334 if (q->devtype_data->little_endian)
335 out_le32(addr, val);
336 else
337 out_be32(addr, val);
338}
339
340static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
341{
342 if (q->devtype_data->little_endian)
343 return in_le32(addr);
344
345 return in_be32(addr);
346}
347
348static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
349{
350 switch (width) {
351 case 1:
352 case 2:
353 case 4:
354 return 0;
355 }
356
357 return -ENOTSUPP;
358}
359
360static bool fsl_qspi_supports_op(struct spi_slave *slave,
361 const struct spi_mem_op *op)
362{
363 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
364 int ret;
365
366 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
367
368 if (op->addr.nbytes)
369 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
370
371 if (op->dummy.nbytes)
372 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
373
374 if (op->data.nbytes)
375 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
376
377 if (ret)
378 return false;
379
380
381
382
383
384 if (op->addr.nbytes +
385 (op->dummy.nbytes ? 1 : 0) +
386 (op->data.nbytes ? 1 : 0) > 6)
387 return false;
388
389
390 if (op->dummy.nbytes &&
391 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
392 return false;
393
394
395 if (op->data.dir == SPI_MEM_DATA_IN &&
396 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
397 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
398 !IS_ALIGNED(op->data.nbytes, 8))))
399 return false;
400
401 if (op->data.dir == SPI_MEM_DATA_OUT &&
402 op->data.nbytes > q->devtype_data->txfifo)
403 return false;
404
405 return spi_mem_default_supports_op(slave, op);
406}
407
408static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
409 const struct spi_mem_op *op)
410{
411 void __iomem *base = q->iobase;
412 u32 lutval[4] = {};
413 int lutidx = 1, i;
414
415 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
416 op->cmd.opcode);
417
418 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
419 if (op->addr.nbytes) {
420 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
421 LUT_PAD(op->addr.buswidth),
422 (op->addr.nbytes == 4) ? 0x20 : 0x18);
423 lutidx++;
424 }
425 } else {
426
427
428
429
430
431 for (i = 0; i < op->addr.nbytes; i++) {
432 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
433
434 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
435 LUT_PAD(op->addr.buswidth),
436 addrbyte);
437 lutidx++;
438 }
439 }
440
441 if (op->dummy.nbytes) {
442 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
443 LUT_PAD(op->dummy.buswidth),
444 op->dummy.nbytes * 8 /
445 op->dummy.buswidth);
446 lutidx++;
447 }
448
449 if (op->data.nbytes) {
450 lutval[lutidx / 2] |= LUT_DEF(lutidx,
451 op->data.dir == SPI_MEM_DATA_IN ?
452 LUT_FSL_READ : LUT_FSL_WRITE,
453 LUT_PAD(op->data.buswidth),
454 0);
455 lutidx++;
456 }
457
458 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
459
460
461 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
462 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
463
464 dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
465 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
466
467
468 for (i = 0; i < ARRAY_SIZE(lutval); i++)
469 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
470
471 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
472 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
473 op->addr.nbytes) {
474 for (i = 0; i < ARRAY_SIZE(lutval); i++)
475 qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
476 }
477 }
478
479
480 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
481 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
482}
483
484
485
486
487
488
489
490
491static void fsl_qspi_invalidate(struct fsl_qspi *q)
492{
493 u32 reg;
494
495 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
496 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
497 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
498
499
500
501
502
503 udelay(1);
504
505 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
506 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
507}
508
509static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
510{
511 struct dm_spi_slave_plat *plat =
512 dev_get_parent_plat(slave->dev);
513
514 if (q->selected == plat->cs)
515 return;
516
517 q->selected = plat->cs;
518 fsl_qspi_invalidate(q);
519}
520
521static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
522{
523 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
524 if (needs_single_bus(q))
525 return q->memmap_size / 2;
526 else
527 return q->memmap_size / 4;
528 } else {
529 return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
530 }
531}
532
533static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
534{
535 void __iomem *ahb_read_addr = q->ahb_addr;
536
537 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
538 if (op->addr.nbytes)
539 ahb_read_addr += op->addr.val;
540 }
541
542 memcpy_fromio(op->data.buf.in,
543 ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
544 op->data.nbytes);
545}
546
547static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
548 const struct spi_mem_op *op)
549{
550 void __iomem *base = q->iobase;
551 int i;
552 u32 val;
553
554 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
555 memcpy(&val, op->data.buf.out + i, 4);
556 val = fsl_qspi_endian_xchg(q, val);
557 qspi_writel(q, val, base + QUADSPI_TBDR);
558 }
559
560 if (i < op->data.nbytes) {
561 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
562 val = fsl_qspi_endian_xchg(q, val);
563 qspi_writel(q, val, base + QUADSPI_TBDR);
564 }
565
566 if (needs_fill_txfifo(q)) {
567 for (i = op->data.nbytes; i < 16; i += 4)
568 qspi_writel(q, 0, base + QUADSPI_TBDR);
569 }
570}
571
572static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
573 const struct spi_mem_op *op)
574{
575 void __iomem *base = q->iobase;
576 int i;
577 u8 *buf = op->data.buf.in;
578 u32 val;
579
580 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
581 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
582 val = fsl_qspi_endian_xchg(q, val);
583 memcpy(buf + i, &val, 4);
584 }
585
586 if (i < op->data.nbytes) {
587 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
588 val = fsl_qspi_endian_xchg(q, val);
589 memcpy(buf + i, &val, op->data.nbytes - i);
590 }
591}
592
593static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
594 u32 mask, u32 delay_us, u32 timeout_us)
595{
596 u32 reg;
597
598 if (!q->devtype_data->little_endian)
599 mask = (u32)cpu_to_be32(mask);
600
601 return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
602}
603
604static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
605{
606 void __iomem *base = q->iobase;
607 int err = 0;
608
609
610
611
612
613
614 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
615 base + QUADSPI_IPCR);
616
617
618 err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
619 (QUADSPI_SR_IP_ACC_MASK |
620 QUADSPI_SR_AHB_ACC_MASK),
621 10, 1000);
622
623 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
624 fsl_qspi_read_rxfifo(q, op);
625
626 return err;
627}
628
629static int fsl_qspi_exec_op(struct spi_slave *slave,
630 const struct spi_mem_op *op)
631{
632 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
633 void __iomem *base = q->iobase;
634 u32 addr_offset = 0;
635 int err = 0;
636
637
638 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
639 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
640
641 fsl_qspi_select_mem(q, slave);
642
643 if (needs_amba_base_offset(q))
644 addr_offset = q->memmap_phy;
645
646 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
647 if (op->addr.nbytes)
648 addr_offset += op->addr.val;
649 }
650
651 qspi_writel(q,
652 q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
653 base + QUADSPI_SFAR);
654
655 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
656 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
657 base + QUADSPI_MCR);
658
659 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
660 base + QUADSPI_SPTRCLR);
661
662 fsl_qspi_prepare_lut(q, op);
663
664
665
666
667
668
669 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
670 op->data.dir == SPI_MEM_DATA_IN) {
671 fsl_qspi_read_ahb(q, op);
672 } else {
673 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
674 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
675
676 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
677 fsl_qspi_fill_txfifo(q, op);
678
679 err = fsl_qspi_do_op(q, op);
680 }
681
682
683 fsl_qspi_invalidate(q);
684
685 return err;
686}
687
688static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
689 struct spi_mem_op *op)
690{
691 struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
692
693 if (op->data.dir == SPI_MEM_DATA_OUT) {
694 if (op->data.nbytes > q->devtype_data->txfifo)
695 op->data.nbytes = q->devtype_data->txfifo;
696 } else {
697 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
698 op->data.nbytes = q->devtype_data->ahb_buf_size;
699 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
700 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
701 }
702
703 return 0;
704}
705
706static int fsl_qspi_default_setup(struct fsl_qspi *q)
707{
708 void __iomem *base = q->iobase;
709 u32 reg, addr_offset = 0, memsize_cs;
710
711
712 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
713 base + QUADSPI_MCR);
714 udelay(1);
715
716
717 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
718 base + QUADSPI_MCR);
719
720
721
722
723
724
725 if (needs_tdh_setting(q))
726 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
727 ~QUADSPI_FLSHCR_TDH_MASK,
728 base + QUADSPI_FLSHCR);
729
730 reg = qspi_readl(q, base + QUADSPI_SMPR);
731 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
732 | QUADSPI_SMPR_FSPHS_MASK
733 | QUADSPI_SMPR_HSENA_MASK
734 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
735
736
737 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
738 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
739 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
740
741 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
742 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
743 q->iobase + QUADSPI_BFGENCR);
744 else
745 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
746 q->iobase + QUADSPI_BFGENCR);
747
748 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
749 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
750 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
751 base + QUADSPI_BUF3CR);
752
753 if (needs_amba_base_offset(q))
754 addr_offset = q->memmap_phy;
755
756
757
758
759
760
761
762
763 memsize_cs = fsl_qspi_memsize_per_cs(q);
764 qspi_writel(q, memsize_cs + addr_offset,
765 base + QUADSPI_SFA1AD);
766 qspi_writel(q, memsize_cs * 2 + addr_offset,
767 base + QUADSPI_SFA2AD);
768 if (!needs_single_bus(q)) {
769 qspi_writel(q, memsize_cs * 3 + addr_offset,
770 base + QUADSPI_SFB1AD);
771 qspi_writel(q, memsize_cs * 4 + addr_offset,
772 base + QUADSPI_SFB2AD);
773 }
774
775 q->selected = -1;
776
777
778 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
779 base + QUADSPI_MCR);
780 return 0;
781}
782
783static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
784 .adjust_op_size = fsl_qspi_adjust_op_size,
785 .supports_op = fsl_qspi_supports_op,
786 .exec_op = fsl_qspi_exec_op,
787};
788
789static int fsl_qspi_probe(struct udevice *bus)
790{
791 struct dm_spi_bus *dm_bus = dev_get_uclass_priv(bus);
792 struct fsl_qspi *q = dev_get_priv(bus);
793 const void *blob = gd->fdt_blob;
794 int node = dev_of_offset(bus);
795 struct fdt_resource res;
796 int ret;
797
798 q->dev = bus;
799 q->devtype_data = (struct fsl_qspi_devtype_data *)
800 dev_get_driver_data(bus);
801
802
803 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
804 &res);
805 if (ret) {
806 dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
807 return -ENOMEM;
808 }
809
810 q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
811
812 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
813 "QuadSPI-memory", &res);
814 if (ret) {
815 dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
816 return -ENOMEM;
817 }
818
819 q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
820 q->memmap_phy = res.start;
821 q->memmap_size = res.end - res.start;
822
823 dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
824 66000000);
825
826 fsl_qspi_default_setup(q);
827
828 return 0;
829}
830
831static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
832 const void *dout, void *din, unsigned long flags)
833{
834 return 0;
835}
836
837static int fsl_qspi_claim_bus(struct udevice *dev)
838{
839 return 0;
840}
841
842static int fsl_qspi_release_bus(struct udevice *dev)
843{
844 return 0;
845}
846
847static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
848{
849 return 0;
850}
851
852static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
853{
854 return 0;
855}
856
857static const struct dm_spi_ops fsl_qspi_ops = {
858 .claim_bus = fsl_qspi_claim_bus,
859 .release_bus = fsl_qspi_release_bus,
860 .xfer = fsl_qspi_xfer,
861 .set_speed = fsl_qspi_set_speed,
862 .set_mode = fsl_qspi_set_mode,
863 .mem_ops = &fsl_qspi_mem_ops,
864};
865
866static const struct udevice_id fsl_qspi_ids[] = {
867 { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
868 { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
869 { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
870 { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
871 { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
872 { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
873 { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, },
874 { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
875 { }
876};
877
878U_BOOT_DRIVER(fsl_qspi) = {
879 .name = "fsl_qspi",
880 .id = UCLASS_SPI,
881 .of_match = fsl_qspi_ids,
882 .ops = &fsl_qspi_ops,
883 .priv_auto = sizeof(struct fsl_qspi),
884 .probe = fsl_qspi_probe,
885};
886