LXR uboot/drivers/spi/mvebu_a3700

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015 Marvell International Ltd.
   4 *
   5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <log.h>
  11#include <malloc.h>
  12#include <spi.h>
  13#include <clk.h>
  14#include <wait_bit.h>
  15#include <asm/global_data.h>
  16#include <asm/io.h>
  17#include <dm/device_compat.h>
  18#include <linux/bitops.h>
  19#include <asm/gpio.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23#define MVEBU_SPI_A3700_XFER_RDY                BIT(1)
  24#define MVEBU_SPI_A3700_FIFO_FLUSH              BIT(9)
  25#define MVEBU_SPI_A3700_BYTE_LEN                BIT(5)
  26#define MVEBU_SPI_A3700_CLK_PHA                 BIT(6)
  27#define MVEBU_SPI_A3700_CLK_POL                 BIT(7)
  28#define MVEBU_SPI_A3700_FIFO_EN                 BIT(17)
  29#define MVEBU_SPI_A3700_SPI_EN_0                BIT(16)
  30#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK       0x1f
  31
  32#define MAX_CS_COUNT    4
  33
  34/* SPI registers */
  35struct spi_reg {
  36        u32 ctrl;       /* 0x10600 */
  37        u32 cfg;        /* 0x10604 */
  38        u32 dout;       /* 0x10608 */
  39        u32 din;        /* 0x1060c */
  40};
  41
  42struct mvebu_spi_plat {
  43        struct spi_reg *spireg;
  44        struct clk clk;
  45        struct gpio_desc cs_gpios[MAX_CS_COUNT];
  46};
  47
  48static void spi_cs_activate(struct mvebu_spi_plat *plat, int cs)
  49{
  50        if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  51                dm_gpio_set_value(&plat->cs_gpios[cs], 1);
  52        else
  53                setbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  54}
  55
  56static void spi_cs_deactivate(struct mvebu_spi_plat *plat, int cs)
  57{
  58        if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  59                dm_gpio_set_value(&plat->cs_gpios[cs], 0);
  60        else
  61                clrbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  62}
  63
  64/**
  65 * spi_legacy_shift_byte() - triggers the real SPI transfer
  66 * @bytelen:    Indicate how many bytes to transfer.
  67 * @dout:       Buffer address of what to send.
  68 * @din:        Buffer address of where to receive.
  69 *
  70 * This function triggers the real SPI transfer in legacy mode. It
  71 * will shift out char buffer from @dout, and shift in char buffer to
  72 * @din, if necessary.
  73 *
  74 * This function assumes that only one byte is shifted at one time.
  75 * However, it is not its responisbility to set the transfer type to
  76 * one-byte. Also, it does not guarantee that it will work if transfer
  77 * type becomes two-byte. See spi_set_legacy() for details.
  78 *
  79 * In legacy mode, simply write to the SPI_DOUT register will trigger
  80 * the transfer.
  81 *
  82 * If @dout == NULL, which means no actual data needs to be sent out,
  83 * then the function will shift out 0x00 in order to shift in data.
  84 * The XFER_RDY flag is checked every time before accessing SPI_DOUT
  85 * and SPI_DIN register.
  86 *
  87 * The number of transfers to be triggerred is decided by @bytelen.
  88 *
  89 * Return:      0 - cool
  90 *              -ETIMEDOUT - XFER_RDY flag timeout
  91 */
  92static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
  93                                 const void *dout, void *din)
  94{
  95        const u8 *dout_8;
  96        u8 *din_8;
  97        int ret;
  98
  99        /* Use 0x00 as dummy dout */
 100        const u8 dummy_dout = 0x0;
 101        u32 pending_dout = 0x0;
 102
 103        /* dout_8: pointer of current dout */
 104        dout_8 = dout;
 105        /* din_8: pointer of current din */
 106        din_8 = din;
 107
 108        while (bytelen) {
 109                ret = wait_for_bit_le32(&reg->ctrl,
 110                                        MVEBU_SPI_A3700_XFER_RDY,
 111                                        true,100, false);
 112                if (ret)
 113                        return ret;
 114
 115                if (dout)
 116                        pending_dout = (u32)*dout_8;
 117                else
 118                        pending_dout = (u32)dummy_dout;
 119
 120                /* Trigger the xfer */
 121                writel(pending_dout, &reg->dout);
 122
 123                if (din) {
 124                        ret = wait_for_bit_le32(&reg->ctrl,
 125                                                MVEBU_SPI_A3700_XFER_RDY,
 126                                                true, 100, false);
 127                        if (ret)
 128                                return ret;
 129
 130                        /* Read what is transferred in */
 131                        *din_8 = (u8)readl(&reg->din);
 132                }
 133
 134                /* Don't increment the current pointer if NULL */
 135                if (dout)
 136                        dout_8++;
 137                if (din)
 138                        din_8++;
 139
 140                bytelen--;
 141        }
 142
 143        return 0;
 144}
 145
 146static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
 147                          const void *dout, void *din, unsigned long flags)
 148{
 149        struct udevice *bus = dev->parent;
 150        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 151        struct spi_reg *reg = plat->spireg;
 152        unsigned int bytelen;
 153        int ret;
 154
 155        bytelen = bitlen / 8;
 156
 157        if (dout && din)
 158                debug("This is a duplex transfer.\n");
 159
 160        /* Activate CS */
 161        if (flags & SPI_XFER_BEGIN) {
 162                debug("SPI: activate cs.\n");
 163                spi_cs_activate(plat, spi_chip_select(dev));
 164        }
 165
 166        /* Send and/or receive */
 167        if (dout || din) {
 168                ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
 169                if (ret)
 170                        return ret;
 171        }
 172
 173        /* Deactivate CS */
 174        if (flags & SPI_XFER_END) {
 175                ret = wait_for_bit_le32(&reg->ctrl,
 176                                        MVEBU_SPI_A3700_XFER_RDY,
 177                                        true, 100, false);
 178                if (ret)
 179                        return ret;
 180
 181                debug("SPI: deactivate cs.\n");
 182                spi_cs_deactivate(plat, spi_chip_select(dev));
 183        }
 184
 185        return 0;
 186}
 187
 188static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
 189{
 190        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 191        struct spi_reg *reg = plat->spireg;
 192        u32 data, prescale;
 193
 194        data = readl(&reg->cfg);
 195
 196        prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
 197        if (prescale > 0xf)
 198                prescale = 0x10 + (prescale + 1) / 2;
 199        prescale = min(prescale, 0x1fu);
 200
 201        data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
 202        data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
 203
 204        writel(data, &reg->cfg);
 205
 206        return 0;
 207}
 208
 209static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
 210{
 211        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 212        struct spi_reg *reg = plat->spireg;
 213
 214        /*
 215         * Set SPI polarity
 216         * 0: Serial interface clock is low when inactive
 217         * 1: Serial interface clock is high when inactive
 218         */
 219        if (mode & SPI_CPOL)
 220                setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
 221        else
 222                clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
 223        if (mode & SPI_CPHA)
 224                setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
 225        else
 226                clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
 227
 228        return 0;
 229}
 230
 231static int mvebu_spi_probe(struct udevice *bus)
 232{
 233        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 234        struct spi_reg *reg = plat->spireg;
 235        u32 data;
 236        int ret;
 237
 238        /*
 239         * Settings SPI controller to be working in legacy mode, which
 240         * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
 241         * for Data In.
 242         */
 243
 244        /* Flush read/write FIFO */
 245        data = readl(&reg->cfg);
 246        writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);
 247        ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
 248                                false, 1000, false);
 249        if (ret)
 250                return ret;
 251
 252        /* Disable FIFO mode */
 253        data &= ~MVEBU_SPI_A3700_FIFO_EN;
 254
 255        /* Always shift 1 byte at a time */
 256        data &= ~MVEBU_SPI_A3700_BYTE_LEN;
 257
 258        writel(data, &reg->cfg);
 259
 260        /* Set up CS GPIOs in device tree, if any */
 261        if (CONFIG_IS_ENABLED(DM_GPIO) && gpio_get_list_count(bus, "cs-gpios") > 0) {
 262                int i;
 263
 264                for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
 265                        ret = gpio_request_by_name(bus, "cs-gpios", i, &plat->cs_gpios[i], 0);
 266                        if (ret < 0 || !dm_gpio_is_valid(&plat->cs_gpios[i])) {
 267                                /* Use the native CS function for this line */
 268                                continue;
 269                        }
 270
 271                        ret = dm_gpio_set_dir_flags(&plat->cs_gpios[i],
 272                                                    GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
 273                        if (ret) {
 274                                dev_err(bus, "Setting cs %d error\n", i);
 275                                return ret;
 276                        }
 277                }
 278        }
 279
 280        return 0;
 281}
 282
 283static int mvebu_spi_of_to_plat(struct udevice *bus)
 284{
 285        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 286        int ret;
 287
 288        plat->spireg = dev_read_addr_ptr(bus);
 289
 290        ret = clk_get_by_index(bus, 0, &plat->clk);
 291        if (ret) {
 292                dev_err(bus, "cannot get clock\n");
 293                return ret;
 294        }
 295
 296        return 0;
 297}
 298
 299static int mvebu_spi_remove(struct udevice *bus)
 300{
 301        struct mvebu_spi_plat *plat = dev_get_plat(bus);
 302
 303        clk_free(&plat->clk);
 304
 305        return 0;
 306}
 307
 308static const struct dm_spi_ops mvebu_spi_ops = {
 309        .xfer           = mvebu_spi_xfer,
 310        .set_speed      = mvebu_spi_set_speed,
 311        .set_mode       = mvebu_spi_set_mode,
 312        /*
 313         * cs_info is not needed, since we require all chip selects to be
 314         * in the device tree explicitly
 315         */
 316};
 317
 318static const struct udevice_id mvebu_spi_ids[] = {
 319        { .compatible = "marvell,armada-3700-spi" },
 320        { }
 321};
 322
 323U_BOOT_DRIVER(mvebu_spi) = {
 324        .name = "mvebu_spi",
 325        .id = UCLASS_SPI,
 326        .of_match = mvebu_spi_ids,
 327        .ops = &mvebu_spi_ops,
 328        .of_to_plat = mvebu_spi_of_to_plat,
 329        .plat_auto      = sizeof(struct mvebu_spi_plat),
 330        .probe = mvebu_spi_probe,
 331        .remove = mvebu_spi_remove,
 332};
 333