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9#include <common.h>
10#include <clk.h>
11#include <dm.h>
12#include <errno.h>
13#include <asm/io.h>
14#include <malloc.h>
15#include <spi.h>
16#include <spi-mem.h>
17#include <linux/bug.h>
18#include <linux/iopoll.h>
19
20#define HC_CFG 0x0
21#define HC_CFG_IF_CFG(x) ((x) << 27)
22#define HC_CFG_DUAL_SLAVE BIT(31)
23#define HC_CFG_INDIVIDUAL BIT(30)
24#define HC_CFG_NIO(x) (((x) / 4) << 27)
25#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
26#define HC_CFG_TYPE_SPI_NOR 0
27#define HC_CFG_TYPE_SPI_NAND 1
28#define HC_CFG_TYPE_SPI_RAM 2
29#define HC_CFG_TYPE_RAW_NAND 3
30#define HC_CFG_SLV_ACT(x) ((x) << 21)
31#define HC_CFG_CLK_PH_EN BIT(20)
32#define HC_CFG_CLK_POL_INV BIT(19)
33#define HC_CFG_BIG_ENDIAN BIT(18)
34#define HC_CFG_DATA_PASS BIT(17)
35#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
36#define HC_CFG_MAN_START_EN BIT(3)
37#define HC_CFG_MAN_START BIT(2)
38#define HC_CFG_MAN_CS_EN BIT(1)
39#define HC_CFG_MAN_CS_ASSERT BIT(0)
40
41#define INT_STS 0x4
42#define INT_STS_EN 0x8
43#define INT_SIG_EN 0xc
44#define INT_STS_ALL GENMASK(31, 0)
45#define INT_RDY_PIN BIT(26)
46#define INT_RDY_SR BIT(25)
47#define INT_LNR_SUSP BIT(24)
48#define INT_ECC_ERR BIT(17)
49#define INT_CRC_ERR BIT(16)
50#define INT_LWR_DIS BIT(12)
51#define INT_LRD_DIS BIT(11)
52#define INT_SDMA_INT BIT(10)
53#define INT_DMA_FINISH BIT(9)
54#define INT_RX_NOT_FULL BIT(3)
55#define INT_RX_NOT_EMPTY BIT(2)
56#define INT_TX_NOT_FULL BIT(1)
57#define INT_TX_EMPTY BIT(0)
58
59#define HC_EN 0x10
60#define HC_EN_BIT BIT(0)
61
62#define TXD(x) (0x14 + ((x) * 4))
63#define RXD 0x24
64
65#define SS_CTRL(s) (0x30 + ((s) * 4))
66#define LRD_CFG 0x44
67#define LWR_CFG 0x80
68#define RWW_CFG 0x70
69#define OP_READ BIT(23)
70#define OP_DUMMY_CYC(x) ((x) << 17)
71#define OP_ADDR_BYTES(x) ((x) << 14)
72#define OP_CMD_BYTES(x) (((x) - 1) << 13)
73#define OP_OCTA_CRC_EN BIT(12)
74#define OP_DQS_EN BIT(11)
75#define OP_ENHC_EN BIT(10)
76#define OP_PREAMBLE_EN BIT(9)
77#define OP_DATA_DDR BIT(8)
78#define OP_DATA_BUSW(x) ((x) << 6)
79#define OP_ADDR_DDR BIT(5)
80#define OP_ADDR_BUSW(x) ((x) << 3)
81#define OP_CMD_DDR BIT(2)
82#define OP_CMD_BUSW(x) (x)
83#define OP_BUSW_1 0
84#define OP_BUSW_2 1
85#define OP_BUSW_4 2
86#define OP_BUSW_8 3
87
88#define OCTA_CRC 0x38
89#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
90#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
91#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
92
93#define ONFI_DIN_CNT(s) (0x3c + (s))
94
95#define LRD_CTRL 0x48
96#define RWW_CTRL 0x74
97#define LWR_CTRL 0x84
98#define LMODE_EN BIT(31)
99#define LMODE_SLV_ACT(x) ((x) << 21)
100#define LMODE_CMD1(x) ((x) << 8)
101#define LMODE_CMD0(x) (x)
102
103#define LRD_ADDR 0x4c
104#define LWR_ADDR 0x88
105#define LRD_RANGE 0x50
106#define LWR_RANGE 0x8c
107
108#define AXI_SLV_ADDR 0x54
109
110#define DMAC_RD_CFG 0x58
111#define DMAC_WR_CFG 0x94
112#define DMAC_CFG_PERIPH_EN BIT(31)
113#define DMAC_CFG_ALLFLUSH_EN BIT(30)
114#define DMAC_CFG_LASTFLUSH_EN BIT(29)
115#define DMAC_CFG_QE(x) (((x) + 1) << 16)
116#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
117#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
118#define DMAC_CFG_DIR_READ BIT(1)
119#define DMAC_CFG_START BIT(0)
120
121#define DMAC_RD_CNT 0x5c
122#define DMAC_WR_CNT 0x98
123
124#define SDMA_ADDR 0x60
125
126#define DMAM_CFG 0x64
127#define DMAM_CFG_START BIT(31)
128#define DMAM_CFG_CONT BIT(30)
129#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
130#define DMAM_CFG_DIR_READ BIT(1)
131#define DMAM_CFG_EN BIT(0)
132
133#define DMAM_CNT 0x68
134
135#define LNR_TIMER_TH 0x6c
136
137#define RDM_CFG0 0x78
138#define RDM_CFG0_POLY(x) (x)
139
140#define RDM_CFG1 0x7c
141#define RDM_CFG1_RDM_EN BIT(31)
142#define RDM_CFG1_SEED(x) (x)
143
144#define LWR_SUSP_CTRL 0x90
145#define LWR_SUSP_CTRL_EN BIT(31)
146
147#define DMAS_CTRL 0x9c
148#define DMAS_CTRL_EN BIT(31)
149#define DMAS_CTRL_DIR_READ BIT(30)
150
151#define DATA_STROB 0xa0
152#define DATA_STROB_EDO_EN BIT(2)
153#define DATA_STROB_INV_POL BIT(1)
154#define DATA_STROB_DELAY_2CYC BIT(0)
155
156#define IDLY_CODE(x) (0xa4 + ((x) * 4))
157#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
158
159#define GPIO 0xc4
160#define GPIO_PT(x) BIT(3 + ((x) * 16))
161#define GPIO_RESET(x) BIT(2 + ((x) * 16))
162#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
163#define GPIO_WPB(x) BIT((x) * 16)
164
165#define HC_VER 0xd0
166
167#define HW_TEST(x) (0xe0 + ((x) * 4))
168
169struct mxic_spi_priv {
170 struct clk *send_clk;
171 struct clk *send_dly_clk;
172 void __iomem *regs;
173 u32 cur_speed_hz;
174};
175
176static int mxic_spi_clk_enable(struct mxic_spi_priv *priv)
177{
178 int ret;
179
180 ret = clk_prepare_enable(priv->send_clk);
181 if (ret)
182 return ret;
183
184 ret = clk_prepare_enable(priv->send_dly_clk);
185 if (ret)
186 goto err_send_dly_clk;
187
188 return ret;
189
190err_send_dly_clk:
191 clk_disable_unprepare(priv->send_clk);
192
193 return ret;
194}
195
196static void mxic_spi_clk_disable(struct mxic_spi_priv *priv)
197{
198 clk_disable_unprepare(priv->send_clk);
199 clk_disable_unprepare(priv->send_dly_clk);
200}
201
202static void mxic_spi_set_input_delay_dqs(struct mxic_spi_priv *priv,
203 u8 idly_code)
204{
205 writel(IDLY_CODE_VAL(0, idly_code) |
206 IDLY_CODE_VAL(1, idly_code) |
207 IDLY_CODE_VAL(2, idly_code) |
208 IDLY_CODE_VAL(3, idly_code),
209 priv->regs + IDLY_CODE(0));
210 writel(IDLY_CODE_VAL(4, idly_code) |
211 IDLY_CODE_VAL(5, idly_code) |
212 IDLY_CODE_VAL(6, idly_code) |
213 IDLY_CODE_VAL(7, idly_code),
214 priv->regs + IDLY_CODE(1));
215}
216
217static int mxic_spi_clk_setup(struct mxic_spi_priv *priv, uint freq)
218{
219 int ret;
220
221 ret = clk_set_rate(priv->send_clk, freq);
222 if (ret)
223 return ret;
224
225 ret = clk_set_rate(priv->send_dly_clk, freq);
226 if (ret)
227 return ret;
228
229
230
231
232
233 mxic_spi_set_input_delay_dqs(priv, 0xf);
234
235 return 0;
236}
237
238static int mxic_spi_set_speed(struct udevice *bus, uint freq)
239{
240 struct mxic_spi_priv *priv = dev_get_priv(bus);
241 int ret;
242
243 if (priv->cur_speed_hz == freq)
244 return 0;
245
246 mxic_spi_clk_disable(priv);
247 ret = mxic_spi_clk_setup(priv, freq);
248 if (ret)
249 return ret;
250
251 ret = mxic_spi_clk_enable(priv);
252 if (ret)
253 return ret;
254
255 priv->cur_speed_hz = freq;
256
257 return 0;
258}
259
260static int mxic_spi_set_mode(struct udevice *bus, uint mode)
261{
262 struct mxic_spi_priv *priv = dev_get_priv(bus);
263 u32 hc_config = 0;
264
265 if (mode & SPI_CPHA)
266 hc_config |= HC_CFG_CLK_PH_EN;
267 if (mode & SPI_CPOL)
268 hc_config |= HC_CFG_CLK_POL_INV;
269
270 writel(hc_config, priv->regs + HC_CFG);
271
272 return 0;
273}
274
275static void mxic_spi_hw_init(struct mxic_spi_priv *priv)
276{
277 writel(0, priv->regs + DATA_STROB);
278 writel(INT_STS_ALL, priv->regs + INT_STS_EN);
279 writel(0, priv->regs + HC_EN);
280 writel(0, priv->regs + LRD_CFG);
281 writel(0, priv->regs + LRD_CTRL);
282 writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
283 HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
284 priv->regs + HC_CFG);
285}
286
287static int mxic_spi_data_xfer(struct mxic_spi_priv *priv, const void *txbuf,
288 void *rxbuf, unsigned int len)
289{
290 unsigned int pos = 0;
291
292 while (pos < len) {
293 unsigned int nbytes = len - pos;
294 u32 data = 0xffffffff;
295 u32 sts;
296 int ret;
297
298 if (nbytes > 4)
299 nbytes = 4;
300
301 if (txbuf)
302 memcpy(&data, txbuf + pos, nbytes);
303
304 ret = readl_poll_timeout(priv->regs + INT_STS, sts,
305 sts & INT_TX_EMPTY, 1000000);
306 if (ret)
307 return ret;
308
309 writel(data, priv->regs + TXD(nbytes % 4));
310
311 if (rxbuf) {
312 ret = readl_poll_timeout(priv->regs + INT_STS, sts,
313 sts & INT_TX_EMPTY,
314 1000000);
315 if (ret)
316 return ret;
317
318 ret = readl_poll_timeout(priv->regs + INT_STS, sts,
319 sts & INT_RX_NOT_EMPTY,
320 1000000);
321 if (ret)
322 return ret;
323
324 data = readl(priv->regs + RXD);
325 data >>= (8 * (4 - nbytes));
326 memcpy(rxbuf + pos, &data, nbytes);
327 WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
328 } else {
329 readl(priv->regs + RXD);
330 }
331 WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
332
333 pos += nbytes;
334 }
335
336 return 0;
337}
338
339static bool mxic_spi_mem_supports_op(struct spi_slave *slave,
340 const struct spi_mem_op *op)
341{
342 if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
343 op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
344 return false;
345
346 if (op->addr.nbytes > 7)
347 return false;
348
349 return spi_mem_default_supports_op(slave, op);
350}
351
352static int mxic_spi_mem_exec_op(struct spi_slave *slave,
353 const struct spi_mem_op *op)
354{
355 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
356 struct udevice *bus = slave->dev->parent;
357 struct mxic_spi_priv *priv = dev_get_priv(bus);
358 int nio = 1, i, ret;
359 u32 ss_ctrl;
360 u8 addr[8], dummy_bytes = 0;
361
362 if (slave->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
363 nio = 8;
364 else if (slave->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
365 nio = 4;
366 else if (slave->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
367 nio = 2;
368
369 writel(HC_CFG_NIO(nio) |
370 HC_CFG_TYPE(slave_plat->cs, HC_CFG_TYPE_SPI_NOR) |
371 HC_CFG_SLV_ACT(slave_plat->cs) | HC_CFG_IDLE_SIO_LVL(1) |
372 HC_CFG_MAN_CS_EN,
373 priv->regs + HC_CFG);
374 writel(HC_EN_BIT, priv->regs + HC_EN);
375
376 ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
377
378 if (op->addr.nbytes)
379 ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
380 OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
381
382
383
384
385
386
387 if (op->dummy.nbytes) {
388 dummy_bytes = op->dummy.nbytes /
389 op->addr.buswidth *
390 op->data.buswidth;
391 ss_ctrl |= OP_DUMMY_CYC(dummy_bytes);
392 }
393
394 if (op->data.nbytes) {
395 ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
396 if (op->data.dir == SPI_MEM_DATA_IN)
397 ss_ctrl |= OP_READ;
398 }
399
400 writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs));
401
402 writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
403 priv->regs + HC_CFG);
404
405 ret = mxic_spi_data_xfer(priv, &op->cmd.opcode, NULL, 1);
406 if (ret)
407 goto out;
408
409 for (i = 0; i < op->addr.nbytes; i++)
410 addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
411
412 ret = mxic_spi_data_xfer(priv, addr, NULL, op->addr.nbytes);
413 if (ret)
414 goto out;
415
416 ret = mxic_spi_data_xfer(priv, NULL, NULL, dummy_bytes);
417 if (ret)
418 goto out;
419
420 ret = mxic_spi_data_xfer(priv,
421 op->data.dir == SPI_MEM_DATA_OUT ?
422 op->data.buf.out : NULL,
423 op->data.dir == SPI_MEM_DATA_IN ?
424 op->data.buf.in : NULL,
425 op->data.nbytes);
426
427out:
428 writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
429 priv->regs + HC_CFG);
430 writel(0, priv->regs + HC_EN);
431
432 return ret;
433}
434
435static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
436 .supports_op = mxic_spi_mem_supports_op,
437 .exec_op = mxic_spi_mem_exec_op,
438};
439
440static int mxic_spi_claim_bus(struct udevice *dev)
441{
442 struct udevice *bus = dev_get_parent(dev);
443 struct mxic_spi_priv *priv = dev_get_priv(bus);
444
445 writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
446 priv->regs + HC_CFG);
447 writel(HC_EN_BIT, priv->regs + HC_EN);
448 writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
449 priv->regs + HC_CFG);
450
451 return 0;
452}
453
454static int mxic_spi_release_bus(struct udevice *dev)
455{
456 struct udevice *bus = dev_get_parent(dev);
457 struct mxic_spi_priv *priv = dev_get_priv(bus);
458
459 writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
460 priv->regs + HC_CFG);
461 writel(0, priv->regs + HC_EN);
462
463 return 0;
464}
465
466static int mxic_spi_xfer(struct udevice *dev, unsigned int bitlen,
467 const void *dout, void *din, unsigned long flags)
468{
469 struct udevice *bus = dev_get_parent(dev);
470 struct mxic_spi_priv *priv = dev_get_priv(bus);
471 struct spi_slave *slave = dev_get_parent_priv(dev);
472 unsigned int busw = OP_BUSW_1;
473 unsigned int len = bitlen / 8;
474 int ret;
475
476 if (dout && din) {
477 if (((slave->mode & SPI_TX_QUAD) &&
478 !(slave->mode & SPI_RX_QUAD)) ||
479 ((slave->mode & SPI_TX_DUAL) &&
480 !(slave->mode & SPI_RX_DUAL)))
481 return -ENOTSUPP;
482 }
483
484 if (din) {
485 if (slave->mode & SPI_TX_QUAD)
486 busw = OP_BUSW_4;
487 else if (slave->mode & SPI_TX_DUAL)
488 busw = OP_BUSW_2;
489 } else if (dout) {
490 if (slave->mode & SPI_RX_QUAD)
491 busw = OP_BUSW_4;
492 else if (slave->mode & SPI_RX_DUAL)
493 busw = OP_BUSW_2;
494 }
495
496 writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
497 OP_DATA_BUSW(busw) | (din ? OP_READ : 0),
498 priv->regs + SS_CTRL(0));
499
500 ret = mxic_spi_data_xfer(priv, dout, din, len);
501 if (ret)
502 return ret;
503
504 return 0;
505}
506
507static int mxic_spi_probe(struct udevice *bus)
508{
509 struct mxic_spi_priv *priv = dev_get_priv(bus);
510
511 priv->regs = (void *)dev_read_addr(bus);
512
513 priv->send_clk = devm_clk_get(bus, "send_clk");
514 if (IS_ERR(priv->send_clk))
515 return PTR_ERR(priv->send_clk);
516
517 priv->send_dly_clk = devm_clk_get(bus, "send_dly_clk");
518 if (IS_ERR(priv->send_dly_clk))
519 return PTR_ERR(priv->send_dly_clk);
520
521 mxic_spi_hw_init(priv);
522
523 return 0;
524}
525
526static const struct dm_spi_ops mxic_spi_ops = {
527 .claim_bus = mxic_spi_claim_bus,
528 .release_bus = mxic_spi_release_bus,
529 .xfer = mxic_spi_xfer,
530 .set_speed = mxic_spi_set_speed,
531 .set_mode = mxic_spi_set_mode,
532 .mem_ops = &mxic_spi_mem_ops,
533};
534
535static const struct udevice_id mxic_spi_ids[] = {
536 { .compatible = "mxicy,mx25f0a-spi", },
537 { }
538};
539
540U_BOOT_DRIVER(mxic_spi) = {
541 .name = "mxic_spi",
542 .id = UCLASS_SPI,
543 .of_match = mxic_spi_ids,
544 .ops = &mxic_spi_ops,
545 .priv_auto = sizeof(struct mxic_spi_priv),
546 .probe = mxic_spi_probe,
547};
548
