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11#include <common.h>
12#include <dm.h>
13#include <timer.h>
14#include <asm/io.h>
15#include <dm/device-internal.h>
16#include <linux/err.h>
17
18
19#define MTIME_REG(base) ((ulong)(base))
20
21static u64 notrace andes_plmt_get_count(struct udevice *dev)
22{
23 return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
24}
25
26#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
27
28
29
30unsigned long notrace timer_early_get_rate(void)
31{
32 return RISCV_MMODE_TIMER_FREQ;
33}
34
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38
39u64 notrace timer_early_get_count(void)
40{
41 return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
42}
43#endif
44
45static const struct timer_ops andes_plmt_ops = {
46 .get_count = andes_plmt_get_count,
47};
48
49static int andes_plmt_probe(struct udevice *dev)
50{
51 dev_set_priv(dev, dev_read_addr_ptr(dev));
52 if (!dev_get_priv(dev))
53 return -EINVAL;
54
55 return timer_timebase_fallback(dev);
56}
57
58static const struct udevice_id andes_plmt_ids[] = {
59 { .compatible = "riscv,plmt0" },
60 { }
61};
62
63U_BOOT_DRIVER(andes_plmt) = {
64 .name = "andes_plmt",
65 .id = UCLASS_TIMER,
66 .of_match = andes_plmt_ids,
67 .ops = &andes_plmt_ops,
68 .probe = andes_plmt_probe,
69 .flags = DM_FLAG_PRE_RELOC,
70};
71