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7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <timer.h>
11#include <asm/io.h>
12#include <dm/device-internal.h>
13#include <linux/err.h>
14
15
16#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
17
18static u64 notrace sifive_clint_get_count(struct udevice *dev)
19{
20 return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
21}
22
23#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
24
25
26
27unsigned long notrace timer_early_get_rate(void)
28{
29 return RISCV_MMODE_TIMER_FREQ;
30}
31
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35
36u64 notrace timer_early_get_count(void)
37{
38 return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
39}
40#endif
41
42static const struct timer_ops sifive_clint_ops = {
43 .get_count = sifive_clint_get_count,
44};
45
46static int sifive_clint_probe(struct udevice *dev)
47{
48 dev_set_priv(dev, dev_read_addr_ptr(dev));
49 if (!dev_get_priv(dev))
50 return -EINVAL;
51
52 return timer_timebase_fallback(dev);
53}
54
55static const struct udevice_id sifive_clint_ids[] = {
56 { .compatible = "riscv,clint0" },
57 { .compatible = "sifive,clint0" },
58 { }
59};
60
61U_BOOT_DRIVER(sifive_clint) = {
62 .name = "sifive_clint",
63 .id = UCLASS_TIMER,
64 .of_match = sifive_clint_ids,
65 .probe = sifive_clint_probe,
66 .ops = &sifive_clint_ops,
67 .flags = DM_FLAG_PRE_RELOC,
68};
69