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15#include <common.h>
16#include <cpu_func.h>
17#include <dm.h>
18#include <dm/device_compat.h>
19#include <linux/bug.h>
20#include <linux/kernel.h>
21#include <linux/list.h>
22
23#include <linux/usb/ch9.h>
24#include <linux/usb/gadget.h>
25#include <linux/usb/composite.h>
26
27#include "core.h"
28#include "gadget.h"
29#include "io.h"
30
31#include "linux-compat.h"
32
33static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
34static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
35 struct dwc3_ep *dep, struct dwc3_request *req);
36
37static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
38{
39 switch (state) {
40 case EP0_UNCONNECTED:
41 return "Unconnected";
42 case EP0_SETUP_PHASE:
43 return "Setup Phase";
44 case EP0_DATA_PHASE:
45 return "Data Phase";
46 case EP0_STATUS_PHASE:
47 return "Status Phase";
48 default:
49 return "UNKNOWN";
50 }
51}
52
53static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
54 u32 len, u32 type, unsigned chain)
55{
56 struct dwc3_gadget_ep_cmd_params params;
57 struct dwc3_trb *trb;
58 struct dwc3_ep *dep;
59
60 int ret;
61
62 dep = dwc->eps[epnum];
63 if (dep->flags & DWC3_EP_BUSY) {
64 dev_vdbg(dwc->dev, "%s still busy", dep->name);
65 return 0;
66 }
67
68 trb = &dwc->ep0_trb[dep->free_slot];
69
70 if (chain)
71 dep->free_slot++;
72
73 trb->bpl = lower_32_bits(buf_dma);
74 trb->bph = upper_32_bits(buf_dma);
75 trb->size = len;
76 trb->ctrl = type;
77
78 trb->ctrl |= (DWC3_TRB_CTRL_HWO
79 | DWC3_TRB_CTRL_ISP_IMI);
80
81 if (chain)
82 trb->ctrl |= DWC3_TRB_CTRL_CHN;
83 else
84 trb->ctrl |= (DWC3_TRB_CTRL_IOC
85 | DWC3_TRB_CTRL_LST);
86
87 dwc3_flush_cache((uintptr_t)buf_dma, len);
88 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
89
90 if (chain)
91 return 0;
92
93 memset(¶ms, 0, sizeof(params));
94 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
95 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
96
97 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
98 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
99 if (ret < 0) {
100 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
101 return ret;
102 }
103
104 dep->flags |= DWC3_EP_BUSY;
105 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
106 dep->number);
107
108 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
109
110 return 0;
111}
112
113static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
114 struct dwc3_request *req)
115{
116 struct dwc3 *dwc = dep->dwc;
117
118 req->request.actual = 0;
119 req->request.status = -EINPROGRESS;
120 req->epnum = dep->number;
121
122 list_add_tail(&req->list, &dep->request_list);
123
124
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129
130
131
132
133 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
134 unsigned direction;
135
136 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
137
138 if (dwc->ep0state != EP0_DATA_PHASE) {
139 dev_WARN(dwc->dev, "Unexpected pending request\n");
140 return 0;
141 }
142
143 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
144
145 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
146 DWC3_EP0_DIR_IN);
147
148 return 0;
149 }
150
151
152
153
154
155 if (dwc->delayed_status) {
156 unsigned direction;
157
158 direction = !dwc->ep0_expect_in;
159 dwc->delayed_status = false;
160 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
161
162 if (dwc->ep0state == EP0_STATUS_PHASE)
163 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
164 else
165 dev_dbg(dwc->dev, "too early for delayed status");
166
167 return 0;
168 }
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201
202 if (dwc->three_stage_setup) {
203 unsigned direction;
204
205 direction = dwc->ep0_expect_in;
206 dwc->ep0state = EP0_DATA_PHASE;
207
208 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
209
210 dep->flags &= ~DWC3_EP0_DIR_IN;
211 }
212
213 return 0;
214}
215
216int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
217 gfp_t gfp_flags)
218{
219 struct dwc3_request *req = to_dwc3_request(request);
220 struct dwc3_ep *dep = to_dwc3_ep(ep);
221 struct dwc3 *dwc = dep->dwc;
222
223 unsigned long flags;
224
225 int ret;
226
227 spin_lock_irqsave(&dwc->lock, flags);
228 if (!dep->endpoint.desc) {
229 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
230 request, dep->name);
231 ret = -ESHUTDOWN;
232 goto out;
233 }
234
235
236 if (!list_empty(&dep->request_list)) {
237 ret = -EBUSY;
238 goto out;
239 }
240
241 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
242 request, dep->name, request->length,
243 dwc3_ep0_state_string(dwc->ep0state));
244
245 ret = __dwc3_gadget_ep0_queue(dep, req);
246
247out:
248 spin_unlock_irqrestore(&dwc->lock, flags);
249
250 return ret;
251}
252
253static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
254{
255 struct dwc3_ep *dep;
256
257
258 dep = dwc->eps[1];
259 dep->flags = DWC3_EP_ENABLED;
260
261
262 dep = dwc->eps[0];
263 __dwc3_gadget_ep_set_halt(dep, 1, false);
264 dep->flags = DWC3_EP_ENABLED;
265 dwc->delayed_status = false;
266
267 if (!list_empty(&dep->request_list)) {
268 struct dwc3_request *req;
269
270 req = next_request(&dep->request_list);
271 dwc3_gadget_giveback(dep, req, -ECONNRESET);
272 }
273
274 dwc->ep0state = EP0_SETUP_PHASE;
275 dwc3_ep0_out_start(dwc);
276}
277
278int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
279{
280 struct dwc3_ep *dep = to_dwc3_ep(ep);
281 struct dwc3 *dwc = dep->dwc;
282
283 dwc3_ep0_stall_and_restart(dwc);
284
285 return 0;
286}
287
288int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
289{
290 unsigned long flags;
291 int ret;
292
293 spin_lock_irqsave(&dwc->lock, flags);
294 ret = __dwc3_gadget_ep0_set_halt(ep, value);
295 spin_unlock_irqrestore(&dwc->lock, flags);
296
297 return ret;
298}
299
300void dwc3_ep0_out_start(struct dwc3 *dwc)
301{
302 int ret;
303
304 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
305 DWC3_TRBCTL_CONTROL_SETUP, 0);
306 WARN_ON(ret < 0);
307}
308
309static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
310{
311 struct dwc3_ep *dep;
312 u32 windex = le16_to_cpu(wIndex_le);
313 u32 epnum;
314
315 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
316 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
317 epnum |= 1;
318
319 dep = dwc->eps[epnum];
320 if (dep->flags & DWC3_EP_ENABLED)
321 return dep;
322
323 return NULL;
324}
325
326static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
327{
328}
329
330
331
332static int dwc3_ep0_handle_status(struct dwc3 *dwc,
333 struct usb_ctrlrequest *ctrl)
334{
335 struct dwc3_ep *dep;
336 u32 recip;
337 u32 reg;
338 u16 usb_status = 0;
339 __le16 *response_pkt;
340
341 recip = ctrl->bRequestType & USB_RECIP_MASK;
342 switch (recip) {
343 case USB_RECIP_DEVICE:
344
345
346
347 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
348
349 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
350 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
351 if (reg & DWC3_DCTL_INITU1ENA)
352 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
353 if (reg & DWC3_DCTL_INITU2ENA)
354 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
355 }
356
357 break;
358
359 case USB_RECIP_INTERFACE:
360
361
362
363
364 break;
365
366 case USB_RECIP_ENDPOINT:
367 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
368 if (!dep)
369 return -EINVAL;
370
371 if (dep->flags & DWC3_EP_STALL)
372 usb_status = 1 << USB_ENDPOINT_HALT;
373 break;
374 default:
375 return -EINVAL;
376 }
377
378 response_pkt = (__le16 *) dwc->setup_buf;
379 *response_pkt = cpu_to_le16(usb_status);
380
381 dep = dwc->eps[0];
382 dwc->ep0_usb_req.dep = dep;
383 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
384 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
385 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
386
387 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
388}
389
390static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
391 struct usb_ctrlrequest *ctrl, int set)
392{
393 struct dwc3_ep *dep;
394 u32 recip;
395 u32 wValue;
396 u32 wIndex;
397 u32 reg;
398 int ret;
399 enum usb_device_state state;
400
401 wValue = le16_to_cpu(ctrl->wValue);
402 wIndex = le16_to_cpu(ctrl->wIndex);
403 recip = ctrl->bRequestType & USB_RECIP_MASK;
404 state = dwc->gadget.state;
405
406 switch (recip) {
407 case USB_RECIP_DEVICE:
408
409 switch (wValue) {
410 case USB_DEVICE_REMOTE_WAKEUP:
411 break;
412
413
414
415
416 case USB_DEVICE_U1_ENABLE:
417 if (state != USB_STATE_CONFIGURED)
418 return -EINVAL;
419 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 return -EINVAL;
421
422 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
423 if (set)
424 reg |= DWC3_DCTL_INITU1ENA;
425 else
426 reg &= ~DWC3_DCTL_INITU1ENA;
427 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 break;
429
430 case USB_DEVICE_U2_ENABLE:
431 if (state != USB_STATE_CONFIGURED)
432 return -EINVAL;
433 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
434 return -EINVAL;
435
436 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
437 if (set)
438 reg |= DWC3_DCTL_INITU2ENA;
439 else
440 reg &= ~DWC3_DCTL_INITU2ENA;
441 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
442 break;
443
444 case USB_DEVICE_LTM_ENABLE:
445 return -EINVAL;
446
447 case USB_DEVICE_TEST_MODE:
448 if ((wIndex & 0xff) != 0)
449 return -EINVAL;
450 if (!set)
451 return -EINVAL;
452
453 dwc->test_mode_nr = wIndex >> 8;
454 dwc->test_mode = true;
455 break;
456 default:
457 return -EINVAL;
458 }
459 break;
460
461 case USB_RECIP_INTERFACE:
462 switch (wValue) {
463 case USB_INTRF_FUNC_SUSPEND:
464 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
465
466 ;
467 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
468
469 ;
470 break;
471 default:
472 return -EINVAL;
473 }
474 break;
475
476 case USB_RECIP_ENDPOINT:
477 switch (wValue) {
478 case USB_ENDPOINT_HALT:
479 dep = dwc3_wIndex_to_dep(dwc, wIndex);
480 if (!dep)
481 return -EINVAL;
482 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
483 break;
484 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
485 if (ret)
486 return -EINVAL;
487 break;
488 default:
489 return -EINVAL;
490 }
491 break;
492
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498}
499
500static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
501{
502 enum usb_device_state state = dwc->gadget.state;
503 u32 addr;
504 u32 reg;
505
506 addr = le16_to_cpu(ctrl->wValue);
507 if (addr > 127) {
508 dev_dbg(dwc->dev, "invalid device address %d", addr);
509 return -EINVAL;
510 }
511
512 if (state == USB_STATE_CONFIGURED) {
513 dev_dbg(dwc->dev, "trying to set address when configured");
514 return -EINVAL;
515 }
516
517 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
518 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
519 reg |= DWC3_DCFG_DEVADDR(addr);
520 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
521
522 if (addr)
523 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
524 else
525 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
526
527 return 0;
528}
529
530static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
531{
532 int ret;
533
534 spin_unlock(&dwc->lock);
535 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
536 spin_lock(&dwc->lock);
537 return ret;
538}
539
540static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
541{
542 enum usb_device_state state = dwc->gadget.state;
543 u32 cfg;
544 int ret;
545 u32 reg;
546
547 dwc->start_config_issued = false;
548 cfg = le16_to_cpu(ctrl->wValue);
549
550 switch (state) {
551 case USB_STATE_DEFAULT:
552 return -EINVAL;
553
554 case USB_STATE_ADDRESS:
555 ret = dwc3_ep0_delegate_req(dwc, ctrl);
556
557 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
558
559
560
561
562
563
564
565 if (ret == 0)
566 usb_gadget_set_state(&dwc->gadget,
567 USB_STATE_CONFIGURED);
568
569
570
571
572
573 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
574 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
575 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
576
577 dwc->resize_fifos = true;
578 dev_dbg(dwc->dev, "resize FIFOs flag SET");
579 }
580 break;
581
582 case USB_STATE_CONFIGURED:
583 ret = dwc3_ep0_delegate_req(dwc, ctrl);
584 if (!cfg && !ret)
585 usb_gadget_set_state(&dwc->gadget,
586 USB_STATE_ADDRESS);
587 break;
588 default:
589 ret = -EINVAL;
590 }
591 return ret;
592}
593
594static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
595{
596 struct dwc3_ep *dep = to_dwc3_ep(ep);
597 struct dwc3 *dwc = dep->dwc;
598
599 u32 param = 0;
600 u32 reg;
601
602 struct timing {
603 u8 u1sel;
604 u8 u1pel;
605 u16 u2sel;
606 u16 u2pel;
607 } __packed timing;
608
609 int ret;
610
611 memcpy(&timing, req->buf, sizeof(timing));
612
613 dwc->u1sel = timing.u1sel;
614 dwc->u1pel = timing.u1pel;
615 dwc->u2sel = le16_to_cpu(timing.u2sel);
616 dwc->u2pel = le16_to_cpu(timing.u2pel);
617
618 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
619 if (reg & DWC3_DCTL_INITU2ENA)
620 param = dwc->u2pel;
621 if (reg & DWC3_DCTL_INITU1ENA)
622 param = dwc->u1pel;
623
624
625
626
627
628
629 if (param > 125)
630 param = 0;
631
632
633 ret = dwc3_send_gadget_generic_command(dwc,
634 DWC3_DGCMD_SET_PERIODIC_PAR, param);
635 WARN_ON(ret < 0);
636}
637
638static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
639{
640 struct dwc3_ep *dep;
641 enum usb_device_state state = dwc->gadget.state;
642 u16 wLength;
643
644 if (state == USB_STATE_DEFAULT)
645 return -EINVAL;
646
647 wLength = le16_to_cpu(ctrl->wLength);
648
649 if (wLength != 6) {
650 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
651 wLength);
652 return -EINVAL;
653 }
654
655
656
657
658
659
660
661
662
663 dep = dwc->eps[0];
664 dwc->ep0_usb_req.dep = dep;
665 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
666 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
667 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
668
669 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
670}
671
672static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
673{
674 u16 wLength;
675 u16 wValue;
676 u16 wIndex;
677
678 wValue = le16_to_cpu(ctrl->wValue);
679 wLength = le16_to_cpu(ctrl->wLength);
680 wIndex = le16_to_cpu(ctrl->wIndex);
681
682 if (wIndex || wLength)
683 return -EINVAL;
684
685
686
687
688
689 dwc->isoch_delay = wValue;
690
691 return 0;
692}
693
694static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
695{
696 int ret;
697
698 switch (ctrl->bRequest) {
699 case USB_REQ_GET_STATUS:
700 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
701 ret = dwc3_ep0_handle_status(dwc, ctrl);
702 break;
703 case USB_REQ_CLEAR_FEATURE:
704 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
705 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
706 break;
707 case USB_REQ_SET_FEATURE:
708 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
709 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
710 break;
711 case USB_REQ_SET_ADDRESS:
712 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
713 ret = dwc3_ep0_set_address(dwc, ctrl);
714 break;
715 case USB_REQ_SET_CONFIGURATION:
716 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
717 ret = dwc3_ep0_set_config(dwc, ctrl);
718 break;
719 case USB_REQ_SET_SEL:
720 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
721 ret = dwc3_ep0_set_sel(dwc, ctrl);
722 break;
723 case USB_REQ_SET_ISOCH_DELAY:
724 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
725 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
726 break;
727 default:
728 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
729 ret = dwc3_ep0_delegate_req(dwc, ctrl);
730 break;
731 }
732
733 return ret;
734}
735
736static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
737 const struct dwc3_event_depevt *event)
738{
739 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
740 int ret = -EINVAL;
741 u32 len;
742
743 if (!dwc->gadget_driver)
744 goto out;
745
746 len = le16_to_cpu(ctrl->wLength);
747 if (!len) {
748 dwc->three_stage_setup = false;
749 dwc->ep0_expect_in = false;
750 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
751 } else {
752 dwc->three_stage_setup = true;
753 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
754 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
755 }
756
757 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
758 ret = dwc3_ep0_std_request(dwc, ctrl);
759 else
760 ret = dwc3_ep0_delegate_req(dwc, ctrl);
761
762 if (ret == USB_GADGET_DELAYED_STATUS)
763 dwc->delayed_status = true;
764
765out:
766 if (ret < 0)
767 dwc3_ep0_stall_and_restart(dwc);
768}
769
770static void dwc3_ep0_complete_data(struct dwc3 *dwc,
771 const struct dwc3_event_depevt *event)
772{
773 struct dwc3_request *r = NULL;
774 struct usb_request *ur;
775 struct dwc3_trb *trb;
776 struct dwc3_ep *ep0;
777 unsigned transfer_size = 0;
778 unsigned maxp;
779 void *buf;
780 u32 transferred = 0;
781 u32 status;
782 u32 length;
783 u8 epnum;
784
785 epnum = event->endpoint_number;
786 ep0 = dwc->eps[0];
787
788 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
789
790 trb = dwc->ep0_trb;
791
792 r = next_request(&ep0->request_list);
793 if (!r)
794 return;
795
796 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
797
798 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
799 if (status == DWC3_TRBSTS_SETUP_PENDING) {
800 dev_dbg(dwc->dev, "Setup Pending received");
801
802 if (r)
803 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
804
805 return;
806 }
807
808 ur = &r->request;
809 buf = ur->buf;
810
811 length = trb->size & DWC3_TRB_SIZE_MASK;
812
813 maxp = ep0->endpoint.maxpacket;
814
815 if (dwc->ep0_bounced) {
816
817
818
819
820 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
821 transfer_size = (ur->length / maxp) * maxp;
822 transferred = transfer_size - length;
823 buf = (u8 *)buf + transferred;
824 ur->actual += transferred;
825
826 trb++;
827 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
828 length = trb->size & DWC3_TRB_SIZE_MASK;
829
830 ep0->free_slot = 0;
831 }
832
833 transfer_size = roundup((ur->length - transfer_size),
834 maxp);
835 transferred = min_t(u32, ur->length - transferred,
836 transfer_size - length);
837 dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
838 memcpy(buf, dwc->ep0_bounce, transferred);
839 } else {
840 transferred = ur->length - length;
841 }
842
843 ur->actual += transferred;
844
845 if ((epnum & 1) && ur->actual < ur->length) {
846
847
848 dwc3_ep0_stall_and_restart(dwc);
849 } else {
850 dwc3_gadget_giveback(ep0, r, 0);
851
852 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
853 ur->length && ur->zero) {
854 int ret;
855
856 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
857
858 ret = dwc3_ep0_start_trans(dwc, epnum,
859 dwc->ctrl_req_addr, 0,
860 DWC3_TRBCTL_CONTROL_DATA, 0);
861 WARN_ON(ret < 0);
862 }
863 }
864}
865
866static void dwc3_ep0_complete_status(struct dwc3 *dwc,
867 const struct dwc3_event_depevt *event)
868{
869 struct dwc3_request *r;
870 struct dwc3_ep *dep;
871 struct dwc3_trb *trb;
872 u32 status;
873
874 dep = dwc->eps[0];
875 trb = dwc->ep0_trb;
876
877 if (!list_empty(&dep->request_list)) {
878 r = next_request(&dep->request_list);
879
880 dwc3_gadget_giveback(dep, r, 0);
881 }
882
883 if (dwc->test_mode) {
884 int ret;
885
886 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
887 if (ret < 0) {
888 dev_dbg(dwc->dev, "Invalid Test #%d",
889 dwc->test_mode_nr);
890 dwc3_ep0_stall_and_restart(dwc);
891 return;
892 }
893 }
894
895 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
896 if (status == DWC3_TRBSTS_SETUP_PENDING)
897 dev_dbg(dwc->dev, "Setup Pending received");
898
899 dwc->ep0state = EP0_SETUP_PHASE;
900 dwc3_ep0_out_start(dwc);
901}
902
903static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
904 const struct dwc3_event_depevt *event)
905{
906 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
907
908 dep->flags &= ~DWC3_EP_BUSY;
909 dep->resource_index = 0;
910 dwc->setup_packet_pending = false;
911
912 switch (dwc->ep0state) {
913 case EP0_SETUP_PHASE:
914 dev_vdbg(dwc->dev, "Setup Phase");
915 dwc3_ep0_inspect_setup(dwc, event);
916 break;
917
918 case EP0_DATA_PHASE:
919 dev_vdbg(dwc->dev, "Data Phase");
920 dwc3_ep0_complete_data(dwc, event);
921 break;
922
923 case EP0_STATUS_PHASE:
924 dev_vdbg(dwc->dev, "Status Phase");
925 dwc3_ep0_complete_status(dwc, event);
926 break;
927 default:
928 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
929 }
930}
931
932static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
933 struct dwc3_ep *dep, struct dwc3_request *req)
934{
935 int ret;
936
937 req->direction = !!dep->number;
938
939 if (req->request.length == 0) {
940 ret = dwc3_ep0_start_trans(dwc, dep->number,
941 dwc->ctrl_req_addr, 0,
942 DWC3_TRBCTL_CONTROL_DATA, 0);
943 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
944 (dep->number == 0)) {
945 u32 transfer_size = 0;
946 u32 maxpacket;
947
948 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
949 dep->number);
950 if (ret) {
951 dev_dbg(dwc->dev, "failed to map request\n");
952 return;
953 }
954
955 maxpacket = dep->endpoint.maxpacket;
956 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
957 transfer_size = (req->request.length / maxpacket) *
958 maxpacket;
959 ret = dwc3_ep0_start_trans(dwc, dep->number,
960 req->request.dma,
961 transfer_size,
962 DWC3_TRBCTL_CONTROL_DATA, 1);
963 }
964
965 transfer_size = roundup((req->request.length - transfer_size),
966 maxpacket);
967
968 dwc->ep0_bounced = true;
969
970
971
972
973
974
975 ret = dwc3_ep0_start_trans(dwc, dep->number,
976 dwc->ep0_bounce_addr, transfer_size,
977 DWC3_TRBCTL_CONTROL_DATA, 0);
978 } else {
979 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
980 dep->number);
981 if (ret) {
982 dev_dbg(dwc->dev, "failed to map request\n");
983 return;
984 }
985
986 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
987 req->request.length,
988 DWC3_TRBCTL_CONTROL_DATA, 0);
989 }
990
991 WARN_ON(ret < 0);
992}
993
994static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
995{
996 struct dwc3 *dwc = dep->dwc;
997 u32 type;
998
999 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1000 : DWC3_TRBCTL_CONTROL_STATUS2;
1001
1002 return dwc3_ep0_start_trans(dwc, dep->number,
1003 dwc->ctrl_req_addr, 0, type, 0);
1004}
1005
1006static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1007{
1008 if (dwc->resize_fifos) {
1009 dev_dbg(dwc->dev, "Resizing FIFOs");
1010 dwc3_gadget_resize_tx_fifos(dwc);
1011 dwc->resize_fifos = 0;
1012 }
1013
1014 WARN_ON(dwc3_ep0_start_control_status(dep));
1015}
1016
1017static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1018 const struct dwc3_event_depevt *event)
1019{
1020 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1021
1022 __dwc3_ep0_do_control_status(dwc, dep);
1023}
1024
1025static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1026{
1027 struct dwc3_gadget_ep_cmd_params params;
1028 u32 cmd;
1029 int ret;
1030
1031 if (!dep->resource_index)
1032 return;
1033
1034 cmd = DWC3_DEPCMD_ENDTRANSFER;
1035 cmd |= DWC3_DEPCMD_CMDIOC;
1036 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1037 memset(¶ms, 0, sizeof(params));
1038 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1039 WARN_ON_ONCE(ret);
1040 dep->resource_index = 0;
1041}
1042
1043static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1044 const struct dwc3_event_depevt *event)
1045{
1046 dwc->setup_packet_pending = true;
1047
1048 switch (event->status) {
1049 case DEPEVT_STATUS_CONTROL_DATA:
1050 dev_vdbg(dwc->dev, "Control Data");
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061 if (dwc->ep0_expect_in != event->endpoint_number) {
1062 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1063
1064 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1065 dwc3_ep0_end_control_data(dwc, dep);
1066 dwc3_ep0_stall_and_restart(dwc);
1067 return;
1068 }
1069
1070 break;
1071
1072 case DEPEVT_STATUS_CONTROL_STATUS:
1073 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1074 return;
1075
1076 dev_vdbg(dwc->dev, "Control Status");
1077
1078 dwc->ep0state = EP0_STATUS_PHASE;
1079
1080 if (dwc->delayed_status) {
1081 WARN_ON_ONCE(event->endpoint_number != 1);
1082 dev_vdbg(dwc->dev, "Delayed Status");
1083 return;
1084 }
1085
1086 dwc3_ep0_do_control_status(dwc, event);
1087 }
1088}
1089
1090void dwc3_ep0_interrupt(struct dwc3 *dwc,
1091 const struct dwc3_event_depevt *event)
1092{
1093 u8 epnum = event->endpoint_number;
1094
1095 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1096 dwc3_ep_event_string(event->endpoint_event),
1097 epnum >> 1, (epnum & 1) ? "in" : "out",
1098 dwc3_ep0_state_string(dwc->ep0state));
1099
1100 switch (event->endpoint_event) {
1101 case DWC3_DEPEVT_XFERCOMPLETE:
1102 dwc3_ep0_xfer_complete(dwc, event);
1103 break;
1104
1105 case DWC3_DEPEVT_XFERNOTREADY:
1106 dwc3_ep0_xfernotready(dwc, event);
1107 break;
1108
1109 case DWC3_DEPEVT_XFERINPROGRESS:
1110 case DWC3_DEPEVT_RXTXFIFOEVT:
1111 case DWC3_DEPEVT_STREAMEVT:
1112 case DWC3_DEPEVT_EPCMDCMPLT:
1113 break;
1114 }
1115}
1116