LXR uboot/drivers/usb/host/utmi-armada100.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2012
   4 * eInfochips Ltd. <www.einfochips.com>
   5 * Written-by: Ajay Bhargav <contact@8051projects.net>
   6 *
   7 * (C) Copyright 2009
   8 * Marvell Semiconductor <www.marvell.com>
   9 */
  10
  11#include <common.h>
  12#include <asm/io.h>
  13#include <usb.h>
  14#include <asm/arch/cpu.h>
  15#include <asm/arch/armada100.h>
  16#include <asm/arch/utmi-armada100.h>
  17#include <linux/delay.h>
  18
  19static int utmi_phy_init(void)
  20{
  21        struct armd1usb_phy_reg *phy_regs =
  22                (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
  23        int timeout;
  24
  25        setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
  26        udelay(1000);
  27        setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
  28
  29        clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
  30        setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
  31
  32        setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
  33
  34        /* Calibrate pll */
  35        timeout = 10000;
  36        while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  37                ;
  38        if (!timeout)
  39                return -1;
  40
  41        udelay(200);
  42        setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  43        udelay(400);
  44        clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  45
  46        udelay(200);
  47        setbits_le32(&phy_regs->utmi_tx, RCAL_START);
  48        udelay(400);
  49        clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
  50
  51        timeout = 10000;
  52        while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  53                ;
  54        if (!timeout)
  55                return -1;
  56
  57        return 0;
  58}
  59
  60/*
  61 * Initialize USB host controller's UTMI Physical interface
  62 */
  63int utmi_init(void)
  64{
  65        struct armd1mpmu_registers *mpmu_regs =
  66                (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
  67
  68        struct armd1apmu_registers *apmu_regs =
  69                (struct armd1apmu_registers *)ARMD1_APMU_BASE;
  70
  71        /* Turn on 26Mhz ref clock for UTMI PLL */
  72        setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
  73
  74        /* USB Clock reset */
  75        writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
  76        writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
  77
  78        /* Initialize UTMI transceiver */
  79        return utmi_phy_init();
  80}
  81