1
2
3
4
5
6
7
8
9
10
11#include <linux/log2.h>
12#include <linux/bitmap.h>
13
14#include "mtu3.h"
15#include "mtu3_dr.h"
16
17static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
18{
19 struct mtu3_fifo_info *fifo = mep->fifo;
20 struct mtu3 *mtu = mep->mtu;
21 u32 fz_bit;
22
23 mep->fifo_seg_size = mtu->is_u3_ip ? USB_SS_MAXP : USB_HS_MAXP;
24
25 fz_bit = find_first_zero_bit(fifo->bitmap, fifo->limit);
26 if (fz_bit >= fifo->limit)
27 return -EOVERFLOW;
28
29 mep->fifo_size = mep->fifo_seg_size * (mep->slot + 1);
30 mep->fifo_addr = fifo->base + mep->fifo_size * fz_bit;
31 generic_set_bit(fz_bit, fifo->bitmap);
32
33 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, bit: %d\n",
34 __func__, mep->fifo_seg_size, mep->fifo_size, fz_bit);
35
36 return mep->fifo_addr;
37}
38
39static void ep_fifo_free(struct mtu3_ep *mep)
40{
41 struct mtu3_fifo_info *fifo = mep->fifo;
42 u32 addr = mep->fifo_addr;
43 u32 bit;
44
45 if (unlikely(addr < fifo->base))
46 return;
47
48 bit = (addr - fifo->base) / mep->fifo_size;
49 generic_clear_bit(bit, fifo->bitmap);
50 mep->fifo_size = 0;
51 mep->fifo_seg_size = 0;
52
53 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, bit: %d\n",
54 __func__, mep->fifo_seg_size, mep->fifo_size, bit);
55}
56
57
58static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
59{
60
61 if (enable)
62 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
63 else
64 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
65
66 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
67}
68
69
70static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
71{
72 if (enable) {
73 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
74 SOFT_CONN | SUSPENDM_ENABLE);
75 } else {
76 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
77 SOFT_CONN | SUSPENDM_ENABLE);
78 }
79 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
80}
81
82
83static int mtu3_device_enable(struct mtu3 *mtu)
84{
85 void __iomem *ibase = mtu->ippc_base;
86 u32 check_clk = 0;
87
88 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
89
90 if (mtu->is_u3_ip) {
91 check_clk = SSUSB_U3_MAC_RST_B_STS;
92 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
93 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
94 SSUSB_U3_PORT_HOST_SEL));
95 }
96 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
97 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
98 SSUSB_U2_PORT_HOST_SEL));
99
100 return ssusb_check_clocks(mtu->ssusb, check_clk);
101}
102
103static void mtu3_device_disable(struct mtu3 *mtu)
104{
105 void __iomem *ibase = mtu->ippc_base;
106
107 if (mtu->is_u3_ip)
108 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
109 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
110
111 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
112 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
113
114 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
115}
116
117
118static void mtu3_device_reset(struct mtu3 *mtu)
119{
120 void __iomem *ibase = mtu->ippc_base;
121
122 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
123 udelay(1);
124 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
125}
126
127static void mtu3_intr_status_clear(struct mtu3 *mtu)
128{
129 void __iomem *mbase = mtu->mac_base;
130
131
132 mtu3_writel(mbase, U3D_EPISR, ~0x0);
133
134 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
135
136 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
137
138 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
139
140 mtu3_writel(mbase, U3D_QISAR0, ~0x0);
141}
142
143
144static void mtu3_intr_disable(struct mtu3 *mtu)
145{
146
147 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
148
149 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
150 mtu3_intr_status_clear(mtu);
151}
152
153
154static void mtu3_intr_enable(struct mtu3 *mtu)
155{
156 void __iomem *mbase = mtu->mac_base;
157 u32 value;
158
159
160 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
161 mtu3_writel(mbase, U3D_LV1IESR, value);
162
163
164 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
165 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
166
167 if (mtu->is_u3_ip) {
168
169 value = HOT_RST_INTR | WARM_RST_INTR |
170 ENTER_U3_INTR | EXIT_U3_INTR;
171 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
172 }
173
174
175 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
176 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
177 mtu3_writel(mbase, U3D_QIESR1, value);
178
179
180 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
181}
182
183void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
184{
185 void __iomem *mbase = mtu->mac_base;
186
187 if (speed > mtu->max_speed)
188 speed = mtu->max_speed;
189
190 switch (speed) {
191 case USB_SPEED_FULL:
192
193 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
194
195 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
196 break;
197 case USB_SPEED_HIGH:
198 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
199
200 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
201 break;
202 case USB_SPEED_SUPER:
203 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
204 SSUSB_U3_PORT_SSP_SPEED);
205 break;
206 case USB_SPEED_SUPER_PLUS:
207 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
208 SSUSB_U3_PORT_SSP_SPEED);
209 break;
210 default:
211 dev_err(mtu->dev, "invalid speed: %d\n", speed);
212 return;
213 }
214
215 mtu->speed = speed;
216 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(mtu->speed));
217}
218
219
220static void mtu3_ep_reset(struct mtu3_ep *mep)
221{
222 struct mtu3 *mtu = mep->mtu;
223 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
224
225 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
226 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
227}
228
229
230void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
231{
232 struct mtu3 *mtu = mep->mtu;
233 void __iomem *mbase = mtu->mac_base;
234 u8 epnum = mep->epnum;
235 u32 csr;
236
237 if (mep->is_in) {
238 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
239 if (set)
240 csr |= TX_SENDSTALL;
241 else
242 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
243 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
244 } else {
245 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
246 if (set)
247 csr |= RX_SENDSTALL;
248 else
249 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
250 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
251 }
252
253 if (!set) {
254 mtu3_ep_reset(mep);
255 mep->flags &= ~MTU3_EP_STALL;
256 } else {
257 mep->flags |= MTU3_EP_STALL;
258 }
259
260 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
261 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
262}
263
264void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
265{
266 if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
267 mtu3_ss_func_set(mtu, is_on);
268 else
269 mtu3_hs_softconn_set(mtu, is_on);
270
271 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
272 usb_speed_string(mtu->speed), is_on ? "+" : "-");
273}
274
275void mtu3_start(struct mtu3 *mtu)
276{
277 void __iomem *mbase = mtu->mac_base;
278
279 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
280 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
281
282
283 mtu3_intr_enable(mtu);
284 mtu->is_active = 1;
285
286 if (mtu->softconnect)
287 mtu3_dev_on_off(mtu, 1);
288}
289
290void mtu3_stop(struct mtu3 *mtu)
291{
292 dev_dbg(mtu->dev, "%s\n", __func__);
293
294 mtu3_intr_disable(mtu);
295
296 if (mtu->softconnect)
297 mtu3_dev_on_off(mtu, 0);
298
299 mtu->is_active = 0;
300}
301
302
303int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
304 int interval, int burst, int mult)
305{
306 void __iomem *mbase = mtu->mac_base;
307 bool gen2cp = mtu->gen2cp;
308 int epnum = mep->epnum;
309 u32 csr0, csr1, csr2;
310 int fifo_sgsz, fifo_addr;
311 int num_pkts;
312
313 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
314 if (fifo_addr < 0) {
315 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
316 return -ENOMEM;
317 }
318 fifo_sgsz = ilog2(mep->fifo_seg_size);
319 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
320 mep->fifo_seg_size, mep->fifo_size);
321
322 if (mep->is_in) {
323 csr0 = TX_TXMAXPKTSZ(mep->maxp);
324 csr0 |= TX_DMAREQEN;
325
326 num_pkts = (burst + 1) * (mult + 1) - 1;
327 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
328 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
329
330 csr2 = TX_FIFOADDR(fifo_addr >> 4);
331 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
332
333 switch (mep->type) {
334 case USB_ENDPOINT_XFER_BULK:
335 csr1 |= TX_TYPE(TYPE_BULK);
336 break;
337 case USB_ENDPOINT_XFER_ISOC:
338 csr1 |= TX_TYPE(TYPE_ISO);
339 csr2 |= TX_BINTERVAL(interval);
340 break;
341 case USB_ENDPOINT_XFER_INT:
342 csr1 |= TX_TYPE(TYPE_INT);
343 csr2 |= TX_BINTERVAL(interval);
344 break;
345 }
346
347
348 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
349
350 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
351 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
352 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
353
354 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
355 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
356 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
357 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
358 } else {
359 csr0 = RX_RXMAXPKTSZ(mep->maxp);
360 csr0 |= RX_DMAREQEN;
361
362 num_pkts = (burst + 1) * (mult + 1) - 1;
363 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
364 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
365
366 csr2 = RX_FIFOADDR(fifo_addr >> 4);
367 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
368
369 switch (mep->type) {
370 case USB_ENDPOINT_XFER_BULK:
371 csr1 |= RX_TYPE(TYPE_BULK);
372 break;
373 case USB_ENDPOINT_XFER_ISOC:
374 csr1 |= RX_TYPE(TYPE_ISO);
375 csr2 |= RX_BINTERVAL(interval);
376 break;
377 case USB_ENDPOINT_XFER_INT:
378 csr1 |= RX_TYPE(TYPE_INT);
379 csr2 |= RX_BINTERVAL(interval);
380 break;
381 }
382
383
384 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
385
386 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
387 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
388 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
389
390 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
391 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
392 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
393 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
394 }
395
396 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
397 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
398 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
399 fifo_sgsz, mep->fifo_seg_size);
400
401 return 0;
402}
403
404
405void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
406{
407 void __iomem *mbase = mtu->mac_base;
408 int epnum = mep->epnum;
409
410 if (mep->is_in) {
411 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
412 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
413 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
414 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
415 } else {
416 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
417 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
418 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
419 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
420 }
421
422 mtu3_ep_reset(mep);
423 ep_fifo_free(mep);
424
425 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
426}
427
428
429
430
431
432
433
434
435
436
437
438
439
440static void get_ep_fifo_config(struct mtu3 *mtu)
441{
442 struct mtu3_fifo_info *tx_fifo;
443 struct mtu3_fifo_info *rx_fifo;
444 u32 fifosize;
445
446 if (mtu->is_u3_ip) {
447 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
448 tx_fifo = &mtu->tx_fifo;
449 tx_fifo->base = 0;
450 tx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT;
451 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
452
453 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
454 rx_fifo = &mtu->rx_fifo;
455 rx_fifo->base = 0;
456 rx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT;
457 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
458 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
459 } else {
460 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
461 tx_fifo = &mtu->tx_fifo;
462 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
463 tx_fifo->limit = (fifosize / MTU3_U2IP_EP_FIFO_UNIT) >> 1;
464 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
465
466 rx_fifo = &mtu->rx_fifo;
467 rx_fifo->base = tx_fifo->base +
468 tx_fifo->limit * MTU3_U2IP_EP_FIFO_UNIT;
469 rx_fifo->limit = tx_fifo->limit;
470 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
471 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
472 }
473
474 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
475 __func__, tx_fifo->base, tx_fifo->limit,
476 rx_fifo->base, rx_fifo->limit);
477}
478
479void mtu3_ep0_setup(struct mtu3 *mtu)
480{
481 u32 maxpacket = mtu->g.ep0->maxpacket;
482 u32 csr;
483
484 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
485
486 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
487 csr &= ~EP0_MAXPKTSZ_MSK;
488 csr |= EP0_MAXPKTSZ(maxpacket);
489 csr &= EP0_W1C_BITS;
490 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
491
492
493 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
494}
495
496static int mtu3_mem_alloc(struct mtu3 *mtu)
497{
498 void __iomem *mbase = mtu->mac_base;
499 struct mtu3_ep *ep_array;
500 int in_ep_num, out_ep_num;
501 u32 cap_epinfo;
502 int i;
503
504 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
505 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
506 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
507
508 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
509 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
510 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
511
512
513 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
514 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
515 if (!ep_array)
516 return -ENOMEM;
517
518 mtu->ep_array = ep_array;
519 mtu->in_eps = ep_array;
520 mtu->out_eps = &ep_array[mtu->num_eps];
521
522 mtu->ep0 = mtu->in_eps;
523 mtu->ep0->mtu = mtu;
524 mtu->ep0->epnum = 0;
525
526 for (i = 1; i < mtu->num_eps; i++) {
527 struct mtu3_ep *mep = mtu->in_eps + i;
528
529 mep->fifo = &mtu->tx_fifo;
530 mep = mtu->out_eps + i;
531 mep->fifo = &mtu->rx_fifo;
532 }
533
534 get_ep_fifo_config(mtu);
535 mtu3_qmu_init(mtu);
536
537 return 0;
538}
539
540static void mtu3_mem_free(struct mtu3 *mtu)
541{
542 mtu3_qmu_exit(mtu);
543 kfree(mtu->ep_array);
544}
545
546static void mtu3_regs_init(struct mtu3 *mtu)
547{
548 void __iomem *mbase = mtu->mac_base;
549
550
551 mtu3_intr_disable(mtu);
552
553 if (mtu->is_u3_ip) {
554
555 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
556 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
557
558 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
559 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
560
561 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
562
563 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
564
565 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
566 }
567
568
569 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
570
571 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
572
573 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
574
575 mtu3_set_speed(mtu, mtu->max_speed);
576 ssusb_set_force_mode(mtu->ssusb, MTU3_DR_FORCE_DEVICE);
577
578 if (mtu->force_vbus)
579 mtu3_setbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
580 else
581 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
582}
583
584static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
585{
586 void __iomem *mbase = mtu->mac_base;
587 enum usb_device_speed udev_speed;
588 u32 maxpkt = 64;
589 u32 link;
590 u32 speed;
591
592 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
593 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
594 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link);
595 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
596
597 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
598 return IRQ_NONE;
599
600 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
601
602 switch (speed) {
603 case MTU3_SPEED_FULL:
604 udev_speed = USB_SPEED_FULL;
605
606 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
607 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
608 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
609 LPM_BESL_STALL | LPM_BESLD_STALL);
610 break;
611 case MTU3_SPEED_HIGH:
612 udev_speed = USB_SPEED_HIGH;
613
614 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
615 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
616 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
617 LPM_BESL_STALL | LPM_BESLD_STALL);
618 break;
619 case MTU3_SPEED_SUPER:
620 udev_speed = USB_SPEED_SUPER;
621 maxpkt = 512;
622 break;
623 case MTU3_SPEED_SUPER_PLUS:
624 udev_speed = USB_SPEED_SUPER_PLUS;
625 maxpkt = 512;
626 break;
627 default:
628 udev_speed = USB_SPEED_UNKNOWN;
629 break;
630 }
631 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
632
633 mtu->g.speed = udev_speed;
634 mtu->g.ep0->maxpacket = maxpkt;
635 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
636
637 if (udev_speed == USB_SPEED_UNKNOWN)
638 mtu3_gadget_disconnect(mtu);
639 else
640 mtu3_ep0_setup(mtu);
641
642 return IRQ_HANDLED;
643}
644
645static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
646{
647 void __iomem *mbase = mtu->mac_base;
648 u32 ltssm;
649
650 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
651 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
652 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm);
653 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
654
655 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
656 mtu3_gadget_reset(mtu);
657
658 if (ltssm & VBUS_FALL_INTR) {
659 mtu3_ss_func_set(mtu, false);
660 mtu3_gadget_reset(mtu);
661 }
662
663 if (ltssm & VBUS_RISE_INTR)
664 mtu3_ss_func_set(mtu, true);
665
666 if (ltssm & EXIT_U3_INTR)
667 mtu3_gadget_resume(mtu);
668
669 if (ltssm & ENTER_U3_INTR)
670 mtu3_gadget_suspend(mtu);
671
672 return IRQ_HANDLED;
673}
674
675static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
676{
677 void __iomem *mbase = mtu->mac_base;
678 u32 u2comm;
679
680 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
681 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
682 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm);
683 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
684
685 if (u2comm & SUSPEND_INTR)
686 mtu3_gadget_suspend(mtu);
687
688 if (u2comm & RESUME_INTR)
689 mtu3_gadget_resume(mtu);
690
691 if (u2comm & RESET_INTR)
692 mtu3_gadget_reset(mtu);
693
694 return IRQ_HANDLED;
695}
696
697irqreturn_t mtu3_irq(int irq, void *data)
698{
699 struct mtu3 *mtu = (struct mtu3 *)data;
700 unsigned long flags;
701 u32 level1;
702
703 spin_lock_irqsave(&mtu->lock, flags);
704
705
706 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
707 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
708
709 if (level1 & EP_CTRL_INTR)
710 mtu3_link_isr(mtu);
711
712 if (level1 & MAC2_INTR)
713 mtu3_u2_common_isr(mtu);
714
715 if (level1 & MAC3_INTR)
716 mtu3_u3_ltssm_isr(mtu);
717
718 if (level1 & BMU_INTR)
719 mtu3_ep0_isr(mtu);
720
721 if (level1 & QMU_INTR)
722 mtu3_qmu_isr(mtu);
723
724 spin_unlock_irqrestore(&mtu->lock, flags);
725
726 return IRQ_HANDLED;
727}
728
729static void mtu3_check_params(struct mtu3 *mtu)
730{
731
732 switch (mtu->max_speed) {
733 case USB_SPEED_FULL:
734 case USB_SPEED_HIGH:
735 case USB_SPEED_SUPER:
736 case USB_SPEED_SUPER_PLUS:
737 break;
738 default:
739 dev_err(mtu->dev, "invalid max_speed: %d\n", mtu->max_speed);
740
741 case USB_SPEED_UNKNOWN:
742
743 mtu->max_speed = USB_SPEED_SUPER;
744 break;
745 }
746
747 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
748 mtu->max_speed = USB_SPEED_HIGH;
749
750 mtu->speed = mtu->max_speed;
751
752 dev_info(mtu->dev, "max_speed: %s\n", usb_speed_string(mtu->speed));
753}
754
755static int mtu3_hw_init(struct mtu3 *mtu)
756{
757 u32 value;
758 int ret;
759
760 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
761 mtu->hw_version = IP_TRUNK_VERS(value);
762 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
763
764 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
765 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
766
767 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
768 mtu->is_u3_ip ? "U3" : "U2");
769
770 mtu3_check_params(mtu);
771
772 mtu3_device_reset(mtu);
773
774 ret = mtu3_device_enable(mtu);
775 if (ret) {
776 dev_err(mtu->dev, "device enable failed %d\n", ret);
777 return ret;
778 }
779
780 ret = mtu3_mem_alloc(mtu);
781 if (ret)
782 return ret;
783
784 mtu3_regs_init(mtu);
785
786 return 0;
787}
788
789static void mtu3_hw_exit(struct mtu3 *mtu)
790{
791 mtu3_device_disable(mtu);
792 mtu3_mem_free(mtu);
793}
794
795int ssusb_gadget_init(struct ssusb_mtk *ssusb)
796{
797 struct mtu3 *mtu = ssusb->u3d;
798 struct udevice *dev = mtu->dev;
799 int ret = -ENOMEM;
800
801 spin_lock_init(&mtu->lock);
802 mtu->ippc_base = ssusb->ippc_base;
803 mtu->mac_base = ssusb->mac_base;
804 mtu->ssusb = ssusb;
805 mtu->max_speed = usb_get_maximum_speed(dev_ofnode(dev));
806 mtu->force_vbus = dev_read_bool(dev, "mediatek,force-vbus");
807
808 ret = mtu3_hw_init(mtu);
809 if (ret) {
810 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
811 return ret;
812 }
813
814 ret = mtu3_gadget_setup(mtu);
815 if (ret) {
816 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
817 goto gadget_err;
818 }
819
820 dev_info(dev, "%s() done...\n", __func__);
821
822 return 0;
823
824gadget_err:
825 mtu3_hw_exit(mtu);
826 ssusb->u3d = NULL;
827 dev_err(dev, "%s() fail...\n", __func__);
828
829 return ret;
830}
831
832void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
833{
834 struct mtu3 *mtu = ssusb->u3d;
835
836 mtu3_gadget_cleanup(mtu);
837 mtu3_hw_exit(mtu);
838}
839
