1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 4 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com> 5 */ 6 7/* Registers at i2c address 0x38 */ 8 9#include <linux/bitops.h> 10#define ANX9804_HDCP_CONTROL_0_REG 0x01 11 12#define ANX9804_SYS_CTRL1_REG 0x80 13#define ANX9804_SYS_CTRL1_PD_IO 0x80 14#define ANX9804_SYS_CTRL1_PD_VID 0x40 15#define ANX9804_SYS_CTRL1_PD_LINK 0x20 16#define ANX9804_SYS_CTRL1_PD_TOTAL 0x10 17#define ANX9804_SYS_CTRL1_MODE_SEL 0x08 18#define ANX9804_SYS_CTRL1_DET_STA 0x04 19#define ANX9804_SYS_CTRL1_FORCE_DET 0x02 20#define ANX9804_SYS_CTRL1_DET_CTRL 0x01 21 22#define ANX9804_SYS_CTRL2_REG 0x81 23#define ANX9804_SYS_CTRL2_CHA_STA 0x04 24 25#define ANX9804_SYS_CTRL3_REG 0x82 26#define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0) 27#define ANX9804_SYS_CTRL3_F_VALID BIT(1) 28#define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4) 29#define ANX9804_SYS_CTRL3_F_HPD BIT(5) 30 31#define ANX9804_LINK_BW_SET_REG 0xa0 32#define ANX9804_LANE_COUNT_SET_REG 0xa1 33#define ANX9804_TRAINING_PTN_SET_REG 0xa2 34#define ANX9804_TRAINING_LANE0_SET_REG 0xa3 35#define ANX9804_TRAINING_LANE1_SET_REG 0xa4 36#define ANX9804_TRAINING_LANE2_SET_REG 0xa5 37#define ANX9804_TRAINING_LANE3_SET_REG 0xa6 38 39#define ANX9804_LINK_TRAINING_CTRL_REG 0xa8 40#define ANX9804_LINK_TRAINING_CTRL_EN BIT(0) 41 42#define ANX9804_LINK_DEBUG_REG 0xb8 43#define ANX9804_PLL_CTRL_REG 0xc7 44#define ANX9804_ANALOG_POWER_DOWN_REG 0xc8 45 46#define ANX9804_AUX_CH_STA 0xe0 47#define ANX9804_AUX_BUSY BIT(4) 48#define ANX9804_AUX_STATUS_MASK 0x0f 49 50#define ANX9804_DP_AUX_RX_COMM 0xe3 51#define ANX9804_AUX_RX_COMM_I2C_DEFER BIT(3) 52#define ANX9804_AUX_RX_COMM_AUX_DEFER BIT(1) 53 54#define ANX9804_DP_AUX_CH_CTL_1 0xe5 55#define ANX9804_AUX_LENGTH(x) (((x - 1) & 0x0f) << 4) 56#define ANX9804_AUX_TX_COMM_MASK 0x0f 57#define ANX9804_AUX_TX_COMM_DP_TRANSACTION BIT(3) 58#define ANX9804_AUX_TX_COMM_MOT BIT(2) 59#define ANX9804_AUX_TX_COMM_READ BIT(0) 60 61#define ANX9804_DP_AUX_ADDR_7_0 0xe6 62#define ANX9804_DP_AUX_ADDR_15_8 0xe7 63#define ANX9804_DP_AUX_ADDR_19_16 0xe8 64 65#define ANX9804_DP_AUX_CH_CTL_2 0xe9 66#define ANX9804_ADDR_ONLY BIT(1) 67#define ANX9804_AUX_EN BIT(0) 68 69#define ANX9804_BUF_DATA_0 0xf0 70 71/* Registers at i2c address 0x39 */ 72 73#define ANX9804_DEV_IDH_REG 0x03 74 75#define ANX9804_POWERD_CTRL_REG 0x05 76#define ANX9804_POWERD_AUDIO BIT(4) 77 78#define ANX9804_RST_CTRL_REG 0x06 79 80#define ANX9804_RST_CTRL2_REG 0x07 81#define ANX9804_RST_CTRL2_AUX BIT(2) 82#define ANX9804_RST_CTRL2_AC_MODE BIT(6) 83 84#define ANX9804_VID_CTRL1_REG 0x08 85#define ANX9804_VID_CTRL1_VID_EN BIT(7) 86#define ANX9804_VID_CTRL1_EDGE BIT(0) 87 88#define ANX9804_VID_CTRL2_REG 0x09 89#define ANX9804_ANALOG_DEBUG_REG1 0xdc 90#define ANX9804_ANALOG_DEBUG_REG3 0xde 91#define ANX9804_PLL_FILTER_CTRL1 0xdf 92#define ANX9804_PLL_FILTER_CTRL3 0xe1 93#define ANX9804_PLL_FILTER_CTRL 0xe2 94#define ANX9804_PLL_CTRL3 0xe6 95 96#define ANX9804_DP_INT_STA 0xf7 97#define ANX9804_RPLY_RECEIV BIT(1) 98#define ANX9804_AUX_ERR BIT(0) 99