1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Amlogic Meson Video Processing Unit driver 4 * 5 * Copyright (c) 2018 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <asm/io.h> 12 13#include "meson_vpu.h" 14 15/* DMC Registers */ 16#define DMC_CAV_LUT_DATAL 0x48 /* 0x12 offset in data sheet */ 17#define CANVAS_WIDTH_LBIT 29 18#define CANVAS_WIDTH_LWID 3 19#define DMC_CAV_LUT_DATAH 0x4c /* 0x13 offset in data sheet */ 20#define CANVAS_WIDTH_HBIT 0 21#define CANVAS_HEIGHT_BIT 9 22#define CANVAS_BLKMODE_BIT 24 23#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */ 24#define CANVAS_LUT_WR_EN (0x2 << 8) 25#define CANVAS_LUT_RD_EN (0x1 << 8) 26 27void meson_canvas_setup(struct meson_vpu_priv *priv, 28 u32 canvas_index, u32 addr, 29 u32 stride, u32 height, 30 unsigned int wrap, 31 unsigned int blkmode) 32{ 33 dmc_write(DMC_CAV_LUT_DATAL, 34 (((addr + 7) >> 3)) | 35 (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT)); 36 37 dmc_write(DMC_CAV_LUT_DATAH, 38 ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) << 39 CANVAS_WIDTH_HBIT) | 40 (height << CANVAS_HEIGHT_BIT) | 41 (wrap << 22) | 42 (blkmode << CANVAS_BLKMODE_BIT)); 43 44 dmc_write(DMC_CAV_LUT_ADDR, 45 CANVAS_LUT_WR_EN | canvas_index); 46 47 /* Force a read-back to make sure everything is flushed. */ 48 dmc_read(DMC_CAV_LUT_DATAH); 49} 50