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7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <env.h>
11#include <log.h>
12#include <asm/cache.h>
13#include <dm/device_compat.h>
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <malloc.h>
17#include <video.h>
18#include <video_fb.h>
19
20#include <asm/arch/clock.h>
21#include <asm/arch/imx-regs.h>
22#include <asm/arch/sys_proto.h>
23#include <asm/global_data.h>
24#include <asm/mach-imx/dma.h>
25#include <asm/io.h>
26
27#include "videomodes.h"
28
29#define PS2KHZ(ps) (1000000000UL / (ps))
30#define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
31
32#define BITS_PP 18
33#define BYTES_PP 4
34
35struct mxs_dma_desc desc;
36
37
38
39
40
41
42
43
44__weak void mxsfb_system_setup(void)
45{
46}
47
48
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57
58
59
60static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
61 struct display_timing *timings, int bpp)
62{
63 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
64 const enum display_flags flags = timings->flags;
65 uint32_t word_len = 0, bus_width = 0;
66 uint8_t valid_data = 0;
67 uint32_t vdctrl0;
68
69#if CONFIG_IS_ENABLED(CLK)
70 struct clk clk;
71 int ret;
72
73 ret = clk_get_by_name(dev, "pix", &clk);
74 if (ret) {
75 dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
76 return;
77 }
78
79 ret = clk_set_rate(&clk, timings->pixelclock.typ);
80 if (ret < 0) {
81 dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
82 return;
83 }
84
85 ret = clk_enable(&clk);
86 if (ret < 0) {
87 dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
88 return;
89 }
90
91 ret = clk_get_by_name(dev, "axi", &clk);
92 if (ret < 0) {
93 debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
94 } else {
95 ret = clk_enable(&clk);
96 if (ret < 0) {
97 dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
98 return;
99 }
100 }
101
102 ret = clk_get_by_name(dev, "disp_axi", &clk);
103 if (ret < 0) {
104 debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
105 } else {
106 ret = clk_enable(&clk);
107 if (ret < 0) {
108 dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n", ret);
109 return;
110 }
111 }
112#else
113
114 mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
115#endif
116
117
118 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
119
120 switch (bpp) {
121 case 24:
122 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
123 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
124 valid_data = 0x7;
125 break;
126 case 18:
127 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
128 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
129 valid_data = 0x7;
130 break;
131 case 16:
132 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
133 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
134 valid_data = 0xf;
135 break;
136 case 8:
137 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
138 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
139 valid_data = 0xf;
140 break;
141 }
142
143 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
144 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
145 ®s->hw_lcdif_ctrl);
146
147 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
148 ®s->hw_lcdif_ctrl1);
149
150 mxsfb_system_setup();
151
152 writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
153 timings->hactive.typ, ®s->hw_lcdif_transfer_count);
154
155 vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
156 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
157 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
158 timings->vsync_len.typ;
159
160 if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
161 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
162 if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
163 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
164 if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
165 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
166 if(flags & DISPLAY_FLAGS_DE_HIGH)
167 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
168
169 writel(vdctrl0, ®s->hw_lcdif_vdctrl0);
170 writel(timings->vback_porch.typ + timings->vfront_porch.typ +
171 timings->vsync_len.typ + timings->vactive.typ,
172 ®s->hw_lcdif_vdctrl1);
173 writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
174 (timings->hback_porch.typ + timings->hfront_porch.typ +
175 timings->hsync_len.typ + timings->hactive.typ),
176 ®s->hw_lcdif_vdctrl2);
177 writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
178 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
179 (timings->vback_porch.typ + timings->vsync_len.typ),
180 ®s->hw_lcdif_vdctrl3);
181 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
182 ®s->hw_lcdif_vdctrl4);
183
184 writel(fb_addr, ®s->hw_lcdif_cur_buf);
185 writel(fb_addr, ®s->hw_lcdif_next_buf);
186
187
188 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
189
190#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
191
192 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
193#endif
194
195
196 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
197
198
199 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
200}
201
202static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
203 int bpp, u32 fb)
204{
205
206 mxs_lcd_init(dev, fb, timings, bpp);
207
208#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
209
210
211
212
213
214
215
216
217 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
218
219 memset(&desc, 0, sizeof(struct mxs_dma_desc));
220 desc.address = (dma_addr_t)&desc;
221 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
222 MXS_DMA_DESC_WAIT4END |
223 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
224 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
225 desc.cmd.next = (uint32_t)&desc.cmd;
226
227
228 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
229#endif
230
231 return 0;
232}
233
234static int mxs_remove_common(u32 fb)
235{
236 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
237 int timeout = 1000000;
238
239 if (!fb)
240 return -EINVAL;
241
242 writel(fb, ®s->hw_lcdif_cur_buf_reg);
243 writel(fb, ®s->hw_lcdif_next_buf_reg);
244 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
245 while (--timeout) {
246 if (readl(®s->hw_lcdif_ctrl1_reg) &
247 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
248 break;
249 udelay(1);
250 }
251 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
252
253 return 0;
254}
255
256#ifndef CONFIG_DM_VIDEO
257
258static GraphicDevice panel;
259
260void lcdif_power_down(void)
261{
262 mxs_remove_common(panel.frameAdrs);
263}
264
265void *video_hw_init(void)
266{
267 int bpp = -1;
268 int ret = 0;
269 char *penv;
270 void *fb = NULL;
271 struct ctfb_res_modes mode;
272 struct display_timing timings;
273
274 puts("Video: ");
275
276
277 penv = env_get("videomode");
278 if (!penv) {
279 puts("MXSFB: 'videomode' variable not set!\n");
280 return NULL;
281 }
282
283 bpp = video_get_params(&mode, penv);
284
285
286 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
287
288 panel.winSizeX = mode.xres;
289 panel.winSizeY = mode.yres;
290 panel.plnSizeX = mode.xres;
291 panel.plnSizeY = mode.yres;
292
293 switch (bpp) {
294 case 24:
295 case 18:
296 panel.gdfBytesPP = 4;
297 panel.gdfIndex = GDF_32BIT_X888RGB;
298 break;
299 case 16:
300 panel.gdfBytesPP = 2;
301 panel.gdfIndex = GDF_16BIT_565RGB;
302 break;
303 case 8:
304 panel.gdfBytesPP = 1;
305 panel.gdfIndex = GDF__8BIT_INDEX;
306 break;
307 default:
308 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
309 return NULL;
310 }
311
312 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
313
314
315 fb = memalign(ARCH_DMA_MINALIGN,
316 roundup(panel.memSize, ARCH_DMA_MINALIGN));
317 if (!fb) {
318 printf("MXSFB: Error allocating framebuffer!\n");
319 return NULL;
320 }
321
322
323 memset(fb, 0, panel.memSize);
324
325 panel.frameAdrs = (u32)fb;
326
327 printf("%s\n", panel.modeIdent);
328
329 video_ctfb_mode_to_display_timing(&mode, &timings);
330
331 ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
332 if (ret)
333 goto dealloc_fb;
334
335 return (void *)&panel;
336
337dealloc_fb:
338 free(fb);
339
340 return NULL;
341}
342#else
343
344static int mxs_of_get_timings(struct udevice *dev,
345 struct display_timing *timings,
346 u32 *bpp)
347{
348 int ret = 0;
349 u32 display_phandle;
350 ofnode display_node;
351
352 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
353 if (ret) {
354 dev_err(dev, "required display property isn't provided\n");
355 return -EINVAL;
356 }
357
358 display_node = ofnode_get_by_phandle(display_phandle);
359 if (!ofnode_valid(display_node)) {
360 dev_err(dev, "failed to find display subnode\n");
361 return -EINVAL;
362 }
363
364 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
365 if (ret) {
366 dev_err(dev,
367 "required bits-per-pixel property isn't provided\n");
368 return -EINVAL;
369 }
370
371 ret = ofnode_decode_display_timing(display_node, 0, timings);
372 if (ret) {
373 dev_err(dev, "failed to get any display timings\n");
374 return -EINVAL;
375 }
376
377 return ret;
378}
379
380static int mxs_video_probe(struct udevice *dev)
381{
382 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
383 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
384
385 struct display_timing timings;
386 u32 bpp = 0;
387 u32 fb_start, fb_end;
388 int ret;
389
390 debug("%s() plat: base 0x%lx, size 0x%x\n",
391 __func__, plat->base, plat->size);
392
393 ret = mxs_of_get_timings(dev, &timings, &bpp);
394 if (ret)
395 return ret;
396
397 ret = mxs_probe_common(dev, &timings, bpp, plat->base);
398 if (ret)
399 return ret;
400
401 switch (bpp) {
402 case 32:
403 case 24:
404 case 18:
405 uc_priv->bpix = VIDEO_BPP32;
406 break;
407 case 16:
408 uc_priv->bpix = VIDEO_BPP16;
409 break;
410 case 8:
411 uc_priv->bpix = VIDEO_BPP8;
412 break;
413 default:
414 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
415 return -EINVAL;
416 }
417
418 uc_priv->xsize = timings.hactive.typ;
419 uc_priv->ysize = timings.vactive.typ;
420
421
422 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
423 fb_end = plat->base + plat->size;
424 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
425 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
426 DCACHE_WRITEBACK);
427 video_set_flush_dcache(dev, true);
428 gd->fb_base = plat->base;
429
430 return ret;
431}
432
433static int mxs_video_bind(struct udevice *dev)
434{
435 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
436 struct display_timing timings;
437 u32 bpp = 0;
438 u32 bytes_pp = 0;
439 int ret;
440
441 ret = mxs_of_get_timings(dev, &timings, &bpp);
442 if (ret)
443 return ret;
444
445 switch (bpp) {
446 case 32:
447 case 24:
448 case 18:
449 bytes_pp = 4;
450 break;
451 case 16:
452 bytes_pp = 2;
453 break;
454 case 8:
455 bytes_pp = 1;
456 break;
457 default:
458 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
459 return -EINVAL;
460 }
461
462 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
463
464 return 0;
465}
466
467static int mxs_video_remove(struct udevice *dev)
468{
469 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
470
471 mxs_remove_common(plat->base);
472
473 return 0;
474}
475
476static const struct udevice_id mxs_video_ids[] = {
477 { .compatible = "fsl,imx23-lcdif" },
478 { .compatible = "fsl,imx28-lcdif" },
479 { .compatible = "fsl,imx7ulp-lcdif" },
480 { .compatible = "fsl,imxrt-lcdif" },
481 { }
482};
483
484U_BOOT_DRIVER(mxs_video) = {
485 .name = "mxs_video",
486 .id = UCLASS_VIDEO,
487 .of_match = mxs_video_ids,
488 .bind = mxs_video_bind,
489 .probe = mxs_video_probe,
490 .remove = mxs_video_remove,
491 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
492};
493#endif
494
