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6#include <common.h>
7#include <dm.h>
8#include <fdtdec.h>
9#include <log.h>
10#include <panel.h>
11#include <part.h>
12#include <pwm.h>
13#include <video.h>
14#include <asm/cache.h>
15#include <asm/global_data.h>
16#include <asm/system.h>
17#include <asm/gpio.h>
18#include <asm/io.h>
19
20#include <asm/arch/clock.h>
21#include <asm/arch/funcmux.h>
22#include <asm/arch/pinmux.h>
23#include <asm/arch/pwm.h>
24#include <asm/arch/display.h>
25#include <asm/arch-tegra/timer.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29
30struct tegra_lcd_priv {
31 int width;
32 int height;
33 enum video_log2_bpp log2_bpp;
34 struct display_timing timing;
35 struct udevice *panel;
36 struct disp_ctlr *disp;
37 fdt_addr_t frame_buffer;
38 unsigned pixel_clock;
39};
40
41enum {
42
43 LCD_MAX_WIDTH = 1366,
44 LCD_MAX_HEIGHT = 768,
45 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
46};
47
48static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
49{
50 unsigned h_dda, v_dda;
51 unsigned long val;
52
53 val = readl(&dc->cmd.disp_win_header);
54 val |= WINDOW_A_SELECT;
55 writel(val, &dc->cmd.disp_win_header);
56
57 writel(win->fmt, &dc->win.color_depth);
58
59 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
60 BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
61
62 val = win->out_x << H_POSITION_SHIFT;
63 val |= win->out_y << V_POSITION_SHIFT;
64 writel(val, &dc->win.pos);
65
66 val = win->out_w << H_SIZE_SHIFT;
67 val |= win->out_h << V_SIZE_SHIFT;
68 writel(val, &dc->win.size);
69
70 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
71 val |= win->h << V_PRESCALED_SIZE_SHIFT;
72 writel(val, &dc->win.prescaled_size);
73
74 writel(0, &dc->win.h_initial_dda);
75 writel(0, &dc->win.v_initial_dda);
76
77 h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
78 v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
79
80 val = h_dda << H_DDA_INC_SHIFT;
81 val |= v_dda << V_DDA_INC_SHIFT;
82 writel(val, &dc->win.dda_increment);
83
84 writel(win->stride, &dc->win.line_stride);
85 writel(0, &dc->win.buf_stride);
86
87 val = WIN_ENABLE;
88 if (win->bpp < 24)
89 val |= COLOR_EXPAND;
90 writel(val, &dc->win.win_opt);
91
92 writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
93 writel(win->x, &dc->winbuf.addr_h_offset);
94 writel(win->y, &dc->winbuf.addr_v_offset);
95
96 writel(0xff00, &dc->win.blend_nokey);
97 writel(0xff00, &dc->win.blend_1win);
98
99 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
100 val |= GENERAL_UPDATE | WIN_A_UPDATE;
101 writel(val, &dc->cmd.state_ctrl);
102}
103
104static int update_display_mode(struct dc_disp_reg *disp,
105 struct tegra_lcd_priv *priv)
106{
107 struct display_timing *dt = &priv->timing;
108 unsigned long val;
109 unsigned long rate;
110 unsigned long div;
111
112 writel(0x0, &disp->disp_timing_opt);
113
114 writel(1 | 1 << 16, &disp->ref_to_sync);
115 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
116 writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
117 &disp->back_porch);
118 writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
119 &disp->front_porch);
120 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
121
122 val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
123 val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
124 writel(val, &disp->data_enable_opt);
125
126 val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
127 val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
128 val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
129 writel(val, &disp->disp_interface_ctrl);
130
131
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134
135
136
137 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
138 div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
139 debug("Display clock %lu, divider %lu\n", rate, div);
140
141 writel(0x00010001, &disp->shift_clk_opt);
142
143 val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
144 val |= div << SHIFT_CLK_DIVIDER_SHIFT;
145 writel(val, &disp->disp_clk_ctrl);
146
147 return 0;
148}
149
150
151static void basic_init(struct dc_cmd_reg *cmd)
152{
153 u32 val;
154
155 writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
156 writel(0x0000011a, &cmd->cont_syncpt_vsync);
157 writel(0x00000000, &cmd->int_type);
158 writel(0x00000000, &cmd->int_polarity);
159 writel(0x00000000, &cmd->int_mask);
160 writel(0x00000000, &cmd->int_enb);
161
162 val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
163 val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
164 val |= PM1_ENABLE;
165 writel(val, &cmd->disp_pow_ctrl);
166
167 val = readl(&cmd->disp_cmd);
168 val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
169 writel(val, &cmd->disp_cmd);
170}
171
172static void basic_init_timer(struct dc_disp_reg *disp)
173{
174 writel(0x00000020, &disp->mem_high_pri);
175 writel(0x00000001, &disp->mem_high_pri_timer);
176}
177
178static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183};
184
185static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
186 0x00000000,
187 0x01000000,
188 0x00000000,
189 0x00000000,
190};
191
192static const u32 rgb_data_tab[PIN_REG_COUNT] = {
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197};
198
199static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00210222,
205 0x00002200,
206 0x00020000,
207};
208
209static void rgb_enable(struct dc_com_reg *com)
210{
211 int i;
212
213 for (i = 0; i < PIN_REG_COUNT; i++) {
214 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
215 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
216 writel(rgb_data_tab[i], &com->pin_output_data[i]);
217 }
218
219 for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
220 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
221}
222
223static int setup_window(struct disp_ctl_win *win,
224 struct tegra_lcd_priv *priv)
225{
226 win->x = 0;
227 win->y = 0;
228 win->w = priv->width;
229 win->h = priv->height;
230 win->out_x = 0;
231 win->out_y = 0;
232 win->out_w = priv->width;
233 win->out_h = priv->height;
234 win->phys_addr = priv->frame_buffer;
235 win->stride = priv->width * (1 << priv->log2_bpp) / 8;
236 debug("%s: depth = %d\n", __func__, priv->log2_bpp);
237 switch (priv->log2_bpp) {
238 case VIDEO_BPP32:
239 win->fmt = COLOR_DEPTH_R8G8B8A8;
240 win->bpp = 32;
241 break;
242 case VIDEO_BPP16:
243 win->fmt = COLOR_DEPTH_B5G6R5;
244 win->bpp = 16;
245 break;
246
247 default:
248 debug("Unsupported LCD bit depth");
249 return -1;
250 }
251
252 return 0;
253}
254
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264
265
266
267static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
268 void *default_lcd_base)
269{
270 struct disp_ctl_win window;
271 struct dc_ctlr *dc;
272
273 priv->frame_buffer = (u32)default_lcd_base;
274
275 dc = (struct dc_ctlr *)priv->disp;
276
277
278
279
280
281
282 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
283 144 * 1000000);
284 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
285 600 * 1000000);
286 basic_init(&dc->cmd);
287 basic_init_timer(&dc->disp);
288 rgb_enable(&dc->com);
289
290 if (priv->pixel_clock)
291 update_display_mode(&dc->disp, priv);
292
293 if (setup_window(&window, priv))
294 return -1;
295
296 update_window(dc, &window);
297
298 return 0;
299}
300
301static int tegra_lcd_probe(struct udevice *dev)
302{
303 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
304 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
305 struct tegra_lcd_priv *priv = dev_get_priv(dev);
306 const void *blob = gd->fdt_blob;
307 int ret;
308
309
310 funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
311 if (tegra_display_probe(blob, priv, (void *)plat->base)) {
312 printf("%s: Failed to probe display driver\n", __func__);
313 return -1;
314 }
315
316 pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
317 pinmux_tristate_disable(PMUX_PINGRP_GPU);
318
319 ret = panel_enable_backlight(priv->panel);
320 if (ret) {
321 debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
322 return ret;
323 }
324
325 mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
326 DCACHE_WRITETHROUGH);
327
328
329 video_set_flush_dcache(dev, true);
330
331 uc_priv->xsize = priv->width;
332 uc_priv->ysize = priv->height;
333 uc_priv->bpix = priv->log2_bpp;
334 debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
335 plat->size);
336
337 return 0;
338}
339
340static int tegra_lcd_of_to_plat(struct udevice *dev)
341{
342 struct tegra_lcd_priv *priv = dev_get_priv(dev);
343 const void *blob = gd->fdt_blob;
344 struct display_timing *timing;
345 int node = dev_of_offset(dev);
346 int panel_node;
347 int rgb;
348 int ret;
349
350 priv->disp = dev_read_addr_ptr(dev);
351 if (!priv->disp) {
352 debug("%s: No display controller address\n", __func__);
353 return -EINVAL;
354 }
355
356 rgb = fdt_subnode_offset(blob, node, "rgb");
357 if (rgb < 0) {
358 debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
359 __func__, dev->name, rgb);
360 return -EINVAL;
361 }
362
363 ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
364 if (ret) {
365 debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
366 __func__, dev->name, ret);
367 return -EINVAL;
368 }
369 timing = &priv->timing;
370 priv->width = timing->hactive.typ;
371 priv->height = timing->vactive.typ;
372 priv->pixel_clock = timing->pixelclock.typ;
373 priv->log2_bpp = VIDEO_BPP16;
374
375
376
377
378
379 panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
380 if (panel_node < 0) {
381 debug("%s: Cannot find panel information\n", __func__);
382 return -EINVAL;
383 }
384 ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
385 &priv->panel);
386 if (ret) {
387 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
388 dev->name, ret);
389 return ret;
390 }
391
392 return 0;
393}
394
395static int tegra_lcd_bind(struct udevice *dev)
396{
397 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
398 const void *blob = gd->fdt_blob;
399 int node = dev_of_offset(dev);
400 int rgb;
401
402 rgb = fdt_subnode_offset(blob, node, "rgb");
403 if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
404 return -ENODEV;
405
406 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
407 (1 << LCD_MAX_LOG2_BPP) / 8;
408
409 return 0;
410}
411
412static const struct video_ops tegra_lcd_ops = {
413};
414
415static const struct udevice_id tegra_lcd_ids[] = {
416 { .compatible = "nvidia,tegra20-dc" },
417 { }
418};
419
420U_BOOT_DRIVER(tegra_lcd) = {
421 .name = "tegra_lcd",
422 .id = UCLASS_VIDEO,
423 .of_match = tegra_lcd_ids,
424 .ops = &tegra_lcd_ops,
425 .bind = tegra_lcd_bind,
426 .probe = tegra_lcd_probe,
427 .of_to_plat = tegra_lcd_of_to_plat,
428 .priv_auto = sizeof(struct tegra_lcd_priv),
429};
430
