LXR uboot/drivers/watchdog/xilinx_tb

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Xilinx AXI platforms watchdog timer driver.
   4 *
   5 * Author(s):   Michal Simek <michal.simek@xilinx.com>
   6 *              Shreenidhi Shedi <yesshedi@gmail.com>
   7 *
   8 * Copyright (c) 2011-2018 Xilinx Inc.
   9 */
  10
  11#include <common.h>
  12#include <dm.h>
  13#include <log.h>
  14#include <wdt.h>
  15#include <linux/err.h>
  16#include <linux/io.h>
  17
  18#define XWT_CSR0_WRS_MASK       0x00000008 /* Reset status Mask */
  19#define XWT_CSR0_WDS_MASK       0x00000004 /* Timer state Mask */
  20#define XWT_CSR0_EWDT1_MASK     0x00000002 /* Enable bit 1 Mask*/
  21#define XWT_CSRX_EWDT2_MASK     0x00000001 /* Enable bit 2 Mask */
  22
  23struct watchdog_regs {
  24        u32 twcsr0; /* 0x0 */
  25        u32 twcsr1; /* 0x4 */
  26        u32 tbr; /* 0x8 */
  27};
  28
  29struct xlnx_wdt_plat {
  30        bool enable_once;
  31        struct watchdog_regs *regs;
  32};
  33
  34static int xlnx_wdt_reset(struct udevice *dev)
  35{
  36        u32 reg;
  37        struct xlnx_wdt_plat *plat = dev_get_plat(dev);
  38
  39        debug("%s ", __func__);
  40
  41        /* Read the current contents of TCSR0 */
  42        reg = readl(&plat->regs->twcsr0);
  43
  44        /* Clear the watchdog WDS bit */
  45        if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
  46                writel(reg | XWT_CSR0_WDS_MASK, &plat->regs->twcsr0);
  47
  48        return 0;
  49}
  50
  51static int xlnx_wdt_stop(struct udevice *dev)
  52{
  53        u32 reg;
  54        struct xlnx_wdt_plat *plat = dev_get_plat(dev);
  55
  56        if (plat->enable_once) {
  57                debug("Can't stop Xilinx watchdog.\n");
  58                return -EBUSY;
  59        }
  60
  61        /* Read the current contents of TCSR0 */
  62        reg = readl(&plat->regs->twcsr0);
  63
  64        writel(reg & ~XWT_CSR0_EWDT1_MASK, &plat->regs->twcsr0);
  65        writel(~XWT_CSRX_EWDT2_MASK, &plat->regs->twcsr1);
  66
  67        debug("Watchdog disabled!\n");
  68
  69        return 0;
  70}
  71
  72static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  73{
  74        struct xlnx_wdt_plat *plat = dev_get_plat(dev);
  75
  76        debug("%s:\n", __func__);
  77
  78        writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
  79               &plat->regs->twcsr0);
  80
  81        writel(XWT_CSRX_EWDT2_MASK, &plat->regs->twcsr1);
  82
  83        return 0;
  84}
  85
  86static int xlnx_wdt_probe(struct udevice *dev)
  87{
  88        debug("%s: Probing wdt%u\n", __func__, dev_seq(dev));
  89
  90        return 0;
  91}
  92
  93static int xlnx_wdt_of_to_plat(struct udevice *dev)
  94{
  95        struct xlnx_wdt_plat *plat = dev_get_plat(dev);
  96
  97        plat->regs = (struct watchdog_regs *)dev_read_addr(dev);
  98        if (IS_ERR(plat->regs))
  99                return PTR_ERR(plat->regs);
 100
 101        plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
 102                                                 0);
 103
 104        debug("%s: wdt-enable-once %d\n", __func__, plat->enable_once);
 105
 106        return 0;
 107}
 108
 109static const struct wdt_ops xlnx_wdt_ops = {
 110        .start = xlnx_wdt_start,
 111        .reset = xlnx_wdt_reset,
 112        .stop = xlnx_wdt_stop,
 113};
 114
 115static const struct udevice_id xlnx_wdt_ids[] = {
 116        { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
 117        { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
 118        {},
 119};
 120
 121U_BOOT_DRIVER(xlnx_wdt) = {
 122        .name = "xlnx_wdt",
 123        .id = UCLASS_WDT,
 124        .of_match = xlnx_wdt_ids,
 125        .probe = xlnx_wdt_probe,
 126        .plat_auto      = sizeof(struct xlnx_wdt_plat),
 127        .of_to_plat = xlnx_wdt_of_to_plat,
 128        .ops = &xlnx_wdt_ops,
 129};
 130