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6#ifndef __ASM_ACPI_S3_H__
7#define __ASM_ACPI_S3_H__
8
9#define WAKEUP_BASE 0x600
10
11
12#define WAK_STS (1 << 15)
13#define PCIEXPWAK_STS (1 << 14)
14#define RTC_STS (1 << 10)
15#define SLPBTN_STS (1 << 9)
16#define PWRBTN_STS (1 << 8)
17#define GBL_STS (1 << 5)
18#define BM_STS (1 << 4)
19#define TMR_STS (1 << 0)
20
21
22#define SLP_EN (1 << 13)
23#define SLP_TYP_SHIFT 10
24#define SLP_TYP (7 << SLP_TYP_SHIFT)
25#define SLP_TYP_S0 0
26#define SLP_TYP_S1 1
27#define SLP_TYP_S3 5
28#define SLP_TYP_S4 6
29#define SLP_TYP_S5 7
30
31
32#define RTC_EN BIT(10)
33#define PWRBTN_EN BIT(8)
34
35
36#define S3_RESERVE_SIZE 0x1000
37
38#ifndef __ASSEMBLY__
39
40extern char __wakeup[];
41extern int __wakeup_size;
42
43enum acpi_sleep_state {
44 ACPI_S0,
45 ACPI_S1,
46 ACPI_S2,
47 ACPI_S3,
48 ACPI_S4,
49 ACPI_S5,
50};
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58static inline char *acpi_ss_string(enum acpi_sleep_state state)
59{
60 char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"};
61
62 return ss_string[state];
63}
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72static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
73{
74 switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
75 case SLP_TYP_S0:
76 return ACPI_S0;
77 case SLP_TYP_S1:
78 return ACPI_S1;
79 case SLP_TYP_S3:
80 return ACPI_S3;
81 case SLP_TYP_S4:
82 return ACPI_S4;
83 case SLP_TYP_S5:
84 return ACPI_S5;
85 }
86
87 return -EINVAL;
88}
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98enum acpi_sleep_state chipset_prev_sleep_state(void);
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106void chipset_clear_sleep_state(void);
107
108struct acpi_fadt;
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117void acpi_resume(struct acpi_fadt *fadt);
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130int acpi_s3_reserve(void);
131
132#endif
133
134#endif
135