LXR uboot/include/configs/db-mv784mp-gp.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
   4 */
   5
   6#ifndef _CONFIG_DB_MV7846MP_GP_H
   7#define _CONFIG_DB_MV7846MP_GP_H
   8
   9/*
  10 * High Level Configuration Options (easy to change)
  11 */
  12#define CONFIG_DB_784MP_GP              /* Board target name for DDR training */
  13
  14/*
  15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  16 * for DDR ECC byte filling in the SPL before loading the main
  17 * U-Boot into it.
  18 */
  19
  20/* I2C */
  21#define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  22
  23/* USB/EHCI configuration */
  24#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  25
  26/* Environment in SPI NOR flash */
  27
  28#define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  29
  30/* SATA support */
  31#define CONFIG_SYS_SATA_MAX_DEVICE      2
  32#define CONFIG_LBA48
  33
  34/* PCIe support */
  35#ifndef CONFIG_SPL_BUILD
  36#define CONFIG_PCI_SCAN_SHOW
  37#endif
  38
  39/* NAND */
  40
  41/*
  42 * mv-common.h should be defined after CMD configs since it used them
  43 * to enable certain macros
  44 */
  45#include "mv-common.h"
  46
  47/*
  48 * Memory layout while starting into the bin_hdr via the
  49 * BootROM:
  50 *
  51 * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  52 * 0x4000.4030                  bin_hdr start address
  53 * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  54 * 0x4007.fffc                  BootROM stack top
  55 *
  56 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  57 * L2 cache thus cannot be used.
  58 */
  59
  60/* SPL */
  61/* Defines for SPL */
  62#define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  63
  64#define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  65#define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  66
  67#ifdef CONFIG_SPL_BUILD
  68#define CONFIG_SYS_MALLOC_SIMPLE
  69#endif
  70
  71#define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
  72#define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
  73
  74/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  75#define CONFIG_SPD_EEPROM               0x4e
  76#define CONFIG_BOARD_ECC_SUPPORT        /* this board supports ECC */
  77
  78#endif /* _CONFIG_DB_MV7846MP_GP_H */
  79