1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuration settings for the EXYNOS 78x0 based boards. 4 * 5 * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) 6 * based on include/exynos7420-common.h 7 * Copyright (C) 2016 Samsung Electronics 8 * Thomas Abraham <thomas.ab@samsung.com> 9 */ 10 11#ifndef __CONFIG_EXYNOS78x0_COMMON_H 12#define __CONFIG_EXYNOS78x0_COMMON_H 13 14/* High Level Configuration Options */ 15#define CONFIG_SAMSUNG /* in a SAMSUNG core */ 16#define CONFIG_S5P 17 18#include <asm/arch/cpu.h> /* get chip and board defs */ 19#include <linux/sizes.h> 20 21/* Miscellaneous configurable options */ 22#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 23#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 24 25/* Boot Argument Buffer Size */ 26#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 27 28/* Timer input clock frequency */ 29#define COUNTER_FREQUENCY 26000000 30 31/* Device Tree */ 32#define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte" 33 34#define CPU_RELEASE_ADDR secondary_boot_addr 35 36#define CONFIG_SYS_BAUDRATE_TABLE \ 37 {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} 38 39#define CONFIG_BOARD_COMMON 40 41#define CONFIG_SYS_SDRAM_BASE 0x40000000 42#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE) 43/* DRAM Memory Banks */ 44#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ 45#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 46#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 47#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 48#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 49#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 50#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 51#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 52#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 53#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 54#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 55#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 56#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 57#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 58#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 59#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 60#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 61#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) 62#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE 63#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) 64#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE 65#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) 66#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE 67#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) 68#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE 69 70#define CONFIG_DEBUG_UART_CLOCK 132710400 71 72#define CONFIG_PREBOOT \ 73"echo Read pressed buttons status;" \ 74"KEY_VOLUMEUP=gpa20;" \ 75"KEY_HOME=gpa17;" \ 76"KEY_VOLUMEDOWN=gpa21;" \ 77"KEY_POWER=gpa00;" \ 78"PRESSED=0;" \ 79"RELEASED=1;" \ 80"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \ 81"else setenv VOLUME_UP $RELEASED; fi;" \ 82"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \ 83"else setenv VOLUME_DOWN $RELEASED; fi;" \ 84"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \ 85"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;" 86 87#ifndef MEM_LAYOUT_ENV_SETTINGS 88#define MEM_LAYOUT_ENV_SETTINGS \ 89 "bootm_size=0x10000000\0" \ 90 "bootm_low=0x40000000\0" 91#endif 92 93#ifndef EXYNOS_DEVICE_SETTINGS 94#define EXYNOS_DEVICE_SETTINGS \ 95 "stdin=serial\0" \ 96 "stdout=serial\0" \ 97 "stderr=serial\0" 98#endif 99 100#ifndef EXYNOS_FDTFILE_SETTING 101#define EXYNOS_FDTFILE_SETTING 102#endif 103 104#define EXTRA_ENV_SETTINGS \ 105 EXYNOS_DEVICE_SETTINGS \ 106 EXYNOS_FDTFILE_SETTING \ 107 MEM_LAYOUT_ENV_SETTINGS 108 109#define CONFIG_EXTRA_ENV_SETTINGS \ 110 EXTRA_ENV_SETTINGS 111 112#endif /* __CONFIG_EXYNOS78x0_COMMON_H */ 113