1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2019 NXP 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12#define CONFIG_SYS_FSL_CLK 13 14#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 15#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 16 17#define CONFIG_SYS_CLK_FREQ 100000000 18 19/* 20 * DDR: 800 MHz ( 1600 MT/s data rate ) 21 */ 22 23#define DDR_SDRAM_CFG 0x470c0008 24#define DDR_CS0_BNDS 0x008000bf 25#define DDR_CS0_CONFIG 0x80014302 26#define DDR_TIMING_CFG_0 0x50550004 27#define DDR_TIMING_CFG_1 0xbcb38c56 28#define DDR_TIMING_CFG_2 0x0040d120 29#define DDR_TIMING_CFG_3 0x010e1000 30#define DDR_TIMING_CFG_4 0x00000001 31#define DDR_TIMING_CFG_5 0x03401400 32#define DDR_SDRAM_CFG_2 0x00401010 33#define DDR_SDRAM_MODE 0x00061c60 34#define DDR_SDRAM_MODE_2 0x00180000 35#define DDR_SDRAM_INTERVAL 0x18600618 36#define DDR_DDR_WRLVL_CNTL 0x8655f605 37#define DDR_DDR_WRLVL_CNTL_2 0x05060607 38#define DDR_DDR_WRLVL_CNTL_3 0x05050505 39#define DDR_DDR_CDR1 0x80040000 40#define DDR_DDR_CDR2 0x00000001 41#define DDR_SDRAM_CLK_CNTL 0x02000000 42#define DDR_DDR_ZQ_CNTL 0x89080600 43#define DDR_CS0_CONFIG_2 0 44#define DDR_SDRAM_CFG_MEM_EN 0x80000000 45#define SDRAM_CFG2_D_INIT 0x00000010 46#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 47#define SDRAM_CFG2_FRC_SR 0x80000000 48#define SDRAM_CFG_BI 0x00000001 49 50#ifdef CONFIG_SD_BOOT 51#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 52 53#define CONFIG_SPL_MAX_SIZE 0x1a000 54#define CONFIG_SPL_STACK 0x1001d000 55#define CONFIG_SPL_PAD_TO 0x1c000 56 57#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 58 CONFIG_SYS_MONITOR_LEN) 59#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 60#define CONFIG_SPL_BSS_START_ADDR 0x80100000 61#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 62#define CONFIG_SYS_MONITOR_LEN 0x80000 63#endif 64 65#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 67 68#define CONFIG_CHIP_SELECTS_PER_CTRL 4 69 70/* 71 * Serial Port 72 */ 73#define CONFIG_SYS_NS16550_SERIAL 74#define CONFIG_SYS_NS16550_REG_SIZE 1 75#define CONFIG_SYS_NS16550_CLK get_serial_clock() 76 77/* 78 * I2C 79 */ 80 81/* EEPROM */ 82#define CONFIG_SYS_I2C_EEPROM_NXID 83#define CONFIG_SYS_EEPROM_BUS_NUM 0 84 85/* 86 * MMC 87 */ 88 89/* SATA */ 90#define CONFIG_SCSI_AHCI_PLAT 91#ifndef PCI_DEVICE_ID_FREESCALE_AHCI 92#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 93#endif 94#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 95 PCI_DEVICE_ID_FREESCALE_AHCI} 96 97#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 98#define CONFIG_SYS_SCSI_MAX_LUN 1 99#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 100 CONFIG_SYS_SCSI_MAX_LUN) 101 102/* SPI */ 103#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 104#define CONFIG_SPI_FLASH_SPANSION 105#endif 106 107/* 108 * eTSEC 109 */ 110 111#ifdef CONFIG_TSEC_ENET 112#define CONFIG_MII_DEFAULT_TSEC 1 113#define CONFIG_TSEC1 1 114#define CONFIG_TSEC1_NAME "eTSEC1" 115#define CONFIG_TSEC2 1 116#define CONFIG_TSEC2_NAME "eTSEC2" 117 118#define TSEC1_PHY_ADDR 1 119#define TSEC2_PHY_ADDR 3 120 121#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 122#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 123 124#define TSEC1_PHYIDX 0 125#define TSEC2_PHYIDX 0 126 127#define CONFIG_ETHPRIME "eTSEC2" 128 129#define CONFIG_HAS_ETH0 130#define CONFIG_HAS_ETH1 131#define CONFIG_HAS_ETH2 132#endif 133 134/* PCIe */ 135#define CONFIG_PCIE1 /* PCIE controler 1 */ 136#define CONFIG_PCIE2 /* PCIE controler 2 */ 137 138#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 139 140#ifdef CONFIG_PCI 141#define CONFIG_PCI_SCAN_SHOW 142#endif 143 144#define CONFIG_PEN_ADDR_BIG_ENDIAN 145#define CONFIG_LAYERSCAPE_NS_ACCESS 146#define CONFIG_SMP_PEN_ADDR 0x01ee0200 147#define COUNTER_FREQUENCY 12500000 148 149#define CONFIG_HWCONFIG 150#define HWCONFIG_BUFFER_SIZE 256 151 152#define CONFIG_FSL_DEVICE_DISABLE 153 154#define CONFIG_EXTRA_ENV_SETTINGS \ 155 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 156"initrd_high=0xffffffff\0" 157 158/* 159 * Miscellaneous configurable options 160 */ 161#define CONFIG_SYS_BOOTMAPSZ (256 << 20) 162 163#define CONFIG_LS102XA_STREAM_ID 164 165#define CONFIG_SYS_INIT_SP_OFFSET \ 166 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 167#define CONFIG_SYS_INIT_SP_ADDR \ 168 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 169 170#ifdef CONFIG_SPL_BUILD 171#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 172#else 173/* start of monitor */ 174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 175#endif 176 177#define CONFIG_OF_BOARD_SETUP 178#define CONFIG_OF_STDOUT_VIA_ALIAS 179 180#include <asm/fsl_secure_boot.h> 181 182#endif 183