1
2
3
4
5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
12#define CONFIG_SYS_FSL_CLK
13
14#define CONFIG_DEEP_SLEEP
15
16#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
17#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
18
19#define CONFIG_SYS_CLK_FREQ 100000000
20
21#define DDR_SDRAM_CFG 0x470c0008
22#define DDR_CS0_BNDS 0x008000bf
23#define DDR_CS0_CONFIG 0x80014302
24#define DDR_TIMING_CFG_0 0x50550004
25#define DDR_TIMING_CFG_1 0xbcb38c56
26#define DDR_TIMING_CFG_2 0x0040d120
27#define DDR_TIMING_CFG_3 0x010e1000
28#define DDR_TIMING_CFG_4 0x00000001
29#define DDR_TIMING_CFG_5 0x03401400
30#define DDR_SDRAM_CFG_2 0x00401010
31#define DDR_SDRAM_MODE 0x00061c60
32#define DDR_SDRAM_MODE_2 0x00180000
33#define DDR_SDRAM_INTERVAL 0x18600618
34#define DDR_DDR_WRLVL_CNTL 0x8655f605
35#define DDR_DDR_WRLVL_CNTL_2 0x05060607
36#define DDR_DDR_WRLVL_CNTL_3 0x05050505
37#define DDR_DDR_CDR1 0x80040000
38#define DDR_DDR_CDR2 0x00000001
39#define DDR_SDRAM_CLK_CNTL 0x02000000
40#define DDR_DDR_ZQ_CNTL 0x89080600
41#define DDR_CS0_CONFIG_2 0
42#define DDR_SDRAM_CFG_MEM_EN 0x80000000
43#define SDRAM_CFG2_D_INIT 0x00000010
44#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
45#define SDRAM_CFG2_FRC_SR 0x80000000
46#define SDRAM_CFG_BI 0x00000001
47
48#ifdef CONFIG_SD_BOOT
49#ifdef CONFIG_NXP_ESBC
50
51
52
53
54#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
55#endif
56
57#define CONFIG_SPL_MAX_SIZE 0x1a000
58#define CONFIG_SPL_STACK 0x1001d000
59#define CONFIG_SPL_PAD_TO 0x1c000
60
61#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
62 CONFIG_SYS_MONITOR_LEN)
63#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
64#define CONFIG_SPL_BSS_START_ADDR 0x80100000
65#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
66
67#ifdef CONFIG_U_BOOT_HDR_SIZE
68
69
70
71
72
73
74#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
75#else
76#define CONFIG_SYS_MONITOR_LEN 0x100000
77#endif
78#endif
79
80#define PHYS_SDRAM 0x80000000
81#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
82
83#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
84#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85
86#define CONFIG_CHIP_SELECTS_PER_CTRL 4
87
88
89
90
91#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
92#define CONFIG_FSL_IFC
93#define CONFIG_SYS_FLASH_BASE 0x60000000
94#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
95
96#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
97#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
98 CSPR_PORT_SIZE_16 | \
99 CSPR_MSEL_NOR | \
100 CSPR_V)
101#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
102
103
104#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
105 CSOR_NOR_TRHZ_80)
106#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
107 FTIM0_NOR_TEADC(0x5) | \
108 FTIM0_NOR_TAVDS(0x0) | \
109 FTIM0_NOR_TEAHC(0x5))
110#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
111 FTIM1_NOR_TRAD_NOR(0x1A) | \
112 FTIM1_NOR_TSEQRAD_NOR(0x13))
113#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
114 FTIM2_NOR_TCH(0x4) | \
115 FTIM2_NOR_TWP(0x1c) | \
116 FTIM2_NOR_TWPH(0x0e))
117#define CONFIG_SYS_NOR_FTIM3 0
118
119#define CONFIG_SYS_FLASH_QUIET_TEST
120#define CONFIG_FLASH_SHOW_PROGRESS 45
121
122#define CONFIG_SYS_MAX_FLASH_BANKS 1
123#define CONFIG_SYS_MAX_FLASH_SECT 1024
124#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
125#define CONFIG_SYS_FLASH_WRITE_TOUT 500
126
127#define CONFIG_SYS_FLASH_EMPTY_INFO
128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
129
130#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
131#define CONFIG_SYS_WRITE_SWAPPED_DATA
132#endif
133
134
135
136#define CONFIG_SYS_CPLD_BASE 0x7fb00000
137#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
138
139#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
140#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
141 CSPR_PORT_SIZE_8 | \
142 CSPR_MSEL_GPCM | \
143 CSPR_V)
144#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
145#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
146 CSOR_NOR_NOR_MODE_AVD_NOR | \
147 CSOR_NOR_TRHZ_80)
148
149
150#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
151 FTIM0_GPCM_TEADC(0xf) | \
152 FTIM0_GPCM_TEAHC(0xf))
153#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
154 FTIM1_GPCM_TRAD(0x3f))
155#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
156 FTIM2_GPCM_TCH(0xf) | \
157 FTIM2_GPCM_TWP(0xff))
158#define CONFIG_SYS_FPGA_FTIM3 0x0
159#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
160#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
161#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
162#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
163#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
164#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
165#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
166#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
167#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
168#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
169#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
170#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
171#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
172#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
173#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
174#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
175
176
177
178
179#ifdef CONFIG_LPUART
180#define CONFIG_LPUART_32B_REG
181#else
182#define CONFIG_SYS_NS16550_SERIAL
183#ifndef CONFIG_DM_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#endif
186#define CONFIG_SYS_NS16550_CLK get_serial_clock()
187#endif
188
189
190
191
192
193
194#ifdef CONFIG_DM_GPIO
195#ifndef CONFIG_MPC8XXX_GPIO
196#define CONFIG_MPC8XXX_GPIO
197#endif
198#endif
199
200
201#define CONFIG_SYS_I2C_EEPROM_NXID
202#define CONFIG_SYS_EEPROM_BUS_NUM 1
203
204
205
206
207
208
209
210
211#ifdef CONFIG_VIDEO_FSL_DCU_FB
212#define CONFIG_VIDEO_LOGO
213#define CONFIG_VIDEO_BMP_LOGO
214
215#define CONFIG_FSL_DCU_SII9022A
216#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
217#define CONFIG_SYS_I2C_DVI_ADDR 0x39
218#endif
219
220
221
222
223
224#ifdef CONFIG_TSEC_ENET
225#define CONFIG_ETHPRIME "ethernet@2d10000"
226#endif
227
228
229#define CONFIG_PCIE1
230#define CONFIG_PCIE2
231
232#ifdef CONFIG_PCI
233#define CONFIG_PCI_SCAN_SHOW
234#endif
235
236#define CONFIG_PEN_ADDR_BIG_ENDIAN
237#define CONFIG_LAYERSCAPE_NS_ACCESS
238#define CONFIG_SMP_PEN_ADDR 0x01ee0200
239#define COUNTER_FREQUENCY 12500000
240
241#define CONFIG_HWCONFIG
242#define HWCONFIG_BUFFER_SIZE 256
243
244#define CONFIG_FSL_DEVICE_DISABLE
245
246#define BOOT_TARGET_DEVICES(func) \
247 func(MMC, mmc, 0) \
248 func(USB, usb, 0) \
249 func(DHCP, dhcp, na)
250#include <config_distro_bootcmd.h>
251
252#ifdef CONFIG_LPUART
253#define CONFIG_EXTRA_ENV_SETTINGS \
254 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
255 "cma=64M@0x0-0xb0000000\0" \
256 "initrd_high=0xffffffff\0" \
257 "fdt_addr=0x64f00000\0" \
258 "kernel_addr=0x65000000\0" \
259 "scriptaddr=0x80000000\0" \
260 "scripthdraddr=0x80080000\0" \
261 "fdtheader_addr_r=0x80100000\0" \
262 "kernelheader_addr_r=0x80200000\0" \
263 "kernel_addr_r=0x81000000\0" \
264 "fdt_addr_r=0x90000000\0" \
265 "ramdisk_addr_r=0xa0000000\0" \
266 "load_addr=0xa0000000\0" \
267 "kernel_size=0x2800000\0" \
268 "kernel_addr_sd=0x8000\0" \
269 "kernel_size_sd=0x14000\0" \
270 "othbootargs=cma=64M@0x0-0xb0000000\0" \
271 BOOTENV \
272 "boot_scripts=ls1021atwr_boot.scr\0" \
273 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
274 "scan_dev_for_boot_part=" \
275 "part list ${devtype} ${devnum} devplist; " \
276 "env exists devplist || setenv devplist 1; " \
277 "for distro_bootpart in ${devplist}; do " \
278 "if fstype ${devtype} " \
279 "${devnum}:${distro_bootpart} " \
280 "bootfstype; then " \
281 "run scan_dev_for_boot; " \
282 "fi; " \
283 "done\0" \
284 "scan_dev_for_boot=" \
285 "echo Scanning ${devtype} " \
286 "${devnum}:${distro_bootpart}...; " \
287 "for prefix in ${boot_prefixes}; do " \
288 "run scan_dev_for_scripts; " \
289 "done;" \
290 "\0" \
291 "boot_a_script=" \
292 "load ${devtype} ${devnum}:${distro_bootpart} " \
293 "${scriptaddr} ${prefix}${script}; " \
294 "env exists secureboot && load ${devtype} " \
295 "${devnum}:${distro_bootpart} " \
296 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
297 "env exists secureboot " \
298 "&& esbc_validate ${scripthdraddr};" \
299 "source ${scriptaddr}\0" \
300 "installer=load mmc 0:2 $load_addr " \
301 "/flex_installer_arm32.itb; " \
302 "bootm $load_addr#ls1021atwr\0" \
303 "qspi_bootcmd=echo Trying load from qspi..;" \
304 "sf probe && sf read $load_addr " \
305 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
306 "nor_bootcmd=echo Trying load from nor..;" \
307 "cp.b $kernel_addr $load_addr " \
308 "$kernel_size && bootm $load_addr#$board\0"
309#else
310#define CONFIG_EXTRA_ENV_SETTINGS \
311 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
312 "cma=64M@0x0-0xb0000000\0" \
313 "initrd_high=0xffffffff\0" \
314 "fdt_addr=0x64f00000\0" \
315 "kernel_addr=0x61000000\0" \
316 "kernelheader_addr=0x60800000\0" \
317 "scriptaddr=0x80000000\0" \
318 "scripthdraddr=0x80080000\0" \
319 "fdtheader_addr_r=0x80100000\0" \
320 "kernelheader_addr_r=0x80200000\0" \
321 "kernel_addr_r=0x81000000\0" \
322 "kernelheader_size=0x40000\0" \
323 "fdt_addr_r=0x90000000\0" \
324 "ramdisk_addr_r=0xa0000000\0" \
325 "load_addr=0xa0000000\0" \
326 "kernel_size=0x2800000\0" \
327 "kernel_addr_sd=0x8000\0" \
328 "kernel_size_sd=0x14000\0" \
329 "kernelhdr_addr_sd=0x4000\0" \
330 "kernelhdr_size_sd=0x10\0" \
331 "othbootargs=cma=64M@0x0-0xb0000000\0" \
332 BOOTENV \
333 "boot_scripts=ls1021atwr_boot.scr\0" \
334 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
335 "scan_dev_for_boot_part=" \
336 "part list ${devtype} ${devnum} devplist; " \
337 "env exists devplist || setenv devplist 1; " \
338 "for distro_bootpart in ${devplist}; do " \
339 "if fstype ${devtype} " \
340 "${devnum}:${distro_bootpart} " \
341 "bootfstype; then " \
342 "run scan_dev_for_boot; " \
343 "fi; " \
344 "done\0" \
345 "scan_dev_for_boot=" \
346 "echo Scanning ${devtype} " \
347 "${devnum}:${distro_bootpart}...; " \
348 "for prefix in ${boot_prefixes}; do " \
349 "run scan_dev_for_scripts; " \
350 "done;" \
351 "\0" \
352 "boot_a_script=" \
353 "load ${devtype} ${devnum}:${distro_bootpart} " \
354 "${scriptaddr} ${prefix}${script}; " \
355 "env exists secureboot && load ${devtype} " \
356 "${devnum}:${distro_bootpart} " \
357 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
358 "&& esbc_validate ${scripthdraddr};" \
359 "source ${scriptaddr}\0" \
360 "qspi_bootcmd=echo Trying load from qspi..;" \
361 "sf probe && sf read $load_addr " \
362 "$kernel_addr $kernel_size; env exists secureboot " \
363 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
364 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
365 "bootm $load_addr#$board\0" \
366 "nor_bootcmd=echo Trying load from nor..;" \
367 "cp.b $kernel_addr $load_addr " \
368 "$kernel_size; env exists secureboot " \
369 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
370 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
371 "bootm $load_addr#$board\0" \
372 "sd_bootcmd=echo Trying load from SD ..;" \
373 "mmcinfo && mmc read $load_addr " \
374 "$kernel_addr_sd $kernel_size_sd && " \
375 "env exists secureboot && mmc read $kernelheader_addr_r " \
376 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
377 " && esbc_validate ${kernelheader_addr_r};" \
378 "bootm $load_addr#$board\0"
379#endif
380
381#undef CONFIG_BOOTCOMMAND
382#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
383#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
384 "env exists secureboot && esbc_halt"
385#elif defined(CONFIG_SD_BOOT)
386#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
387 "env exists secureboot && esbc_halt;"
388#else
389#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
390 "env exists secureboot && esbc_halt;"
391#endif
392
393
394
395
396#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
397
398#define CONFIG_LS102XA_STREAM_ID
399
400#define CONFIG_SYS_INIT_SP_OFFSET \
401 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
402#define CONFIG_SYS_INIT_SP_ADDR \
403 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
404
405#ifdef CONFIG_SPL_BUILD
406#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
407#else
408#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
409#endif
410
411
412
413
414
415#include <asm/fsl_secure_boot.h>
416#define CONFIG_SYS_BOOTM_LEN (64 << 20)
417
418#endif
419
