LXR uboot/include/dp83848.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * DP83848 ethernet Physical layer
   4 *
   5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   6 *
   7 */
   8
   9
  10/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
  11
  12#define DP83848_CTL_REG         0x0     /* Basic Mode Control Reg */
  13#define DP83848_STAT_REG                0x1     /* Basic Mode Status Reg */
  14#define DP83848_PHYID1_REG              0x2     /* PHY Idendifier Reg 1 */
  15#define DP83848_PHYID2_REG              0x3     /* PHY Idendifier Reg 2 */
  16#define DP83848_ANA_REG                 0x4     /* Auto_Neg Advt Reg  */
  17#define DP83848_ANLPA_REG               0x5     /* Auto_neg Link Partner Ability Reg */
  18#define DP83848_ANE_REG                 0x6     /* Auto-neg Expansion Reg  */
  19#define DP83848_PHY_STAT_REG            0x10    /* PHY Status Register  */
  20#define DP83848_PHY_INTR_CTRL_REG       0x11    /* PHY Interrupt Control Register */
  21#define DP83848_PHY_CTRL_REG            0x19    /* PHY Status Register  */
  22
  23/*--Bit definitions: DP83848_CTL_REG */
  24#define DP83848_RESET           (1 << 15)  /* 1= S/W Reset */
  25#define DP83848_LOOPBACK        (1 << 14)  /* 1=loopback Enabled */
  26#define DP83848_SPEED_SELECT    (1 << 13)
  27#define DP83848_AUTONEG         (1 << 12)
  28#define DP83848_POWER_DOWN      (1 << 11)
  29#define DP83848_ISOLATE         (1 << 10)
  30#define DP83848_RESTART_AUTONEG (1 << 9)
  31#define DP83848_DUPLEX_MODE     (1 << 8)
  32#define DP83848_COLLISION_TEST  (1 << 7)
  33
  34/*--Bit definitions: DP83848_STAT_REG */
  35#define DP83848_100BASE_T4      (1 << 15)
  36#define DP83848_100BASE_TX_FD   (1 << 14)
  37#define DP83848_100BASE_TX_HD   (1 << 13)
  38#define DP83848_10BASE_T_FD     (1 << 12)
  39#define DP83848_10BASE_T_HD     (1 << 11)
  40#define DP83848_MF_PREAMB_SUPPR (1 << 6)
  41#define DP83848_AUTONEG_COMP    (1 << 5)
  42#define DP83848_RMT_FAULT       (1 << 4)
  43#define DP83848_AUTONEG_ABILITY (1 << 3)
  44#define DP83848_LINK_STATUS     (1 << 2)
  45#define DP83848_JABBER_DETECT   (1 << 1)
  46#define DP83848_EXTEND_CAPAB    (1 << 0)
  47
  48/*--definitions: DP83848_PHYID1 */
  49#define DP83848_PHYID1_OUI      0x2000
  50#define DP83848_PHYID2_OUI      0x5c90
  51
  52/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
  53#define DP83848_NP              (1 << 15)
  54#define DP83848_ACK             (1 << 14)
  55#define DP83848_RF              (1 << 13)
  56#define DP83848_PAUSE           (1 << 10)
  57#define DP83848_T4              (1 << 9)
  58#define DP83848_TX_FDX          (1 << 8)
  59#define DP83848_TX_HDX          (1 << 7)
  60#define DP83848_10_FDX          (1 << 6)
  61#define DP83848_10_HDX          (1 << 5)
  62#define DP83848_AN_IEEE_802_3   0x0001
  63
  64/*--Bit definitions: DP83848_ANER */
  65#define DP83848_PDF             (1 << 4)
  66#define DP83848_LP_NP_ABLE      (1 << 3)
  67#define DP83848_NP_ABLE         (1 << 2)
  68#define DP83848_PAGE_RX         (1 << 1)
  69#define DP83848_LP_AN_ABLE      (1 << 0)
  70
  71/*--Bit definitions: DP83848_PHY_STAT */
  72#define DP83848_RX_ERR_LATCH            (1 << 13)
  73#define DP83848_POLARITY_STAT           (1 << 12)
  74#define DP83848_FALSE_CAR_SENSE         (1 << 11)
  75#define DP83848_SIG_DETECT              (1 << 10)
  76#define DP83848_DESCRAM_LOCK            (1 << 9)
  77#define DP83848_PAGE_RCV                (1 << 8)
  78#define DP83848_PHY_RMT_FAULT           (1 << 6)
  79#define DP83848_JABBER                  (1 << 5)
  80#define DP83848_AUTONEG_COMPLETE        (1 << 4)
  81#define DP83848_LOOPBACK_STAT           (1 << 3)
  82#define DP83848_DUPLEX                  (1 << 2)
  83#define DP83848_SPEED                   (1 << 1)
  84#define DP83848_LINK                    (1 << 0)
  85