uboot/include/dw_hdmi.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (c) 2015 Google, Inc
   4 * Copyright 2014 Rockchip Inc.
   5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
   6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   7 */
   8
   9#ifndef _DW_HDMI_H
  10#define _DW_HDMI_H
  11
  12#include <edid.h>
  13
  14#define HDMI_EDID_BLOCK_SIZE            128
  15
  16/* Identification Registers */
  17#define HDMI_DESIGN_ID                          0x0000
  18#define HDMI_REVISION_ID                        0x0001
  19#define HDMI_PRODUCT_ID0                        0x0002
  20#define HDMI_PRODUCT_ID1                        0x0003
  21#define HDMI_CONFIG0_ID                         0x0004
  22#define HDMI_CONFIG1_ID                         0x0005
  23#define HDMI_CONFIG2_ID                         0x0006
  24#define HDMI_CONFIG3_ID                         0x0007
  25
  26/* Interrupt Registers */
  27#define HDMI_IH_FC_STAT0                        0x0100
  28#define HDMI_IH_FC_STAT1                        0x0101
  29#define HDMI_IH_FC_STAT2                        0x0102
  30#define HDMI_IH_AS_STAT0                        0x0103
  31#define HDMI_IH_PHY_STAT0                       0x0104
  32#define HDMI_IH_I2CM_STAT0                      0x0105
  33#define HDMI_IH_CEC_STAT0                       0x0106
  34#define HDMI_IH_VP_STAT0                        0x0107
  35#define HDMI_IH_I2CMPHY_STAT0                   0x0108
  36#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
  37
  38#define HDMI_IH_MUTE_FC_STAT0                   0x0180
  39#define HDMI_IH_MUTE_FC_STAT1                   0x0181
  40#define HDMI_IH_MUTE_FC_STAT2                   0x0182
  41#define HDMI_IH_MUTE_AS_STAT0                   0x0183
  42#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
  43#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
  44#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
  45#define HDMI_IH_MUTE_VP_STAT0                   0x0187
  46#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
  47#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
  48#define HDMI_IH_MUTE                            0x01FF
  49
  50/* Video Sample Registers */
  51#define HDMI_TX_INVID0                          0x0200
  52#define HDMI_TX_INSTUFFING                      0x0201
  53#define HDMI_TX_GYDATA0                         0x0202
  54#define HDMI_TX_GYDATA1                         0x0203
  55#define HDMI_TX_RCRDATA0                        0x0204
  56#define HDMI_TX_RCRDATA1                        0x0205
  57#define HDMI_TX_BCBDATA0                        0x0206
  58#define HDMI_TX_BCBDATA1                        0x0207
  59
  60/* Video Packetizer Registers */
  61#define HDMI_VP_STATUS                          0x0800
  62#define HDMI_VP_PR_CD                           0x0801
  63#define HDMI_VP_STUFF                           0x0802
  64#define HDMI_VP_REMAP                           0x0803
  65#define HDMI_VP_CONF                            0x0804
  66#define HDMI_VP_STAT                            0x0805
  67#define HDMI_VP_INT                             0x0806
  68#define HDMI_VP_MASK                            0x0807
  69#define HDMI_VP_POL                             0x0808
  70
  71/* Frame Composer Registers */
  72#define HDMI_FC_INVIDCONF                       0x1000
  73#define HDMI_FC_INHACTV0                        0x1001
  74#define HDMI_FC_INHACTV1                        0x1002
  75#define HDMI_FC_INHBLANK0                       0x1003
  76#define HDMI_FC_INHBLANK1                       0x1004
  77#define HDMI_FC_INVACTV0                        0x1005
  78#define HDMI_FC_INVACTV1                        0x1006
  79#define HDMI_FC_INVBLANK                        0x1007
  80#define HDMI_FC_HSYNCINDELAY0                   0x1008
  81#define HDMI_FC_HSYNCINDELAY1                   0x1009
  82#define HDMI_FC_HSYNCINWIDTH0                   0x100A
  83#define HDMI_FC_HSYNCINWIDTH1                   0x100B
  84#define HDMI_FC_VSYNCINDELAY                    0x100C
  85#define HDMI_FC_VSYNCINWIDTH                    0x100D
  86#define HDMI_FC_INFREQ0                         0x100E
  87#define HDMI_FC_INFREQ1                         0x100F
  88#define HDMI_FC_INFREQ2                         0x1010
  89#define HDMI_FC_CTRLDUR                         0x1011
  90#define HDMI_FC_EXCTRLDUR                       0x1012
  91#define HDMI_FC_EXCTRLSPAC                      0x1013
  92#define HDMI_FC_CH0PREAM                        0x1014
  93#define HDMI_FC_CH1PREAM                        0x1015
  94#define HDMI_FC_CH2PREAM                        0x1016
  95#define HDMI_FC_AVICONF3                        0x1017
  96#define HDMI_FC_GCP                             0x1018
  97#define HDMI_FC_AVICONF0                        0x1019
  98#define HDMI_FC_AVICONF1                        0x101A
  99#define HDMI_FC_AVICONF2                        0x101B
 100#define HDMI_FC_AVIVID                          0x101C
 101#define HDMI_FC_AVIETB0                         0x101D
 102#define HDMI_FC_AVIETB1                         0x101E
 103#define HDMI_FC_AVISBB0                         0x101F
 104#define HDMI_FC_AVISBB1                         0x1020
 105#define HDMI_FC_AVIELB0                         0x1021
 106#define HDMI_FC_AVIELB1                         0x1022
 107#define HDMI_FC_AVISRB0                         0x1023
 108#define HDMI_FC_AVISRB1                         0x1024
 109#define HDMI_FC_AUDICONF0                       0x1025
 110#define HDMI_FC_AUDICONF1                       0x1026
 111#define HDMI_FC_AUDICONF2                       0x1027
 112#define HDMI_FC_AUDICONF3                       0x1028
 113#define HDMI_FC_VSDIEEEID0                      0x1029
 114#define HDMI_FC_VSDSIZE                         0x102A
 115
 116/* HDMI Source PHY Registers */
 117#define HDMI_PHY_CONF0                          0x3000
 118#define HDMI_PHY_TST0                           0x3001
 119#define HDMI_PHY_TST1                           0x3002
 120#define HDMI_PHY_TST2                           0x3003
 121#define HDMI_PHY_STAT0                          0x3004
 122#define HDMI_PHY_INT0                           0x3005
 123#define HDMI_PHY_MASK0                          0x3006
 124#define HDMI_PHY_POL0                           0x3007
 125
 126/* HDMI Master PHY Registers */
 127#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
 128#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
 129#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
 130#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
 131#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
 132#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
 133#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
 134#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
 135#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
 136#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
 137#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
 138#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
 139#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
 140#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
 141#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
 142#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
 143#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
 144#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
 145#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
 146
 147/* Audio Sampler Registers */
 148#define HDMI_AUD_CONF0                          0x3100
 149#define HDMI_AUD_CONF1                          0x3101
 150#define HDMI_AUD_INT                            0x3102
 151#define HDMI_AUD_CONF2                          0x3103
 152#define HDMI_AUD_INT1                           0x3104
 153#define HDMI_AUD_N1                             0x3200
 154#define HDMI_AUD_N2                             0x3201
 155#define HDMI_AUD_N3                             0x3202
 156#define HDMI_AUD_CTS1                           0x3203
 157#define HDMI_AUD_CTS2                           0x3204
 158#define HDMI_AUD_CTS3                           0x3205
 159#define HDMI_AUD_INPUTCLKFS                     0x3206
 160#define HDMI_AUD_SPDIFINT                       0x3302
 161#define HDMI_AUD_CONF0_HBR                      0x3400
 162#define HDMI_AUD_HBR_STATUS                     0x3401
 163#define HDMI_AUD_HBR_INT                        0x3402
 164#define HDMI_AUD_HBR_POL                        0x3403
 165#define HDMI_AUD_HBR_MASK                       0x3404
 166
 167/* Main Controller Registers */
 168#define HDMI_MC_SFRDIV                          0x4000
 169#define HDMI_MC_CLKDIS                          0x4001
 170#define HDMI_MC_SWRSTZ                          0x4002
 171#define HDMI_MC_OPCTRL                          0x4003
 172#define HDMI_MC_FLOWCTRL                        0x4004
 173#define HDMI_MC_PHYRSTZ                         0x4005
 174#define HDMI_MC_LOCKONCLOCK                     0x4006
 175#define HDMI_MC_HEACPHY_RST                     0x4007
 176
 177/* Color Space  Converter Registers */
 178#define HDMI_CSC_CFG                            0x4100
 179#define HDMI_CSC_SCALE                          0x4101
 180#define HDMI_CSC_COEF_A1_MSB                    0x4102
 181#define HDMI_CSC_COEF_A1_LSB                    0x4103
 182#define HDMI_CSC_COEF_A2_MSB                    0x4104
 183#define HDMI_CSC_COEF_A2_LSB                    0x4105
 184#define HDMI_CSC_COEF_A3_MSB                    0x4106
 185#define HDMI_CSC_COEF_A3_LSB                    0x4107
 186#define HDMI_CSC_COEF_A4_MSB                    0x4108
 187#define HDMI_CSC_COEF_A4_LSB                    0x4109
 188#define HDMI_CSC_COEF_B1_MSB                    0x410A
 189#define HDMI_CSC_COEF_B1_LSB                    0x410B
 190#define HDMI_CSC_COEF_B2_MSB                    0x410C
 191#define HDMI_CSC_COEF_B2_LSB                    0x410D
 192#define HDMI_CSC_COEF_B3_MSB                    0x410E
 193#define HDMI_CSC_COEF_B3_LSB                    0x410F
 194#define HDMI_CSC_COEF_B4_MSB                    0x4110
 195#define HDMI_CSC_COEF_B4_LSB                    0x4111
 196#define HDMI_CSC_COEF_C1_MSB                    0x4112
 197#define HDMI_CSC_COEF_C1_LSB                    0x4113
 198#define HDMI_CSC_COEF_C2_MSB                    0x4114
 199#define HDMI_CSC_COEF_C2_LSB                    0x4115
 200#define HDMI_CSC_COEF_C3_MSB                    0x4116
 201#define HDMI_CSC_COEF_C3_LSB                    0x4117
 202#define HDMI_CSC_COEF_C4_MSB                    0x4118
 203#define HDMI_CSC_COEF_C4_LSB                    0x4119
 204
 205/* I2C Master Registers (E-DDC) */
 206#define HDMI_I2CM_SLAVE                         0x7E00
 207#define HDMI_I2CM_ADDRESS                       0x7E01
 208#define HDMI_I2CM_DATAO                         0x7E02
 209#define HDMI_I2CM_DATAI                         0x7E03
 210#define HDMI_I2CM_OPERATION                     0x7E04
 211#define HDMI_I2CM_INT                           0x7E05
 212#define HDMI_I2CM_CTLINT                        0x7E06
 213#define HDMI_I2CM_DIV                           0x7E07
 214#define HDMI_I2CM_SEGADDR                       0x7E08
 215#define HDMI_I2CM_SOFTRSTZ                      0x7E09
 216#define HDMI_I2CM_SEGPTR                        0x7E0A
 217#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
 218#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
 219#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
 220#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
 221#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
 222#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
 223#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
 224#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
 225#define HDMI_I2CM_BUF0                          0x7E20
 226
 227enum {
 228        /* HDMI PHY registers define */
 229        PHY_OPMODE_PLLCFG = 0x06,
 230        PHY_CKCALCTRL = 0x05,
 231        PHY_CKSYMTXCTRL = 0x09,
 232        PHY_VLEVCTRL = 0x0e,
 233        PHY_PLLCURRCTRL = 0x10,
 234        PHY_PLLPHBYCTRL = 0x13,
 235        PHY_PLLGMPCTRL = 0x15,
 236        PHY_PLLCLKBISTPHASE = 0x17,
 237        PHY_TXTERM = 0x19,
 238
 239        /* ih_phy_stat0 field values */
 240        HDMI_IH_PHY_STAT0_HPD = 0x1,
 241
 242        /* ih_mute field values */
 243        HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
 244        HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
 245
 246        /* tx_invid0 field values */
 247        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
 248        HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
 249        HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
 250
 251        /* tx_instuffing field values */
 252        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
 253        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
 254        HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
 255
 256        /* vp_pr_cd field values */
 257        HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
 258        HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
 259        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
 260        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
 261
 262        /* vp_stuff field values */
 263        HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
 264        HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
 265        HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
 266        HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
 267        HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
 268        HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
 269        HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
 270        HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
 271
 272        /* vp_conf field values */
 273        HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
 274        HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
 275        HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
 276        HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
 277        HDMI_VP_CONF_PR_EN_MASK = 0x10,
 278        HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
 279        HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
 280        HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
 281        HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
 282        HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
 283        HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
 284        HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
 285
 286        /* vp_remap field values */
 287        HDMI_VP_REMAP_YCC422_16BIT = 0x0,
 288
 289        /* fc_invidconf field values */
 290        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
 291        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
 292        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
 293        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
 294        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
 295        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 296        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
 297        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
 298        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 299        HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
 300        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
 301        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
 302        HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
 303        HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
 304        HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
 305        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
 306        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
 307        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
 308        HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
 309        HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
 310        HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
 311
 312
 313        /* fc_aviconf0-fc_aviconf3 field values */
 314        HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
 315        HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
 316        HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
 317        HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
 318        HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
 319        HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
 320        HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
 321        HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
 322        HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
 323        HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
 324        HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
 325        HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
 326        HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
 327        HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
 328        HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
 329        HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
 330
 331        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
 332        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
 333        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
 334        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
 335        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
 336        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
 337        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
 338        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
 339        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
 340        HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
 341        HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
 342        HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
 343        HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
 344        HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
 345
 346        HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
 347        HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
 348        HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
 349        HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
 350        HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
 351        HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
 352        HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
 353        HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
 354        HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
 355        HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
 356        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
 357        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
 358        HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
 359        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
 360        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
 361        HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
 362        HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
 363        HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
 364
 365        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
 366        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
 367        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
 368        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
 369        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
 370        HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
 371        HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
 372        HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
 373
 374        /* fc_gcp field values*/
 375        HDMI_FC_GCP_SET_AVMUTE = 0x02,
 376        HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
 377
 378        /* phy_conf0 field values */
 379        HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 380        HDMI_PHY_CONF0_PDZ_OFFSET = 7,
 381        HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
 382        HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
 383        HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
 384        HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
 385        HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
 386        HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
 387        HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
 388        HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
 389        HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
 390        HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
 391        HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
 392        HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
 393
 394        /* phy_tst0 field values */
 395        HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
 396        HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
 397
 398        /* phy_stat0 field values */
 399        HDMI_PHY_HPD = 0x02,
 400        HDMI_PHY_TX_PHY_LOCK = 0x01,
 401
 402        /* phy_i2cm_slave_addr field values */
 403        HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
 404
 405        /* phy_i2cm_operation_addr field values */
 406        HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
 407
 408        /* hdmi_phy_i2cm_int_addr */
 409        HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
 410
 411        /* hdmi_phy_i2cm_ctlint_addr */
 412        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
 413        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
 414
 415        /* aud_conf0 field values */
 416        HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
 417        HDMI_AUD_CONF0_I2S_SELECT = 0x20,
 418        HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
 419        HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
 420        HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
 421        HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
 422
 423        /* aud_conf0 field values */
 424        HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
 425        HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
 426
 427        /* aud_n3 field values */
 428        HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
 429        HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
 430
 431        /* aud_cts3 field values */
 432        HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
 433        HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
 434        HDMI_AUD_CTS3_N_SHIFT_1 = 0,
 435        HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
 436        HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
 437        HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
 438        HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
 439        HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
 440        HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
 441        HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
 442
 443        /* aud_inputclkfs filed values */
 444        HDMI_AUD_INPUTCLKFS_128 = 0x0,
 445
 446        /* mc_clkdis field values */
 447        HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
 448        HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
 449        HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
 450        HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
 451        HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
 452        HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
 453        HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
 454
 455        /* mc_swrstz field values */
 456        HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
 457        HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
 458
 459        /* mc_flowctrl field values */
 460        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
 461        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
 462
 463        /* mc_phyrstz field values */
 464        HDMI_MC_PHYRSTZ_ASSERT = 0x0,
 465        HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
 466
 467        /* mc_heacphy_rst field values */
 468        HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
 469
 470        /* i2cm filed values */
 471        HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
 472        HDMI_I2CM_SEGADDR_DDC = 0x30,
 473        HDMI_I2CM_OP_RD8_EXT = 0x2,
 474        HDMI_I2CM_OP_RD8 = 0x1,
 475        HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
 476        HDMI_I2CM_DIV_FAST_MODE = 0x8,
 477        HDMI_I2CM_DIV_STD_MODE = 0x0,
 478        HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
 479
 480        /* CSC_CFG field values */
 481        HDMI_CSC_CFG_INTMODE_MASK = 0x30,
 482        HDMI_CSC_CFG_INTMODE_OFFSET = 4,
 483        HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
 484        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
 485        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
 486        HDMI_CSC_CFG_DECMODE_MASK = 0x3,
 487        HDMI_CSC_CFG_DECMODE_OFFSET = 0,
 488        HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
 489        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
 490        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
 491        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
 492
 493        /* CSC_SCALE field values */
 494        HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
 495        HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
 496        HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
 497        HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
 498        HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
 499        HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
 500};
 501
 502struct hdmi_mpll_config {
 503        u64 mpixelclock;
 504        /* Mode of Operation and PLL Dividers Control Register */
 505        u32 cpce;
 506        /* PLL Gmp Control Register */
 507        u32 gmp;
 508        /* PLL Current Control Register */
 509        u32 curr;
 510};
 511
 512struct hdmi_phy_config {
 513        u64 mpixelclock;
 514        u32 sym_ctr;    /* clock symbol and transmitter control */
 515        u32 term;       /* transmission termination value */
 516        u32 vlev_ctr;   /* voltage level control */
 517};
 518
 519struct hdmi_vmode {
 520        bool mdataenablepolarity;
 521
 522        unsigned int mpixelclock;
 523        unsigned int mpixelrepetitioninput;
 524        unsigned int mpixelrepetitionoutput;
 525};
 526
 527struct hdmi_data_info {
 528        unsigned int enc_in_bus_format;
 529        unsigned int enc_out_bus_format;
 530        unsigned int enc_in_encoding;
 531        unsigned int enc_out_encoding;
 532        unsigned int pix_repet_factor;
 533        unsigned int hdcp_enable;
 534        struct hdmi_vmode video_mode;
 535};
 536
 537struct dw_hdmi {
 538        ulong ioaddr;
 539        const struct hdmi_mpll_config *mpll_cfg;
 540        const struct hdmi_phy_config *phy_cfg;
 541        u8 i2c_clk_high;
 542        u8 i2c_clk_low;
 543        u8 reg_io_width;
 544        struct hdmi_data_info hdmi_data;
 545        struct udevice *ddc_bus;
 546
 547        int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
 548        void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
 549        u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
 550};
 551
 552int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
 553int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
 554void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
 555
 556int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
 557int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
 558void dw_hdmi_init(struct dw_hdmi *hdmi);
 559
 560#endif
 561