LXR uboot/include/fsl

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef FSL_DDR_MAIN_H
   7#define FSL_DDR_MAIN_H
   8
   9#include <fsl_ddrc_version.h>
  10#include <fsl_ddr_sdram.h>
  11#include <fsl_ddr_dimm_params.h>
  12
  13#include <common_timing_params.h>
  14
  15struct cmd_tbl;
  16
  17#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  18/* All controllers are for main memory */
  19#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_SYS_NUM_DDR_CTLRS
  20#endif
  21
  22#ifdef CONFIG_SYS_FSL_DDR_LE
  23#define ddr_in32(a)     in_le32(a)
  24#define ddr_out32(a, v) out_le32(a, v)
  25#define ddr_setbits32(a, v)     setbits_le32(a, v)
  26#define ddr_clrbits32(a, v)     clrbits_le32(a, v)
  27#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  28#else
  29#define ddr_in32(a)     in_be32(a)
  30#define ddr_out32(a, v) out_be32(a, v)
  31#define ddr_setbits32(a, v)     setbits_be32(a, v)
  32#define ddr_clrbits32(a, v)     clrbits_be32(a, v)
  33#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  34#endif
  35
  36u32 fsl_ddr_get_version(unsigned int ctrl_num);
  37
  38#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  39/*
  40 * Bind the main DDR setup driver's generic names
  41 * to this specific DDR technology.
  42 */
  43static __inline__ int
  44compute_dimm_parameters(const unsigned int ctrl_num,
  45                        const generic_spd_eeprom_t *spd,
  46                        dimm_params_t *pdimm,
  47                        unsigned int dimm_number)
  48{
  49        return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  50}
  51#endif
  52
  53/*
  54 * Data Structures
  55 *
  56 * All data structures have to be on the stack
  57 */
  58#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  59
  60typedef struct {
  61        generic_spd_eeprom_t
  62           spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  63        struct dimm_params_s
  64           dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  65        memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  66        common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  67        fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  68        unsigned int first_ctrl;
  69        unsigned int num_ctrls;
  70        unsigned long long mem_base;
  71        unsigned int dimm_slots_per_ctrl;
  72        int (*board_need_mem_reset)(void);
  73        void (*board_mem_reset)(void);
  74        void (*board_mem_de_reset)(void);
  75} fsl_ddr_info_t;
  76
  77/* Compute steps */
  78#define STEP_GET_SPD                 (1 << 0)
  79#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  80#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  81#define STEP_GATHER_OPTS             (1 << 3)
  82#define STEP_ASSIGN_ADDRESSES        (1 << 4)
  83#define STEP_COMPUTE_REGS            (1 << 5)
  84#define STEP_PROGRAM_REGS            (1 << 6)
  85#define STEP_ALL                     0xFFF
  86
  87unsigned long long
  88fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  89                                       unsigned int size_only);
  90const char *step_to_string(unsigned int step);
  91
  92unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  93                               const memctl_options_t *popts,
  94                               fsl_ddr_cfg_regs_t *ddr,
  95                               const common_timing_params_t *common_dimm,
  96                               const dimm_params_t *dimm_parameters,
  97                               unsigned int dbw_capacity_adjust,
  98                               unsigned int size_only);
  99unsigned int compute_lowest_common_dimm_parameters(
 100                                const unsigned int ctrl_num,
 101                                const dimm_params_t *dimm_params,
 102                                common_timing_params_t *outpdimm,
 103                                unsigned int number_of_dimms);
 104unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 105                                memctl_options_t *popts,
 106                                dimm_params_t *pdimm,
 107                                unsigned int ctrl_num);
 108void check_interleaving_options(fsl_ddr_info_t *pinfo);
 109
 110unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
 111unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
 112unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
 113void fsl_ddr_set_lawbar(
 114                const common_timing_params_t *memctl_common_params,
 115                unsigned int memctl_interleaved,
 116                unsigned int ctrl_num);
 117void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 118                                 unsigned int last_ctrl);
 119
 120int fsl_ddr_interactive_env_var_exists(void);
 121unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 122void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 123                     unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 124
 125int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 126unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 127void board_add_ram_info(int use_default);
 128
 129/* processor specific function */
 130void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 131                                   unsigned int ctrl_num, int step);
 132void remove_unused_controllers(fsl_ddr_info_t *info);
 133
 134/* board specific function */
 135int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 136                        unsigned int controller_number,
 137                        unsigned int dimm_number);
 138void update_spd_address(unsigned int ctrl_num,
 139                        unsigned int slot,
 140                        unsigned int *addr);
 141
 142void erratum_a009942_check_cpo(void);
 143#endif
 144