1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * FSL SD/MMC Defines 4 *------------------------------------------------------------------- 5 * 6 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc 7 * Copyright 2020 NXP 8 */ 9 10#ifndef __FSL_ESDHC_H__ 11#define __FSL_ESDHC_H__ 12 13#include <linux/errno.h> 14#include <asm/byteorder.h> 15 16/* needed for the mmc_cfg definition */ 17#include <mmc.h> 18 19/* FSL eSDHC-specific constants */ 20#define SYSCTL 0x0002e02c 21#define SYSCTL_INITA 0x08000000 22#define SYSCTL_TIMEOUT_MASK 0x000f0000 23#define SYSCTL_CLOCK_MASK 0x0000fff0 24#define SYSCTL_CKEN 0x00000008 25#define SYSCTL_PEREN 0x00000004 26#define SYSCTL_HCKEN 0x00000002 27#define SYSCTL_IPGEN 0x00000001 28#define SYSCTL_RSTA 0x01000000 29#define SYSCTL_RSTC 0x02000000 30#define SYSCTL_RSTD 0x04000000 31 32#define IRQSTAT 0x0002e030 33#define IRQSTAT_DMAE (0x10000000) 34#define IRQSTAT_AC12E (0x01000000) 35#define IRQSTAT_DEBE (0x00400000) 36#define IRQSTAT_DCE (0x00200000) 37#define IRQSTAT_DTOE (0x00100000) 38#define IRQSTAT_CIE (0x00080000) 39#define IRQSTAT_CEBE (0x00040000) 40#define IRQSTAT_CCE (0x00020000) 41#define IRQSTAT_CTOE (0x00010000) 42#define IRQSTAT_CINT (0x00000100) 43#define IRQSTAT_CRM (0x00000080) 44#define IRQSTAT_CINS (0x00000040) 45#define IRQSTAT_BRR (0x00000020) 46#define IRQSTAT_BWR (0x00000010) 47#define IRQSTAT_DINT (0x00000008) 48#define IRQSTAT_BGE (0x00000004) 49#define IRQSTAT_TC (0x00000002) 50#define IRQSTAT_CC (0x00000001) 51 52#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) 53#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ 54 IRQSTAT_DMAE) 55#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) 56 57#define IRQSTATEN 0x0002e034 58#define IRQSTATEN_DMAE (0x10000000) 59#define IRQSTATEN_AC12E (0x01000000) 60#define IRQSTATEN_DEBE (0x00400000) 61#define IRQSTATEN_DCE (0x00200000) 62#define IRQSTATEN_DTOE (0x00100000) 63#define IRQSTATEN_CIE (0x00080000) 64#define IRQSTATEN_CEBE (0x00040000) 65#define IRQSTATEN_CCE (0x00020000) 66#define IRQSTATEN_CTOE (0x00010000) 67#define IRQSTATEN_CINT (0x00000100) 68#define IRQSTATEN_CRM (0x00000080) 69#define IRQSTATEN_CINS (0x00000040) 70#define IRQSTATEN_BRR (0x00000020) 71#define IRQSTATEN_BWR (0x00000010) 72#define IRQSTATEN_DINT (0x00000008) 73#define IRQSTATEN_BGE (0x00000004) 74#define IRQSTATEN_TC (0x00000002) 75#define IRQSTATEN_CC (0x00000001) 76 77/* eSDHC control register */ 78#define ESDHCCTL 0x0002e40c 79#define ESDHCCTL_PCS (0x00080000) 80#define ESDHCCTL_FAF (0x00040000) 81 82#define PRSSTAT 0x0002e024 83#define PRSSTAT_DAT0 (0x01000000) 84#define PRSSTAT_CLSL (0x00800000) 85#define PRSSTAT_WPSPL (0x00080000) 86#define PRSSTAT_CDPL (0x00040000) 87#define PRSSTAT_CINS (0x00010000) 88#define PRSSTAT_BREN (0x00000800) 89#define PRSSTAT_BWEN (0x00000400) 90#define PRSSTAT_SDSTB (0X00000008) 91#define PRSSTAT_DLA (0x00000004) 92#define PRSSTAT_CICHB (0x00000002) 93#define PRSSTAT_CIDHB (0x00000001) 94 95#define PROCTL 0x0002e028 96#define PROCTL_INIT 0x00000020 97#define PROCTL_DTW_4 0x00000002 98#define PROCTL_DTW_8 0x00000004 99#define PROCTL_D3CD 0x00000008 100#define PROCTL_DMAS_MASK 0x00000300 101#define PROCTL_DMAS_SDMA 0x00000000 102#define PROCTL_DMAS_ADMA1 0x00000100 103#define PROCTL_DMAS_ADMA2 0x00000300 104#define PROCTL_VOLT_SEL 0x00000400 105 106#define CMDARG 0x0002e008 107 108#define XFERTYP 0x0002e00c 109#define XFERTYP_CMD(x) ((x & 0x3f) << 24) 110#define XFERTYP_CMDTYP_NORMAL 0x0 111#define XFERTYP_CMDTYP_SUSPEND 0x00400000 112#define XFERTYP_CMDTYP_RESUME 0x00800000 113#define XFERTYP_CMDTYP_ABORT 0x00c00000 114#define XFERTYP_DPSEL 0x00200000 115#define XFERTYP_CICEN 0x00100000 116#define XFERTYP_CCCEN 0x00080000 117#define XFERTYP_RSPTYP_NONE 0 118#define XFERTYP_RSPTYP_136 0x00010000 119#define XFERTYP_RSPTYP_48 0x00020000 120#define XFERTYP_RSPTYP_48_BUSY 0x00030000 121#define XFERTYP_MSBSEL 0x00000020 122#define XFERTYP_DTDSEL 0x00000010 123#define XFERTYP_DDREN 0x00000008 124#define XFERTYP_AC12EN 0x00000004 125#define XFERTYP_BCEN 0x00000002 126#define XFERTYP_DMAEN 0x00000001 127 128#define CINS_TIMEOUT 1000 129#define PIO_TIMEOUT 500 130 131#define DSADDR 0x2e004 132 133#define CMDRSP0 0x2e010 134#define CMDRSP1 0x2e014 135#define CMDRSP2 0x2e018 136#define CMDRSP3 0x2e01c 137 138#define DATPORT 0x2e020 139 140#define WML 0x2e044 141#define WML_WRITE 0x00010000 142#ifdef CONFIG_FSL_SDHC_V2_3 143#define WML_RD_WML_MAX 0x80 144#define WML_WR_WML_MAX 0x80 145#define WML_RD_WML_MAX_VAL 0x0 146#define WML_WR_WML_MAX_VAL 0x0 147#define WML_RD_WML_MASK 0x7f 148#define WML_WR_WML_MASK 0x7f0000 149#else 150#define WML_RD_WML_MAX 0x10 151#define WML_WR_WML_MAX 0x80 152#define WML_RD_WML_MAX_VAL 0x10 153#define WML_WR_WML_MAX_VAL 0x80 154#define WML_RD_WML_MASK 0xff 155#define WML_WR_WML_MASK 0xff0000 156#endif 157 158#define BLKATTR 0x2e004 159#define BLKATTR_CNT(x) ((x & 0xffff) << 16) 160#define BLKATTR_SIZE(x) (x & 0x1fff) 161#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ 162 163/* Auto CMD error status register / system control 2 register */ 164#define EXECUTE_TUNING 0x00400000 165#define SMPCLKSEL 0x00800000 166#define UHSM_MASK 0x00070000 167#define UHSM_SDR104_HS200 0x00030000 168 169/* Host controller capabilities register */ 170#define HOSTCAPBLT_VS18 0x04000000 171#define HOSTCAPBLT_VS30 0x02000000 172#define HOSTCAPBLT_VS33 0x01000000 173#define HOSTCAPBLT_SRS 0x00800000 174#define HOSTCAPBLT_DMAS 0x00400000 175#define HOSTCAPBLT_HSS 0x00200000 176 177/* Tuning block control register */ 178#define TBCTL_TB_EN 0x00000004 179#define HS400_MODE 0x00000010 180#define HS400_WNDW_ADJUST 0x00000040 181 182/* SD clock control register */ 183#define CMD_CLK_CTL 0x00008000 184 185/* SD timing control register */ 186#define FLW_CTL_BG 0x00008000 187 188/* DLL config 0 register */ 189#define DLL_ENABLE 0x80000000 190#define DLL_RESET 0x40000000 191#define DLL_FREQ_SEL 0x08000000 192 193/* DLL config 1 register */ 194#define DLL_PD_PULSE_STRETCH_SEL 0x80000000 195 196/* DLL status 0 register */ 197#define DLL_STS_SLV_LOCK 0x08000000 198 199#define MAX_TUNING_LOOP 40 200 201#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff) 202#define VENDOR_V_10 0x00 203#define VENDOR_V_20 0x10 204#define VENDOR_V_21 0x11 205#define VENDOR_V_22 0x12 206#define VENDOR_V_23 0x13 207#define VENDOR_V_30 0x20 208#define VENDOR_V_31 0x21 209#define VENDOR_V_32 0x22 210 211struct fsl_esdhc_cfg { 212 phys_addr_t esdhc_base; 213 u32 sdhc_clk; 214 u8 max_bus_width; 215 int vs18_enable; /* Use 1.8V if set to 1 */ 216 struct mmc_config cfg; 217}; 218 219/* Select the correct accessors depending on endianess */ 220#if defined CONFIG_SYS_FSL_ESDHC_LE 221#define esdhc_read32 in_le32 222#define esdhc_write32 out_le32 223#define esdhc_clrsetbits32 clrsetbits_le32 224#define esdhc_clrbits32 clrbits_le32 225#define esdhc_setbits32 setbits_le32 226#elif defined(CONFIG_SYS_FSL_ESDHC_BE) 227#define esdhc_read32 in_be32 228#define esdhc_write32 out_be32 229#define esdhc_clrsetbits32 clrsetbits_be32 230#define esdhc_clrbits32 clrbits_be32 231#define esdhc_setbits32 setbits_be32 232#elif __BYTE_ORDER == __LITTLE_ENDIAN 233#define esdhc_read32 in_le32 234#define esdhc_write32 out_le32 235#define esdhc_clrsetbits32 clrsetbits_le32 236#define esdhc_clrbits32 clrbits_le32 237#define esdhc_setbits32 setbits_le32 238#elif __BYTE_ORDER == __BIG_ENDIAN 239#define esdhc_read32 in_be32 240#define esdhc_write32 out_be32 241#define esdhc_clrsetbits32 clrsetbits_be32 242#define esdhc_clrbits32 clrbits_be32 243#define esdhc_setbits32 setbits_be32 244#else 245#error "Endianess is not defined: please fix to continue" 246#endif 247 248#ifdef CONFIG_FSL_ESDHC 249int fsl_esdhc_mmc_init(struct bd_info *bis); 250int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); 251void fdt_fixup_esdhc(void *blob, struct bd_info *bd); 252#else 253static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; } 254static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {} 255#endif /* CONFIG_FSL_ESDHC */ 256void __noreturn mmc_boot(void); 257void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); 258 259#endif /* __FSL_ESDHC_H__ */ 260