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6
7#ifndef __FSL_IFC_H
8#define __FSL_IFC_H
9
10#ifdef CONFIG_FSL_IFC
11#include <config.h>
12#include <common.h>
13#include <part.h>
14#ifdef CONFIG_ARM
15#include <asm/arch/soc.h>
16#endif
17
18#define FSL_IFC_V1_1_0 0x01010000
19#define FSL_IFC_V2_0_0 0x02000000
20
21#ifdef CONFIG_SYS_FSL_IFC_LE
22#define ifc_in32(a) in_le32(a)
23#define ifc_out32(a, v) out_le32(a, v)
24#define ifc_in16(a) in_le16(a)
25#define ifc_out16(a, v) out_le16(a, v)
26#elif defined(CONFIG_SYS_FSL_IFC_BE)
27#define ifc_in32(a) in_be32(a)
28#define ifc_out32(a, v) out_be32(a, v)
29#define ifc_in16(a) in_be16(a)
30#define ifc_out16(a, v) out_be16(a, v)
31#else
32#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
33#endif
34
35
36
37
38
39#define CSPR_BA 0xFFFF0000
40#define CSPR_BA_SHIFT 16
41#define CSPR_PORT_SIZE 0x00000180
42#define CSPR_PORT_SIZE_SHIFT 7
43
44#define CSPR_PORT_SIZE_8 0x00000080
45
46#define CSPR_PORT_SIZE_16 0x00000100
47
48#define CSPR_PORT_SIZE_32 0x00000180
49
50#define CSPR_WP 0x00000040
51#define CSPR_WP_SHIFT 6
52
53#define CSPR_MSEL 0x00000006
54#define CSPR_MSEL_SHIFT 1
55
56#define CSPR_TE 0x00000010
57
58#define CSPR_MSEL_NOR 0x00000000
59
60#define CSPR_MSEL_NAND 0x00000002
61
62#define CSPR_MSEL_GPCM 0x00000004
63
64#define CSPR_V 0x00000001
65#define CSPR_V_SHIFT 0
66
67
68#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
69
70
71
72
73#define IFC_AMASK_MASK 0xFFFF0000
74#define IFC_AMASK_SHIFT 16
75#define IFC_AMASK(n) (IFC_AMASK_MASK << \
76 (LOG2(n) - IFC_AMASK_SHIFT))
77
78
79
80
81
82#define CSOR_NAND_ECC_ENC_EN 0x80000000
83#define CSOR_NAND_ECC_MODE_MASK 0x30000000
84
85#define CSOR_NAND_ECC_MODE_4 0x00000000
86
87#define CSOR_NAND_ECC_MODE_8 0x10000000
88
89#define CSOR_NAND_ECC_DEC_EN 0x04000000
90
91#define CSOR_NAND_RAL_MASK 0x01800000
92#define CSOR_NAND_RAL_SHIFT 20
93#define CSOR_NAND_RAL_1 0x00000000
94#define CSOR_NAND_RAL_2 0x00800000
95#define CSOR_NAND_RAL_3 0x01000000
96#define CSOR_NAND_RAL_4 0x01800000
97
98#define CSOR_NAND_PGS_MASK 0x00180000
99#define CSOR_NAND_PGS_SHIFT 16
100#define CSOR_NAND_PGS_512 0x00000000
101#define CSOR_NAND_PGS_2K 0x00080000
102#define CSOR_NAND_PGS_4K 0x00100000
103#define CSOR_NAND_PGS_8K 0x00180000
104
105#define CSOR_NAND_SPRZ_MASK 0x0000E000
106#define CSOR_NAND_SPRZ_SHIFT 13
107#define CSOR_NAND_SPRZ_16 0x00000000
108#define CSOR_NAND_SPRZ_64 0x00002000
109#define CSOR_NAND_SPRZ_128 0x00004000
110#define CSOR_NAND_SPRZ_210 0x00006000
111#define CSOR_NAND_SPRZ_218 0x00008000
112#define CSOR_NAND_SPRZ_224 0x0000A000
113#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
114
115#define CSOR_NAND_PB_MASK 0x00000700
116#define CSOR_NAND_PB_SHIFT 8
117#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
118
119#define CSOR_NAND_TRHZ_MASK 0x0000001C
120#define CSOR_NAND_TRHZ_SHIFT 2
121#define CSOR_NAND_TRHZ_20 0x00000000
122#define CSOR_NAND_TRHZ_40 0x00000004
123#define CSOR_NAND_TRHZ_60 0x00000008
124#define CSOR_NAND_TRHZ_80 0x0000000C
125#define CSOR_NAND_TRHZ_100 0x00000010
126
127#define CSOR_NAND_BCTLD 0x00000001
128
129
130
131
132
133#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
134
135#define CSOR_NOR_PGRD_EN 0x10000000
136
137#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
138
139#define CSOR_NOR_ADM_MASK 0x0003E000
140#define CSOR_NOR_ADM_SHIFT_SHIFT 13
141#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
142
143#define CSOR_NOR_NOR_MODE_ASYNC_NOR 0x00000000
144#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
145
146#define CSOR_NOR_TRHZ_MASK 0x0000001C
147#define CSOR_NOR_TRHZ_SHIFT 2
148#define CSOR_NOR_TRHZ_20 0x00000000
149#define CSOR_NOR_TRHZ_40 0x00000004
150#define CSOR_NOR_TRHZ_60 0x00000008
151#define CSOR_NOR_TRHZ_80 0x0000000C
152#define CSOR_NOR_TRHZ_100 0x00000010
153
154#define CSOR_NOR_BCTLD 0x00000001
155
156
157
158
159
160#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
161
162#define CSOR_GPCM_GPMODE_ASIC 0x80000000
163
164#define CSOR_GPCM_PARITY_EVEN 0x40000000
165
166#define CSOR_GPCM_PAR_EN 0x20000000
167
168#define CSOR_GPCM_GPTO_MASK 0x0F000000
169#define CSOR_GPCM_GPTO_SHIFT 24
170#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
171
172#define CSOR_GPCM_RGETA_EXT 0x00080000
173
174#define CSOR_GPCM_WGETA_EXT 0x00040000
175
176#define CSOR_GPCM_ADM_MASK 0x0003E000
177#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
178#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
179
180#define CSOR_GPCM_GAPERRD_MASK 0x00000180
181#define CSOR_GPCM_GAPERRD_SHIFT 7
182#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
183
184#define CSOR_GPCM_TRHZ_MASK 0x0000001C
185#define CSOR_GPCM_TRHZ_20 0x00000000
186#define CSOR_GPCM_TRHZ_40 0x00000004
187#define CSOR_GPCM_TRHZ_60 0x00000008
188#define CSOR_GPCM_TRHZ_80 0x0000000C
189#define CSOR_GPCM_TRHZ_100 0x00000010
190
191#define CSOR_GPCM_BCTLD 0x00000001
192
193
194
195
196
197
198
199#define FTIM0_NAND 0x7EFF3F3F
200#define FTIM0_NAND_TCCST_SHIFT 25
201#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
202#define FTIM0_NAND_TWP_SHIFT 16
203#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
204#define FTIM0_NAND_TWCHT_SHIFT 8
205#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
206#define FTIM0_NAND_TWH_SHIFT 0
207#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
208
209
210
211#define FTIM1_NAND 0xFFFF3FFF
212#define FTIM1_NAND_TADLE_SHIFT 24
213#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
214#define FTIM1_NAND_TWBE_SHIFT 16
215#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
216#define FTIM1_NAND_TRR_SHIFT 8
217#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
218#define FTIM1_NAND_TRP_SHIFT 0
219#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
220
221
222
223#define FTIM2_NAND 0x1FE1F8FF
224#define FTIM2_NAND_TRAD_SHIFT 21
225#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
226#define FTIM2_NAND_TREH_SHIFT 11
227#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
228#define FTIM2_NAND_TWHRE_SHIFT 0
229#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
230
231
232
233#define FTIM3_NAND 0xFF000000
234#define FTIM3_NAND_TWW_SHIFT 24
235#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
236
237
238
239
240#define FTIM0_NOR 0xF03F3F3F
241#define FTIM0_NOR_TACSE_SHIFT 28
242#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
243#define FTIM0_NOR_TEADC_SHIFT 16
244#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
245#define FTIM0_NOR_TAVDS_SHIFT 8
246#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
247#define FTIM0_NOR_TEAHC_SHIFT 0
248#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
249
250
251
252#define FTIM1_NOR 0xFF003F3F
253#define FTIM1_NOR_TACO_SHIFT 24
254#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
255#define FTIM1_NOR_TRAD_NOR_SHIFT 8
256#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
257#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
258#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
259
260
261
262#define FTIM2_NOR 0x0F3CFCFF
263#define FTIM2_NOR_TCS_SHIFT 24
264#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
265#define FTIM2_NOR_TCH_SHIFT 18
266#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
267#define FTIM2_NOR_TWPH_SHIFT 10
268#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
269#define FTIM2_NOR_TWP_SHIFT 0
270#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
271
272
273
274
275#define FTIM0_GPCM 0xF03F3F3F
276#define FTIM0_GPCM_TACSE_SHIFT 28
277#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
278#define FTIM0_GPCM_TEADC_SHIFT 16
279#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
280#define FTIM0_GPCM_TAVDS_SHIFT 8
281#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
282#define FTIM0_GPCM_TEAHC_SHIFT 0
283#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
284
285
286
287#define FTIM1_GPCM 0xFF003F00
288#define FTIM1_GPCM_TACO_SHIFT 24
289#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
290#define FTIM1_GPCM_TRAD_SHIFT 8
291#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
292
293
294
295#define FTIM2_GPCM 0x0F3C00FF
296#define FTIM2_GPCM_TCS_SHIFT 24
297#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
298#define FTIM2_GPCM_TCH_SHIFT 18
299#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
300#define FTIM2_GPCM_TWP_SHIFT 0
301#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
302
303
304
305
306
307#define IFC_RB_STAT_READY_CS0 0x80000000
308#define IFC_RB_STAT_READY_CS1 0x40000000
309#define IFC_RB_STAT_READY_CS2 0x20000000
310#define IFC_RB_STAT_READY_CS3 0x10000000
311
312
313
314
315#define IFC_GCR_MASK 0x8000F800
316
317#define IFC_GCR_SOFT_RST_ALL 0x80000000
318
319#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
320#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
321
322
323
324
325
326#define IFC_CM_EVTER_STAT_CSER 0x80000000
327
328
329
330
331
332#define IFC_CM_EVTER_EN_CSEREN 0x80000000
333
334
335
336
337
338#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
339
340
341
342
343
344#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
345#define IFC_CM_ERATTR0_ERAID 0x0FF00000
346#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
347
348
349
350
351#define IFC_CCR_MASK 0x0F0F8800
352
353#define IFC_CCR_CLK_DIV_MASK 0x0F000000
354#define IFC_CCR_CLK_DIV_SHIFT 24
355#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
356
357#define IFC_CCR_CLK_DLY_MASK 0x000F0000
358#define IFC_CCR_CLK_DLY_SHIFT 16
359#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
360
361#define IFC_CCR_INV_CLK_EN 0x00008000
362
363#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
364
365
366
367
368
369#define IFC_CSR_CLK_STAT_STABLE 0x80000000
370
371
372
373
374
375
376
377
378#define IFC_NAND_NCFGR_BOOT 0x80000000
379
380#define IFC_NAND_SRAM_INIT_EN 0x20000000
381
382#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
383
384#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
385
386#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
387#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
388#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
389
390#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
391#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
392
393
394
395
396
397#define IFC_NAND_FCR0_CMD0 0xFF000000
398#define IFC_NAND_FCR0_CMD0_SHIFT 24
399#define IFC_NAND_FCR0_CMD1 0x00FF0000
400#define IFC_NAND_FCR0_CMD1_SHIFT 16
401#define IFC_NAND_FCR0_CMD2 0x0000FF00
402#define IFC_NAND_FCR0_CMD2_SHIFT 8
403#define IFC_NAND_FCR0_CMD3 0x000000FF
404#define IFC_NAND_FCR0_CMD3_SHIFT 0
405#define IFC_NAND_FCR1_CMD4 0xFF000000
406#define IFC_NAND_FCR1_CMD4_SHIFT 24
407#define IFC_NAND_FCR1_CMD5 0x00FF0000
408#define IFC_NAND_FCR1_CMD5_SHIFT 16
409#define IFC_NAND_FCR1_CMD6 0x0000FF00
410#define IFC_NAND_FCR1_CMD6_SHIFT 8
411#define IFC_NAND_FCR1_CMD7 0x000000FF
412#define IFC_NAND_FCR1_CMD7_SHIFT 0
413
414
415
416
417
418#define IFC_NAND_COL_MS 0x80000000
419
420#define IFC_NAND_COL_CA_MASK 0x00000FFF
421
422
423
424
425
426#define IFC_NAND_BC 0x000001FF
427
428
429
430
431
432#define IFC_NAND_FIR0_OP0 0xFC000000
433#define IFC_NAND_FIR0_OP0_SHIFT 26
434#define IFC_NAND_FIR0_OP1 0x03F00000
435#define IFC_NAND_FIR0_OP1_SHIFT 20
436#define IFC_NAND_FIR0_OP2 0x000FC000
437#define IFC_NAND_FIR0_OP2_SHIFT 14
438#define IFC_NAND_FIR0_OP3 0x00003F00
439#define IFC_NAND_FIR0_OP3_SHIFT 8
440#define IFC_NAND_FIR0_OP4 0x000000FC
441#define IFC_NAND_FIR0_OP4_SHIFT 2
442#define IFC_NAND_FIR1_OP5 0xFC000000
443#define IFC_NAND_FIR1_OP5_SHIFT 26
444#define IFC_NAND_FIR1_OP6 0x03F00000
445#define IFC_NAND_FIR1_OP6_SHIFT 20
446#define IFC_NAND_FIR1_OP7 0x000FC000
447#define IFC_NAND_FIR1_OP7_SHIFT 14
448#define IFC_NAND_FIR1_OP8 0x00003F00
449#define IFC_NAND_FIR1_OP8_SHIFT 8
450#define IFC_NAND_FIR1_OP9 0x000000FC
451#define IFC_NAND_FIR1_OP9_SHIFT 2
452#define IFC_NAND_FIR2_OP10 0xFC000000
453#define IFC_NAND_FIR2_OP10_SHIFT 26
454#define IFC_NAND_FIR2_OP11 0x03F00000
455#define IFC_NAND_FIR2_OP11_SHIFT 20
456#define IFC_NAND_FIR2_OP12 0x000FC000
457#define IFC_NAND_FIR2_OP12_SHIFT 14
458#define IFC_NAND_FIR2_OP13 0x00003F00
459#define IFC_NAND_FIR2_OP13_SHIFT 8
460#define IFC_NAND_FIR2_OP14 0x000000FC
461#define IFC_NAND_FIR2_OP14_SHIFT 2
462
463
464
465
466
467enum ifc_nand_fir_opcodes {
468 IFC_FIR_OP_NOP,
469 IFC_FIR_OP_CA0,
470 IFC_FIR_OP_CA1,
471 IFC_FIR_OP_CA2,
472 IFC_FIR_OP_CA3,
473 IFC_FIR_OP_RA0,
474 IFC_FIR_OP_RA1,
475 IFC_FIR_OP_RA2,
476 IFC_FIR_OP_RA3,
477 IFC_FIR_OP_CMD0,
478 IFC_FIR_OP_CMD1,
479 IFC_FIR_OP_CMD2,
480 IFC_FIR_OP_CMD3,
481 IFC_FIR_OP_CMD4,
482 IFC_FIR_OP_CMD5,
483 IFC_FIR_OP_CMD6,
484 IFC_FIR_OP_CMD7,
485 IFC_FIR_OP_CW0,
486 IFC_FIR_OP_CW1,
487 IFC_FIR_OP_CW2,
488 IFC_FIR_OP_CW3,
489 IFC_FIR_OP_CW4,
490 IFC_FIR_OP_CW5,
491 IFC_FIR_OP_CW6,
492 IFC_FIR_OP_CW7,
493 IFC_FIR_OP_WBCD,
494 IFC_FIR_OP_RBCD,
495 IFC_FIR_OP_BTRD,
496 IFC_FIR_OP_RDSTAT,
497 IFC_FIR_OP_NWAIT,
498 IFC_FIR_OP_WFR,
499 IFC_FIR_OP_SBRD,
500 IFC_FIR_OP_UA,
501 IFC_FIR_OP_RB,
502};
503
504
505
506
507#define IFC_NAND_CSEL 0x0C000000
508#define IFC_NAND_CSEL_SHIFT 26
509#define IFC_NAND_CSEL_CS0 0x00000000
510#define IFC_NAND_CSEL_CS1 0x04000000
511#define IFC_NAND_CSEL_CS2 0x08000000
512#define IFC_NAND_CSEL_CS3 0x0C000000
513
514
515
516
517
518#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
519
520#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
521
522#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
523
524#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
525
526#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
527
528#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
529
530
531
532
533
534#define IFC_NAND_EVTER_STAT_OPC 0x80000000
535
536#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
537
538#define IFC_NAND_EVTER_STAT_WPER 0x04000000
539
540#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
541
542#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
543
544#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
545
546#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
547
548
549
550
551
552#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
553
554#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
555
556#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
557
558#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
559
560
561
562
563
564#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
565
566#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
567
568#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
569
570#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
571
572#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
573
574
575
576
577
578#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
579
580#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
581
582#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
583
584#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
585
586#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
587
588
589
590
591#define IFC_NAND_ERATTR0_MASK 0x0C080000
592
593#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
594#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
595#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
596#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
597
598#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
599
600
601
602
603
604#define IFC_NAND_NFSR_RS0 0xFF000000
605
606#define IFC_NAND_NFSR_RS1 0x00FF0000
607
608
609
610
611
612#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
613#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
614#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
615#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
616#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
617#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
618#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
619#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
620#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
621#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
622#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
623#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
624#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
625#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
626#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
627#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
628#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
629#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
630#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
631#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
632#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
633#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
634#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
635#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
636#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
637#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
638#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
639#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
640#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
641#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
642#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
643#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
644
645
646
647
648#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
649#define IFC_NAND_NCR_FTOCNT_SHIFT 25
650#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
651
652
653
654
655
656#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
657
658#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
659
660
661
662
663
664#define IFC_NAND_MDR_RDATA0 0xFF000000
665
666#define IFC_NAND_MDR_RDATA1 0x00FF0000
667
668
669
670
671
672
673
674
675#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
676
677#define IFC_NOR_EVTER_STAT_WPER 0x04000000
678
679#define IFC_NOR_EVTER_STAT_STOER 0x01000000
680
681
682
683
684
685#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
686
687#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
688
689#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
690
691
692
693
694
695#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
696
697#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
698
699#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
700
701
702
703
704
705#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
706
707#define IFC_NOR_ERATTR0_ERAID 0x000FF000
708
709#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
710#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
711#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
712#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
713
714#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
715
716
717
718
719#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
720#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
721
722
723
724
725#define IFC_NORCR_MASK 0x0F0F0000
726
727#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
728#define IFC_NORCR_NUM_PHASE_SHIFT 24
729#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
730
731#define IFC_NORCR_STOCNT_MASK 0x000F0000
732#define IFC_NORCR_STOCNT_SHIFT 16
733#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
734
735
736
737
738
739
740
741
742#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
743
744#define IFC_GPCM_EVTER_STAT_PER 0x01000000
745
746
747
748
749
750#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
751
752#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
753
754
755
756
757
758#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
759
760#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
761
762
763
764
765
766#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
767
768#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
769
770#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
771#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
772#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
773#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
774
775#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
776
777
778
779
780
781#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
782
783#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
784
785#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
786
787
788
789
790#define IFC_GPCM_STAT_BSY 0x80000000
791
792
793#ifndef __ASSEMBLY__
794#include <asm/io.h>
795
796extern void print_ifc_regs(void);
797extern void init_early_memctl_regs(void);
798void init_final_memctl_regs(void);
799
800#define IFC_RREGS_4KOFFSET (4*1024)
801#define IFC_RREGS_64KOFFSET (64*1024)
802
803#define IFC_FCM_BASE_ADDR \
804 ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
805
806#define get_ifc_cspr_ext(i) \
807 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
808#define get_ifc_cspr(i) \
809 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
810#define get_ifc_csor_ext(i) \
811 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
812#define get_ifc_csor(i) \
813 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
814#define get_ifc_amask(i) \
815 (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
816#define get_ifc_ftim(i, j) \
817 (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
818#define set_ifc_cspr_ext(i, v) \
819 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
820#define set_ifc_cspr(i, v) \
821 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
822#define set_ifc_csor_ext(i, v) \
823 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
824#define set_ifc_csor(i, v) \
825 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
826#define set_ifc_amask(i, v) \
827 (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
828#define set_ifc_ftim(i, j, v) \
829 (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
830
831enum ifc_chip_sel {
832 IFC_CS0,
833 IFC_CS1,
834 IFC_CS2,
835 IFC_CS3,
836 IFC_CS4,
837 IFC_CS5,
838 IFC_CS6,
839 IFC_CS7,
840};
841
842enum ifc_ftims {
843 IFC_FTIM0,
844 IFC_FTIM1,
845 IFC_FTIM2,
846 IFC_FTIM3,
847};
848
849
850
851
852struct fsl_ifc_nand {
853 u32 ncfgr;
854 u32 res1[0x4];
855 u32 nand_fcr0;
856 u32 nand_fcr1;
857 u32 res2[0x8];
858 u32 row0;
859 u32 res3;
860 u32 col0;
861 u32 res4;
862 u32 row1;
863 u32 res5;
864 u32 col1;
865 u32 res6;
866 u32 row2;
867 u32 res7;
868 u32 col2;
869 u32 res8;
870 u32 row3;
871 u32 res9;
872 u32 col3;
873 u32 res10[0x24];
874 u32 nand_fbcr;
875 u32 res11;
876 u32 nand_fir0;
877 u32 nand_fir1;
878 u32 nand_fir2;
879 u32 res12[0x10];
880 u32 nand_csel;
881 u32 res13;
882 u32 nandseq_strt;
883 u32 res14;
884 u32 nand_evter_stat;
885 u32 res15;
886 u32 pgrdcmpl_evt_stat;
887 u32 res16[0x2];
888 u32 nand_evter_en;
889 u32 res17[0x2];
890 u32 nand_evter_intr_en;
891 u32 nand_vol_addr_stat;
892 u32 res18;
893 u32 nand_erattr0;
894 u32 nand_erattr1;
895 u32 res19[0x10];
896 u32 nand_fsr;
897 u32 res20[0x1];
898 u32 nand_eccstat[8];
899 u32 res21[0x1c];
900 u32 nanndcr;
901 u32 res22[0x2];
902 u32 nand_autoboot_trgr;
903 u32 res23;
904 u32 nand_mdr;
905 u32 res24[0x1c];
906 u32 nand_dll_lowcfg0;
907 u32 nand_dll_lowcfg1;
908 u32 res25;
909 u32 nand_dll_lowstat;
910 u32 res26[0x3C];
911};
912
913
914
915
916struct fsl_ifc_nor {
917 u32 nor_evter_stat;
918 u32 res1[0x2];
919 u32 nor_evter_en;
920 u32 res2[0x2];
921 u32 nor_evter_intr_en;
922 u32 res3[0x2];
923 u32 nor_erattr0;
924 u32 nor_erattr1;
925 u32 nor_erattr2;
926 u32 res4[0x4];
927 u32 norcr;
928 u32 res5[0xEF];
929};
930
931
932
933
934struct fsl_ifc_gpcm {
935 u32 gpcm_evter_stat;
936 u32 res1[0x2];
937 u32 gpcm_evter_en;
938 u32 res2[0x2];
939 u32 gpcm_evter_intr_en;
940 u32 res3[0x2];
941 u32 gpcm_erattr0;
942 u32 gpcm_erattr1;
943 u32 gpcm_erattr2;
944 u32 gpcm_stat;
945};
946
947#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
948#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
949#define IFC_CSPR_REG_LEN 148
950#define IFC_AMASK_REG_LEN 144
951#define IFC_CSOR_REG_LEN 144
952#define IFC_FTIM_REG_LEN 576
953
954#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
955 CONFIG_SYS_FSL_IFC_BANK_COUNT
956#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
957 CONFIG_SYS_FSL_IFC_BANK_COUNT
958#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
959 CONFIG_SYS_FSL_IFC_BANK_COUNT
960#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
961 CONFIG_SYS_FSL_IFC_BANK_COUNT
962#else
963#error IFC BANK count not vaild
964#endif
965#else
966#error IFC BANK count not defined
967#endif
968
969struct fsl_ifc_cspr {
970 u32 cspr_ext;
971 u32 cspr;
972 u32 res;
973};
974
975struct fsl_ifc_amask {
976 u32 amask;
977 u32 res[0x2];
978};
979
980struct fsl_ifc_csor {
981 u32 csor;
982 u32 csor_ext;
983 u32 res;
984};
985
986struct fsl_ifc_ftim {
987 u32 ftim[4];
988 u32 res[0x8];
989};
990
991
992
993
994
995
996struct fsl_ifc_fcm {
997 u32 ifc_rev;
998 u32 res1[0x2];
999 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1000 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
1001 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1002 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
1003 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1004 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
1005 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1006 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
1007 u32 rb_stat;
1008 u32 rb_map;
1009 u32 wp_map;
1010 u32 ifc_gcr;
1011 u32 res7[0x2];
1012 u32 cm_evter_stat;
1013 u32 res8[0x2];
1014 u32 cm_evter_en;
1015 u32 res9[0x2];
1016 u32 cm_evter_intr_en;
1017 u32 res10[0x2];
1018 u32 cm_erattr0;
1019 u32 cm_erattr1;
1020 u32 res11[0x2];
1021 u32 ifc_ccr;
1022 u32 ifc_csr;
1023 u32 ddr_ccr_low;
1024};
1025
1026struct fsl_ifc_runtime {
1027 struct fsl_ifc_nand ifc_nand;
1028 struct fsl_ifc_nor ifc_nor;
1029 struct fsl_ifc_gpcm ifc_gpcm;
1030};
1031
1032struct fsl_ifc {
1033 struct fsl_ifc_fcm *gregs;
1034 struct fsl_ifc_runtime *rregs;
1035};
1036
1037struct ifc_regs {
1038 const char *name;
1039 u32 pr;
1040 u32 pr_ext;
1041 u32 amask;
1042 u32 or;
1043 u32 ftim[4];
1044 u32 or_ext;
1045 u32 pr_final;
1046 u32 amask_final;
1047};
1048
1049struct ifc_regs_info {
1050 struct ifc_regs *regs;
1051 u32 cs_size;
1052};
1053
1054#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
1055#undef CSPR_MSEL_NOR
1056#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
1057#endif
1058#endif
1059
1060#endif
1061#endif
1062