LXR uboot/include/fsl

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Common internal memory map for some Freescale SoCs
   4 *
   5 * Copyright 2014 Freescale Semiconductor, Inc.
   6 * Copyright 2018 NXP
   7 */
   8
   9#ifndef __FSL_SEC_H
  10#define __FSL_SEC_H
  11
  12#include <common.h>
  13#include <asm/io.h>
  14
  15#ifdef CONFIG_SYS_FSL_SEC_LE
  16#define sec_in32(a)       in_le32((ulong *)(ulong)a)
  17#define sec_out32(a, v)   out_le32((ulong *)(ulong)a, v)
  18#define sec_in16(a)       in_le16(a)
  19#define sec_clrbits32     clrbits_le32
  20#define sec_setbits32     setbits_le32
  21#elif defined(CONFIG_SYS_FSL_SEC_BE)
  22#define sec_in32(a)       in_be32(a)
  23#define sec_out32(a, v)   out_be32(a, v)
  24#define sec_in16(a)       in_be16(a)
  25#define sec_clrbits32     clrbits_be32
  26#define sec_setbits32     setbits_be32
  27#elif defined(CONFIG_SYS_FSL_HAS_SEC)
  28#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  29#endif
  30
  31#define BLOB_SIZE(x)            ((x) + 32 + 16) /* Blob buffer size */
  32
  33/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  34#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  35/* RNG4 TRNG test registers */
  36struct rng4tst {
  37#define RTMCTL_PRGM 0x00010000  /* 1 -> program mode, 0 -> run mode */
  38#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
  39                                                    both entropy shifter and
  40                                                    statistical checker */
  41#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
  42                                                    entropy shifter and
  43                                                    statistical checker */
  44#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  45                                                    entropy shifter, raw data
  46                                                    in statistical checker */
  47#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
  48        u32 rtmctl;             /* misc. control register */
  49        u32 rtscmisc;           /* statistical check misc. register */
  50        u32 rtpkrrng;           /* poker range register */
  51#define RTSDCTL_ENT_DLY_MIN     3200
  52#define RTSDCTL_ENT_DLY_MAX     12800
  53        union {
  54                u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
  55                u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
  56        };
  57#define RTSDCTL_ENT_DLY_SHIFT 16
  58#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  59        u32 rtsdctl;            /* seed control register */
  60        union {
  61                u32 rtsblim;    /* PRGM=1: sparse bit limit register */
  62                u32 rttotsam;   /* PRGM=0: total samples register */
  63        };
  64        u32 rtfreqmin;          /* frequency count min. limit register */
  65#define RTFRQMAX_DISABLE       (1 << 20)
  66        union {
  67                u32 rtfreqmax;  /* PRGM=1: freq. count max. limit register */
  68                u32 rtfreqcnt;  /* PRGM=0: freq. count register */
  69        };
  70        u32 rsvd1[40];
  71#define RDSTA_IF(idx) (0x00000001 << (idx))
  72#define RDSTA_PR(idx) (0x00000010 << (idx))
  73#define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0))
  74#define RDSTA_SKVN 0x40000000
  75        u32 rdsta;              /*RNG DRNG Status Register*/
  76        u32 rsvd2[15];
  77};
  78
  79/* Version registers (Era 10+) */
  80struct version_regs {
  81        u32 crca;       /* CRCA_VERSION */
  82        u32 afha;       /* AFHA_VERSION */
  83        u32 kfha;       /* KFHA_VERSION */
  84        u32 pkha;       /* PKHA_VERSION */
  85        u32 aesa;       /* AESA_VERSION */
  86        u32 mdha;       /* MDHA_VERSION */
  87        u32 desa;       /* DESA_VERSION */
  88        u32 snw8a;      /* SNW8A_VERSION */
  89        u32 snw9a;      /* SNW9A_VERSION */
  90        u32 zuce;       /* ZUCE_VERSION */
  91        u32 zuca;       /* ZUCA_VERSION */
  92        u32 ccha;       /* CCHA_VERSION */
  93        u32 ptha;       /* PTHA_VERSION */
  94        u32 rng;        /* RNG_VERSION */
  95        u32 trng;       /* TRNG_VERSION */
  96        u32 aaha;       /* AAHA_VERSION */
  97        u32 rsvd[10];
  98        u32 sr;         /* SR_VERSION */
  99        u32 dma;        /* DMA_VERSION */
 100        u32 ai;         /* AI_VERSION */
 101        u32 qi;         /* QI_VERSION */
 102        u32 jr;         /* JR_VERSION */
 103        u32 deco;       /* DECO_VERSION */
 104};
 105
 106#define CHA_VER_NUM_MASK        0x000000ff
 107#define CHA_VER_MISC_SHIFT      8
 108#define CHA_VER_MISC_MASK       0x0000ff00
 109#define CHA_VER_REV_SHIFT       16
 110#define CHA_VER_REV_MASK        0x00ff0000
 111#define CHA_VER_VID_SHIFT       24
 112#define CHA_VER_VID_MASK        0xff000000
 113
 114typedef struct ccsr_sec {
 115        u32     res0;
 116        u32     mcfgr;          /* Master CFG Register */
 117        u8      res1[0x4];
 118        u32     scfgr;
 119        struct {
 120                u32     ms;     /* Job Ring LIODN Register, MS */
 121                u32     ls;     /* Job Ring LIODN Register, LS */
 122        } jrliodnr[4];
 123        u8      res2[0x2c];
 124        u32     jrstartr;       /* Job Ring Start Register */
 125        struct {
 126                u32     ms;     /* RTIC LIODN Register, MS */
 127                u32     ls;     /* RTIC LIODN Register, LS */
 128        } rticliodnr[4];
 129        u8      res3[0x1c];
 130        u32     decorr;         /* DECO Request Register */
 131        struct {
 132                u32     ms;     /* DECO LIODN Register, MS */
 133                u32     ls;     /* DECO LIODN Register, LS */
 134        } decoliodnr[16];
 135        u32     dar;            /* DECO Avail Register */
 136        u32     drr;            /* DECO Reset Register */
 137        u8      res5[0x4d8];
 138        struct rng4tst rng;     /* RNG Registers */
 139        u8      res6[0x780];
 140        struct version_regs vreg; /* version registers since era 10 */
 141        u8      res7[0xa0];
 142        u32     crnr_ms;        /* CHA Revision Number Register, MS */
 143        u32     crnr_ls;        /* CHA Revision Number Register, LS */
 144        u32     ctpr_ms;        /* Compile Time Parameters Register, MS */
 145        u32     ctpr_ls;        /* Compile Time Parameters Register, LS */
 146        u8      res8[0x10];
 147        u32     far_ms;         /* Fault Address Register, MS */
 148        u32     far_ls;         /* Fault Address Register, LS */
 149        u32     falr;           /* Fault Address LIODN Register */
 150        u32     fadr;           /* Fault Address Detail Register */
 151        u8      res9[0x4];
 152        u32     csta;           /* CAAM Status Register */
 153        u32     smpart;         /* Secure Memory Partition Parameters */
 154        u32     smvid;          /* Secure Memory Version ID */
 155        u32     rvid;           /* Run Time Integrity Checking Version ID Reg.*/
 156        u32     ccbvid;         /* CHA Cluster Block Version ID Register */
 157        u32     chavid_ms;      /* CHA Version ID Register, MS */
 158        u32     chavid_ls;      /* CHA Version ID Register, LS */
 159        u32     chanum_ms;      /* CHA Number Register, MS */
 160        u32     chanum_ls;      /* CHA Number Register, LS */
 161        u32     secvid_ms;      /* SEC Version ID Register, MS */
 162        u32     secvid_ls;      /* SEC Version ID Register, LS */
 163#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
 164        u8      res10[0x6f020];
 165#else
 166        u8      res10[0x6020];
 167#endif
 168        u32     qilcr_ms;       /* Queue Interface LIODN CFG Register, MS */
 169        u32     qilcr_ls;       /* Queue Interface LIODN CFG Register, LS */
 170#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
 171        u8      res11[0x8ffd8];
 172#else
 173        u8      res11[0x8fd8];
 174#endif
 175} ccsr_sec_t;
 176
 177#define SEC_CTPR_MS_AXI_LIODN           0x08000000
 178#define SEC_CTPR_MS_QI                  0x02000000
 179#define SEC_CTPR_MS_VIRT_EN_INCL        0x00000001
 180#define SEC_CTPR_MS_VIRT_EN_POR         0x00000002
 181#define SEC_RVID_MA                     0x0f000000
 182#define SEC_CHANUM_MS_JRNUM_MASK        0xf0000000
 183#define SEC_CHANUM_MS_JRNUM_SHIFT       28
 184#define SEC_CHANUM_MS_DECONUM_MASK      0x0f000000
 185#define SEC_CHANUM_MS_DECONUM_SHIFT     24
 186#define SEC_SECVID_MS_IPID_MASK 0xffff0000
 187#define SEC_SECVID_MS_IPID_SHIFT        16
 188#define SEC_SECVID_MS_MAJ_REV_MASK      0x0000ff00
 189#define SEC_SECVID_MS_MAJ_REV_SHIFT     8
 190#define SEC_CCBVID_ERA_MASK             0xff000000
 191#define SEC_CCBVID_ERA_SHIFT            24
 192#define SEC_SCFGR_RDBENABLE             0x00000400
 193#define SEC_SCFGR_VIRT_EN               0x00008000
 194#define SEC_CHAVID_LS_RNG_SHIFT         16
 195#define SEC_CHAVID_RNG_LS_MASK          0x000f0000
 196
 197#define CONFIG_JRSTARTR_JR0             0x00000001
 198
 199struct jr_regs {
 200#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 201        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
 202          defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
 203        u32 irba_l;
 204        u32 irba_h;
 205#else
 206        u32 irba_h;
 207        u32 irba_l;
 208#endif
 209        u32 rsvd1;
 210        u32 irs;
 211        u32 rsvd2;
 212        u32 irsa;
 213        u32 rsvd3;
 214        u32 irja;
 215#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 216        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
 217          defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
 218        u32 orba_l;
 219        u32 orba_h;
 220#else
 221        u32 orba_h;
 222        u32 orba_l;
 223#endif
 224        u32 rsvd4;
 225        u32 ors;
 226        u32 rsvd5;
 227        u32 orjr;
 228        u32 rsvd6;
 229        u32 orsf;
 230        u32 rsvd7;
 231        u32 jrsta;
 232        u32 rsvd8;
 233        u32 jrint;
 234        u32 jrcfg0;
 235        u32 jrcfg1;
 236        u32 rsvd9;
 237        u32 irri;
 238        u32 rsvd10;
 239        u32 orwi;
 240        u32 rsvd11;
 241        u32 jrcr;
 242};
 243
 244/*
 245 * Scatter Gather Entry - Specifies the the Scatter Gather Format
 246 * related information
 247 */
 248struct sg_entry {
 249#if defined(CONFIG_SYS_FSL_SEC_LE) && \
 250        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
 251          defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
 252        uint32_t addr_lo;       /* Memory Address - lo */
 253        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 254#else
 255        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 256        uint32_t addr_lo;       /* Memory Address - lo */
 257#endif
 258
 259        uint32_t len_flag;      /* Length of the data in the frame */
 260#define SG_ENTRY_LENGTH_MASK    0x3FFFFFFF
 261#define SG_ENTRY_EXTENSION_BIT  0x80000000
 262#define SG_ENTRY_FINAL_BIT      0x40000000
 263        uint32_t bpid_offset;
 264#define SG_ENTRY_BPID_MASK      0x00FF0000
 265#define SG_ENTRY_BPID_SHIFT     16
 266#define SG_ENTRY_OFFSET_MASK    0x00001FFF
 267#define SG_ENTRY_OFFSET_SHIFT   0
 268};
 269
 270#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
 271        defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
 272/* Job Ring Base Address */
 273#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
 274/* Secure Memory Offset varies accross versions */
 275#define SM_V1_OFFSET 0x0f4
 276#define SM_V2_OFFSET 0xa00
 277/*Secure Memory Versioning */
 278#define SMVID_V2 0x20105
 279#define SM_VERSION(x)  ({typeof(x) _x = x; \
 280                _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); })
 281#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
 282/* CAAM Job Ring 0 Registers */
 283/* Secure Memory Partition Owner register */
 284#define SMCSJR_PO               (3 << 6)
 285/* JR Allocation Error */
 286#define SMCSJR_AERR             (3 << 12)
 287/* Secure memory partition 0 page 0 owner register */
 288#define CAAM_SMPO_0         (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
 289/* Secure memory command register */
 290#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
 291/* Secure memory command status register */
 292#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
 293/* Secure memory access permissions register */
 294#define CAAM_SMAPJR(v, jr, y) \
 295        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
 296/* Secure memory access group 2 register */
 297#define CAAM_SMAG2JR(v, jr, y) \
 298        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
 299/* Secure memory access group 1 register */
 300#define CAAM_SMAG1JR(v, jr, y)  \
 301        (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
 302
 303/* Commands and macros for secure memory */
 304#define SM_CMD(v)               (v == 1 ? 0x0 : 0x1E4)
 305#define SM_STATUS(v)            (v == 1 ? 0x8 : 0x1EC)
 306#define SM_PERM(v)              (v == 1 ?  0x10 : 0x4)
 307#define SM_GROUP2(v)            ({typeof(v) _v = v; \
 308                _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); })
 309#define SM_GROUP1(v)            ({typeof(v) _v = v; \
 310                _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); })
 311#define CMD_PAGE_ALLOC          0x1
 312#define CMD_PAGE_DEALLOC        0x2
 313#define CMD_PART_DEALLOC        0x3
 314#define CMD_INQUIRY             0x5
 315#define CMD_COMPLETE            (3 << 14)
 316#define PAGE_AVAILABLE          0
 317#define PAGE_OWNED              (3 << 6)
 318#define PAGE(x)                 (x << 16)
 319#define PARTITION(x)            (x << 8)
 320#define PARTITION_OWNER(x)      (0x3 << (x*2))
 321
 322/* Address of secure 4kbyte pages */
 323#define SEC_MEM_PAGE0           CAAM_ARB_BASE_ADDR
 324#define SEC_MEM_PAGE1           (CAAM_ARB_BASE_ADDR + 0x1000)
 325#define SEC_MEM_PAGE2           (CAAM_ARB_BASE_ADDR + 0x2000)
 326#define SEC_MEM_PAGE3           (CAAM_ARB_BASE_ADDR + 0x3000)
 327
 328#ifdef CONFIG_IMX8M
 329#define JR_MID    (1)         /* Matches ATF configuration */
 330#define KS_G1     (0x10000 << JR_MID) /* CAAM only */
 331#define PERM      (0xB080)    /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
 332#else
 333#define JR_MID    (2)         /* Matches ROM configuration */
 334#define KS_G1     BIT(JR_MID) /* CAAM only */
 335#define PERM      (0xB008)    /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
 336#endif /* CONFIG_IMX8M */
 337
 338/* HAB WRAPPED KEY header */
 339#define WRP_HDR_SIZE            0x08
 340#define HDR_TAG                 0x81
 341#define HDR_PAR                 0x41
 342/* HAB WRAPPED KEY Data */
 343#define HAB_MOD                 0x66
 344#define HAB_ALG                 0x55
 345#define HAB_FLG                 0x00
 346
 347/* Partition and Page IDs */
 348#define PARTITION_1     1
 349#define PAGE_1                  1
 350
 351#define ERROR_IN_PAGE_ALLOC     1
 352#define ECONSTRJDESC   -1
 353
 354#endif
 355
 356#define FSL_CAAM_MP_PUBK_BYTES              64
 357#define FSL_CAAM_MP_PRVK_BYTES              32
 358#define FSL_CAAM_MP_MES_DGST_BYTES          32
 359
 360#define FSL_CAAM_ORSR_JRa_OFFSET        0x102c
 361#define FSL_CAAM_MAX_JR_SIZE            4
 362
 363/* blob_dek:
 364 * Encapsulates the src in a secure blob and stores it dst
 365 * @src: reference to the plaintext
 366 * @dst: reference to the output adrress
 367 * @len: size in bytes of src
 368 * @return: 0 on success, error otherwise
 369 */
 370int blob_dek(const u8 *src, u8 *dst, u8 len);
 371
 372int gen_mppubk(u8 *dst);
 373
 374int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d);
 375
 376#if defined(CONFIG_ARCH_C29X)
 377int sec_init_idx(uint8_t);
 378#endif
 379int sec_init(void);
 380
 381u8 caam_get_era(void);
 382#endif
 383
 384#endif /* __FSL_SEC_H */
 385