1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Common internal memory map for some Freescale SoCs 4 * 5 * Copyright 2015 Freescale Semiconductor, Inc. 6 */ 7 8#ifndef __FSL_SEC_MON_H 9#define __FSL_SEC_MON_H 10 11#include <common.h> 12#include <asm/io.h> 13 14#ifdef CONFIG_SYS_FSL_SEC_MON_LE 15#define sec_mon_in32(a) in_le32(a) 16#define sec_mon_out32(a, v) out_le32(a, v) 17#define sec_mon_in16(a) in_le16(a) 18#define sec_mon_clrbits32 clrbits_le32 19#define sec_mon_setbits32 setbits_le32 20#elif defined(CONFIG_SYS_FSL_SEC_MON_BE) 21#define sec_mon_in32(a) in_be32(a) 22#define sec_mon_out32(a, v) out_be32(a, v) 23#define sec_mon_in16(a) in_be16(a) 24#define sec_mon_clrbits32 clrbits_be32 25#define sec_mon_setbits32 setbits_be32 26#else 27#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined 28#endif 29 30struct ccsr_sec_mon_regs { 31 u8 reserved0[0x04]; 32 u32 hp_com; /* 0x04 SEC_MON_HP Command Register */ 33 u8 reserved2[0x0c]; 34 u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ 35}; 36 37#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ 38#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ 39#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ 40#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ 41#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ 42#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ 43#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ 44#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ 45#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ 46#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ 47#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ 48 49/* 50 * SEC_MON read. This specifies the possible reads 51 * from the SEC_MON 52 */ 53enum { 54 SEC_MON_SSM_ST, 55 SEC_MON_SW_FSV, 56 SEC_MON_SW_SV, 57}; 58 59/* Transition SEC_MON state */ 60int set_sec_mon_state(u32 state); 61 62#endif /* __FSL_SEC_MON_H */ 63