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13#ifndef __LINUX_MTD_RAWNAND_H
14#define __LINUX_MTD_RAWNAND_H
15
16#include <config.h>
17
18#include <dm/device.h>
19#include <linux/bitops.h>
20#include <linux/compat.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/flashchip.h>
23#include <linux/mtd/bbm.h>
24#include <asm/cache.h>
25
26struct mtd_info;
27struct nand_chip;
28struct nand_flash_dev;
29struct device_node;
30
31
32struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
33 struct nand_chip *chip,
34 int *maf_id, int *dev_id,
35 struct nand_flash_dev *type);
36
37
38int nand_scan(struct mtd_info *mtd, int max_chips);
39
40
41
42
43int nand_scan_ident(struct mtd_info *mtd, int max_chips,
44 struct nand_flash_dev *table);
45int nand_scan_tail(struct mtd_info *mtd);
46
47
48void nand_release(struct mtd_info *mtd);
49
50
51void nand_wait_ready(struct mtd_info *mtd);
52
53
54
55
56
57
58#define NAND_MAX_OOBSIZE 1664
59#define NAND_MAX_PAGESIZE 16384
60
61
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64
65
66
67
68#define NAND_NCE 0x01
69
70#define NAND_CLE 0x02
71
72#define NAND_ALE 0x04
73
74#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
75#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
76#define NAND_CTRL_CHANGE 0x80
77
78
79
80
81#define NAND_CMD_READ0 0
82#define NAND_CMD_READ1 1
83#define NAND_CMD_RNDOUT 5
84#define NAND_CMD_PAGEPROG 0x10
85#define NAND_CMD_READOOB 0x50
86#define NAND_CMD_ERASE1 0x60
87#define NAND_CMD_STATUS 0x70
88#define NAND_CMD_SEQIN 0x80
89#define NAND_CMD_RNDIN 0x85
90#define NAND_CMD_READID 0x90
91#define NAND_CMD_ERASE2 0xd0
92#define NAND_CMD_PARAM 0xec
93#define NAND_CMD_GET_FEATURES 0xee
94#define NAND_CMD_SET_FEATURES 0xef
95#define NAND_CMD_RESET 0xff
96
97#define NAND_CMD_LOCK 0x2a
98#define NAND_CMD_UNLOCK1 0x23
99#define NAND_CMD_UNLOCK2 0x24
100
101
102#define NAND_CMD_READSTART 0x30
103#define NAND_CMD_RNDOUTSTART 0xE0
104#define NAND_CMD_CACHEDPROG 0x15
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111
112
113#define NAND_CMD_DEPLETE1 0x100
114#define NAND_CMD_DEPLETE2 0x38
115#define NAND_CMD_STATUS_MULTI 0x71
116#define NAND_CMD_STATUS_ERROR 0x72
117
118#define NAND_CMD_STATUS_ERROR0 0x73
119#define NAND_CMD_STATUS_ERROR1 0x74
120#define NAND_CMD_STATUS_ERROR2 0x75
121#define NAND_CMD_STATUS_ERROR3 0x76
122#define NAND_CMD_STATUS_RESET 0x7f
123#define NAND_CMD_STATUS_CLEAR 0xff
124
125#define NAND_CMD_NONE -1
126
127
128#define NAND_STATUS_FAIL 0x01
129#define NAND_STATUS_FAIL_N1 0x02
130#define NAND_STATUS_TRUE_READY 0x20
131#define NAND_STATUS_READY 0x40
132#define NAND_STATUS_WP 0x80
133
134#define NAND_DATA_IFACE_CHECK_ONLY -1
135
136
137
138
139typedef enum {
140 NAND_ECC_NONE,
141 NAND_ECC_SOFT,
142 NAND_ECC_HW,
143 NAND_ECC_HW_SYNDROME,
144 NAND_ECC_HW_OOB_FIRST,
145 NAND_ECC_SOFT_BCH,
146} nand_ecc_modes_t;
147
148enum nand_ecc_algo {
149 NAND_ECC_UNKNOWN,
150 NAND_ECC_HAMMING,
151 NAND_ECC_BCH,
152};
153
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156
157
158#define NAND_ECC_READ 0
159
160#define NAND_ECC_WRITE 1
161
162#define NAND_ECC_READSYN 2
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169
170#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
171#define NAND_ECC_MAXIMIZE BIT(1)
172
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175
176
177#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
178
179
180#define NAND_GET_DEVICE 0x80
181
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185
186
187
188#define NAND_BUSWIDTH_16 0x00000002
189
190#define NAND_NO_PADDING 0x00000004
191
192#define NAND_CACHEPRG 0x00000008
193
194#define NAND_COPYBACK 0x00000010
195
196
197
198
199
200#define NAND_NEED_READRDY 0x00000100
201
202
203#define NAND_NO_SUBPAGE_WRITE 0x00000200
204
205
206#define NAND_BROKEN_XD 0x00000400
207
208
209#define NAND_ROM 0x00000800
210
211
212#define NAND_SUBPAGE_READ 0x00001000
213
214
215
216
217
218#define NAND_NEED_SCRAMBLING 0x00002000
219
220
221#define NAND_ROW_ADDR_3 0x00004000
222
223
224#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
225
226
227#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
228#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
229#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
230
231
232
233#define NAND_SKIP_BBTSCAN 0x00010000
234
235
236
237
238#define NAND_OWN_BUFFERS 0x00020000
239
240#define NAND_SCAN_SILENT_NODEV 0x00040000
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245
246
247#define NAND_BUSWIDTH_AUTO 0x00080000
248
249
250
251
252#define NAND_USE_BOUNCE_BUFFER 0x00100000
253
254
255
256#define NAND_BBT_SCANNED 0x40000000
257
258#define NAND_CONTROLLER_ALLOC 0x80000000
259
260
261#define NAND_CI_CHIPNR_MSK 0x03
262#define NAND_CI_CELLTYPE_MSK 0x0C
263#define NAND_CI_CELLTYPE_SHIFT 2
264
265
266#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
267#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
268
269
270#define ONFI_TIMING_MODE_0 (1 << 0)
271#define ONFI_TIMING_MODE_1 (1 << 1)
272#define ONFI_TIMING_MODE_2 (1 << 2)
273#define ONFI_TIMING_MODE_3 (1 << 3)
274#define ONFI_TIMING_MODE_4 (1 << 4)
275#define ONFI_TIMING_MODE_5 (1 << 5)
276#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
277
278
279#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
280
281
282#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
283
284
285#define ONFI_SUBFEATURE_PARAM_LEN 4
286
287
288#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
289
290struct nand_onfi_params {
291
292
293 u8 sig[4];
294 __le16 revision;
295 __le16 features;
296 __le16 opt_cmd;
297 u8 reserved0[2];
298 __le16 ext_param_page_length;
299 u8 num_of_param_pages;
300 u8 reserved1[17];
301
302
303 char manufacturer[12];
304 char model[20];
305 u8 jedec_id;
306 __le16 date_code;
307 u8 reserved2[13];
308
309
310 __le32 byte_per_page;
311 __le16 spare_bytes_per_page;
312 __le32 data_bytes_per_ppage;
313 __le16 spare_bytes_per_ppage;
314 __le32 pages_per_block;
315 __le32 blocks_per_lun;
316 u8 lun_count;
317 u8 addr_cycles;
318 u8 bits_per_cell;
319 __le16 bb_per_lun;
320 __le16 block_endurance;
321 u8 guaranteed_good_blocks;
322 __le16 guaranteed_block_endurance;
323 u8 programs_per_page;
324 u8 ppage_attr;
325 u8 ecc_bits;
326 u8 interleaved_bits;
327 u8 interleaved_ops;
328 u8 reserved3[13];
329
330
331 u8 io_pin_capacitance_max;
332 __le16 async_timing_mode;
333 __le16 program_cache_timing_mode;
334 __le16 t_prog;
335 __le16 t_bers;
336 __le16 t_r;
337 __le16 t_ccs;
338 __le16 src_sync_timing_mode;
339 u8 src_ssync_features;
340 __le16 clk_pin_capacitance_typ;
341 __le16 io_pin_capacitance_typ;
342 __le16 input_pin_capacitance_typ;
343 u8 input_pin_capacitance_max;
344 u8 driver_strength_support;
345 __le16 t_int_r;
346 __le16 t_adl;
347 u8 reserved4[8];
348
349
350 __le16 vendor_revision;
351 u8 vendor[88];
352
353 __le16 crc;
354} __packed;
355
356#define ONFI_CRC_BASE 0x4F4E
357
358
359struct onfi_ext_ecc_info {
360 u8 ecc_bits;
361 u8 codeword_size;
362 __le16 bb_per_lun;
363 __le16 block_endurance;
364 u8 reserved[2];
365} __packed;
366
367#define ONFI_SECTION_TYPE_0 0
368#define ONFI_SECTION_TYPE_1 1
369#define ONFI_SECTION_TYPE_2 2
370struct onfi_ext_section {
371 u8 type;
372 u8 length;
373} __packed;
374
375#define ONFI_EXT_SECTION_MAX 8
376
377
378struct onfi_ext_param_page {
379 __le16 crc;
380 u8 sig[4];
381 u8 reserved0[10];
382 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
383
384
385
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388
389
390} __packed;
391
392struct nand_onfi_vendor_micron {
393 u8 two_plane_read;
394 u8 read_cache;
395 u8 read_unique_id;
396 u8 dq_imped;
397 u8 dq_imped_num_settings;
398 u8 dq_imped_feat_addr;
399 u8 rb_pulldown_strength;
400 u8 rb_pulldown_strength_feat_addr;
401 u8 rb_pulldown_strength_num_settings;
402 u8 otp_mode;
403 u8 otp_page_start;
404 u8 otp_data_prot_addr;
405 u8 otp_num_pages;
406 u8 otp_feat_addr;
407 u8 read_retry_options;
408 u8 reserved[72];
409 u8 param_revision;
410} __packed;
411
412struct jedec_ecc_info {
413 u8 ecc_bits;
414 u8 codeword_size;
415 __le16 bb_per_lun;
416 __le16 block_endurance;
417 u8 reserved[2];
418} __packed;
419
420
421#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
422
423struct nand_jedec_params {
424
425
426 u8 sig[4];
427 __le16 revision;
428 __le16 features;
429 u8 opt_cmd[3];
430 __le16 sec_cmd;
431 u8 num_of_param_pages;
432 u8 reserved0[18];
433
434
435 char manufacturer[12];
436 char model[20];
437 u8 jedec_id[6];
438 u8 reserved1[10];
439
440
441 __le32 byte_per_page;
442 __le16 spare_bytes_per_page;
443 u8 reserved2[6];
444 __le32 pages_per_block;
445 __le32 blocks_per_lun;
446 u8 lun_count;
447 u8 addr_cycles;
448 u8 bits_per_cell;
449 u8 programs_per_page;
450 u8 multi_plane_addr;
451 u8 multi_plane_op_attr;
452 u8 reserved3[38];
453
454
455 __le16 async_sdr_speed_grade;
456 __le16 toggle_ddr_speed_grade;
457 __le16 sync_ddr_speed_grade;
458 u8 async_sdr_features;
459 u8 toggle_ddr_features;
460 u8 sync_ddr_features;
461 __le16 t_prog;
462 __le16 t_bers;
463 __le16 t_r;
464 __le16 t_r_multi_plane;
465 __le16 t_ccs;
466 __le16 io_pin_capacitance_typ;
467 __le16 input_pin_capacitance_typ;
468 __le16 clk_pin_capacitance_typ;
469 u8 driver_strength_support;
470 __le16 t_adl;
471 u8 reserved4[36];
472
473
474 u8 guaranteed_good_blocks;
475 __le16 guaranteed_block_endurance;
476 struct jedec_ecc_info ecc_info[4];
477 u8 reserved5[29];
478
479
480 u8 reserved6[148];
481
482
483 __le16 vendor_rev_num;
484 u8 reserved7[88];
485
486
487 __le16 crc;
488} __packed;
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497
498struct nand_hw_control {
499 spinlock_t lock;
500 struct nand_chip *active;
501};
502
503static inline void nand_hw_control_init(struct nand_hw_control *nfc)
504{
505 nfc->active = NULL;
506 spin_lock_init(&nfc->lock);
507 init_waitqueue_head(&nfc->wq);
508}
509
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515
516struct nand_ecc_step_info {
517 int stepsize;
518 const int *strengths;
519 int nstrengths;
520};
521
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527
528struct nand_ecc_caps {
529 const struct nand_ecc_step_info *stepinfos;
530 int nstepinfos;
531 int (*calc_ecc_bytes)(int step_size, int strength);
532};
533
534
535#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
536static const int __name##_strengths[] = { __VA_ARGS__ }; \
537static const struct nand_ecc_step_info __name##_stepinfo = { \
538 .stepsize = __step, \
539 .strengths = __name##_strengths, \
540 .nstrengths = ARRAY_SIZE(__name##_strengths), \
541}; \
542static const struct nand_ecc_caps __name = { \
543 .stepinfos = &__name##_stepinfo, \
544 .nstepinfos = 1, \
545 .calc_ecc_bytes = __calc, \
546}
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600struct nand_ecc_ctrl {
601 nand_ecc_modes_t mode;
602 enum nand_ecc_algo algo;
603 int steps;
604 int size;
605 int bytes;
606 int total;
607 int strength;
608 int prepad;
609 int postpad;
610 unsigned int options;
611 struct nand_ecclayout *layout;
612 void *priv;
613 void (*hwctl)(struct mtd_info *mtd, int mode);
614 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
615 uint8_t *ecc_code);
616 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
617 uint8_t *calc_ecc);
618 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
619 uint8_t *buf, int oob_required, int page);
620 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
621 const uint8_t *buf, int oob_required, int page);
622 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
623 uint8_t *buf, int oob_required, int page);
624 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
625 uint32_t offs, uint32_t len, uint8_t *buf, int page);
626 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
627 uint32_t offset, uint32_t data_len,
628 const uint8_t *data_buf, int oob_required, int page);
629 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
630 const uint8_t *buf, int oob_required, int page);
631 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
632 int page);
633 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
634 int page);
635 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
636 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
637 int page);
638};
639
640static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
641{
642 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
643}
644
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651
652
653
654struct nand_buffers {
655 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
656 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
657 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
658 ARCH_DMA_MINALIGN)];
659};
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712struct nand_sdr_timings {
713 u64 tBERS_max;
714 u32 tCCS_min;
715 u64 tPROG_max;
716 u64 tR_max;
717 u32 tALH_min;
718 u32 tADL_min;
719 u32 tALS_min;
720 u32 tAR_min;
721 u32 tCEA_max;
722 u32 tCEH_min;
723 u32 tCH_min;
724 u32 tCHZ_max;
725 u32 tCLH_min;
726 u32 tCLR_min;
727 u32 tCLS_min;
728 u32 tCOH_min;
729 u32 tCS_min;
730 u32 tDH_min;
731 u32 tDS_min;
732 u32 tFEAT_max;
733 u32 tIR_min;
734 u32 tITC_max;
735 u32 tRC_min;
736 u32 tREA_max;
737 u32 tREH_min;
738 u32 tRHOH_min;
739 u32 tRHW_min;
740 u32 tRHZ_max;
741 u32 tRLOH_min;
742 u32 tRP_min;
743 u32 tRR_min;
744 u64 tRST_max;
745 u32 tWB_max;
746 u32 tWC_min;
747 u32 tWH_min;
748 u32 tWHR_min;
749 u32 tWP_min;
750 u32 tWW_min;
751};
752
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755
756
757enum nand_data_interface_type {
758 NAND_SDR_IFACE,
759};
760
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764
765
766struct nand_data_interface {
767 enum nand_data_interface_type type;
768 union {
769 struct nand_sdr_timings sdr;
770 } timings;
771};
772
773
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775
776
777static inline const struct nand_sdr_timings *
778nand_get_sdr_timings(const struct nand_data_interface *conf)
779{
780 if (conf->type != NAND_SDR_IFACE)
781 return ERR_PTR(-EINVAL);
782
783 return &conf->timings.sdr;
784}
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889struct nand_chip {
890 struct mtd_info mtd;
891 void __iomem *IO_ADDR_R;
892 void __iomem *IO_ADDR_W;
893
894 ofnode flash_node;
895
896 uint8_t (*read_byte)(struct mtd_info *mtd);
897 u16 (*read_word)(struct mtd_info *mtd);
898 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
899 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
900 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
901 void (*select_chip)(struct mtd_info *mtd, int chip);
902 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
903 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
904 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
905 int (*dev_ready)(struct mtd_info *mtd);
906 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
907 int page_addr);
908 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
909 int (*erase)(struct mtd_info *mtd, int page);
910 int (*scan_bbt)(struct mtd_info *mtd);
911 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
912 uint32_t offset, int data_len, const uint8_t *buf,
913 int oob_required, int page, int raw);
914 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
915 int feature_addr, uint8_t *subfeature_para);
916 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
917 int feature_addr, uint8_t *subfeature_para);
918 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
919 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
920 const struct nand_data_interface *conf);
921
922
923 int chip_delay;
924 unsigned int options;
925 unsigned int bbt_options;
926
927 int page_shift;
928 int phys_erase_shift;
929 int bbt_erase_shift;
930 int chip_shift;
931 int numchips;
932 uint64_t chipsize;
933 int pagemask;
934 int pagebuf;
935 unsigned int pagebuf_bitflips;
936 int subpagesize;
937 uint8_t bits_per_cell;
938 uint16_t ecc_strength_ds;
939 uint16_t ecc_step_ds;
940 int onfi_timing_mode_default;
941 int badblockpos;
942 int badblockbits;
943
944 int onfi_version;
945 int jedec_version;
946 struct nand_onfi_params onfi_params;
947 struct nand_jedec_params jedec_params;
948
949 struct nand_data_interface *data_interface;
950
951 int read_retries;
952
953 flstate_t state;
954
955 uint8_t *oob_poi;
956 struct nand_hw_control *controller;
957 struct nand_ecclayout *ecclayout;
958
959 struct nand_ecc_ctrl ecc;
960 struct nand_buffers *buffers;
961 unsigned long buf_align;
962 struct nand_hw_control hwcontrol;
963
964 uint8_t *bbt;
965 struct nand_bbt_descr *bbt_td;
966 struct nand_bbt_descr *bbt_md;
967
968 struct nand_bbt_descr *badblock_pattern;
969
970 void *priv;
971};
972
973static inline void nand_set_flash_node(struct nand_chip *chip,
974 ofnode node)
975{
976 chip->flash_node = node;
977}
978
979static inline ofnode nand_get_flash_node(struct nand_chip *chip)
980{
981 return chip->flash_node;
982}
983
984static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
985{
986 return container_of(mtd, struct nand_chip, mtd);
987}
988
989static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
990{
991 return &chip->mtd;
992}
993
994static inline void *nand_get_controller_data(struct nand_chip *chip)
995{
996 return chip->priv;
997}
998
999static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1000{
1001 chip->priv = priv;
1002}
1003
1004
1005
1006
1007#define NAND_MFR_TOSHIBA 0x98
1008#define NAND_MFR_SAMSUNG 0xec
1009#define NAND_MFR_FUJITSU 0x04
1010#define NAND_MFR_NATIONAL 0x8f
1011#define NAND_MFR_RENESAS 0x07
1012#define NAND_MFR_STMICRO 0x20
1013#define NAND_MFR_HYNIX 0xad
1014#define NAND_MFR_MICRON 0x2c
1015#define NAND_MFR_AMD 0x01
1016#define NAND_MFR_MACRONIX 0xc2
1017#define NAND_MFR_EON 0x92
1018#define NAND_MFR_SANDISK 0x45
1019#define NAND_MFR_INTEL 0x89
1020#define NAND_MFR_ATO 0x9b
1021
1022
1023#define NAND_MAX_ID_LEN 8
1024
1025
1026
1027
1028
1029
1030#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1031 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1032 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1045 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1046 .options = (opts) }
1047
1048#define NAND_ECC_INFO(_strength, _step) \
1049 { .strength_ds = (_strength), .step_ds = (_step) }
1050#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1051#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
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1070
1071
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1073
1074
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1076
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1079
1080
1081
1082struct nand_flash_dev {
1083 char *name;
1084 union {
1085 struct {
1086 uint8_t mfr_id;
1087 uint8_t dev_id;
1088 };
1089 uint8_t id[NAND_MAX_ID_LEN];
1090 };
1091 unsigned int pagesize;
1092 unsigned int chipsize;
1093 unsigned int erasesize;
1094 unsigned int options;
1095 uint16_t id_len;
1096 uint16_t oobsize;
1097 struct {
1098 uint16_t strength_ds;
1099 uint16_t step_ds;
1100 } ecc;
1101 int onfi_timing_mode_default;
1102};
1103
1104
1105
1106
1107
1108
1109struct nand_manufacturers {
1110 int id;
1111 char *name;
1112};
1113
1114extern struct nand_flash_dev nand_flash_ids[];
1115extern struct nand_manufacturers nand_manuf_ids[];
1116
1117int nand_default_bbt(struct mtd_info *mtd);
1118int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1119int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1120int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1121int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1122 int allowbbt);
1123int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1124 size_t *retlen, uint8_t *buf);
1125
1126
1127
1128
1129#define NAND_SMALL_BADBLOCK_POS 5
1130#define NAND_LARGE_BADBLOCK_POS 0
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143struct platform_nand_chip {
1144 int nr_chips;
1145 int chip_offset;
1146 int nr_partitions;
1147 struct mtd_partition *partitions;
1148 int chip_delay;
1149 unsigned int options;
1150 unsigned int bbt_options;
1151 const char **part_probe_types;
1152};
1153
1154
1155struct platform_device;
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173struct platform_nand_ctrl {
1174 int (*probe)(struct platform_device *pdev);
1175 void (*remove)(struct platform_device *pdev);
1176 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1177 int (*dev_ready)(struct mtd_info *mtd);
1178 void (*select_chip)(struct mtd_info *mtd, int chip);
1179 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1180 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1181 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1182 unsigned char (*read_byte)(struct mtd_info *mtd);
1183 void *priv;
1184};
1185
1186
1187
1188
1189
1190
1191struct platform_nand_data {
1192 struct platform_nand_chip chip;
1193 struct platform_nand_ctrl ctrl;
1194};
1195
1196#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1197
1198static inline int onfi_feature(struct nand_chip *chip)
1199{
1200 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1201}
1202
1203
1204static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1205{
1206 if (!chip->onfi_version)
1207 return ONFI_TIMING_MODE_UNKNOWN;
1208 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1209}
1210
1211
1212static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1213{
1214 if (!chip->onfi_version)
1215 return ONFI_TIMING_MODE_UNKNOWN;
1216 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1217}
1218#else
1219static inline int onfi_feature(struct nand_chip *chip)
1220{
1221 return 0;
1222}
1223
1224static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1225{
1226 return ONFI_TIMING_MODE_UNKNOWN;
1227}
1228
1229static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1230{
1231 return ONFI_TIMING_MODE_UNKNOWN;
1232}
1233#endif
1234
1235int onfi_init_data_interface(struct nand_chip *chip,
1236 struct nand_data_interface *iface,
1237 enum nand_data_interface_type type,
1238 int timing_mode);
1239
1240
1241
1242
1243
1244
1245static inline bool nand_is_slc(struct nand_chip *chip)
1246{
1247 return chip->bits_per_cell == 1;
1248}
1249
1250
1251
1252
1253
1254static inline int nand_opcode_8bits(unsigned int command)
1255{
1256 switch (command) {
1257 case NAND_CMD_READID:
1258 case NAND_CMD_PARAM:
1259 case NAND_CMD_GET_FEATURES:
1260 case NAND_CMD_SET_FEATURES:
1261 return 1;
1262 default:
1263 break;
1264 }
1265 return 0;
1266}
1267
1268
1269static inline int jedec_feature(struct nand_chip *chip)
1270{
1271 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1272 : 0;
1273}
1274
1275
1276void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1277void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1278void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1279void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1280uint8_t nand_read_byte(struct mtd_info *mtd);
1281
1282
1283const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1284
1285const struct nand_data_interface *nand_get_default_data_interface(void);
1286
1287int nand_check_erased_ecc_chunk(void *data, int datalen,
1288 void *ecc, int ecclen,
1289 void *extraoob, int extraooblen,
1290 int threshold);
1291
1292int nand_check_ecc_caps(struct nand_chip *chip,
1293 const struct nand_ecc_caps *caps, int oobavail);
1294
1295int nand_match_ecc_req(struct nand_chip *chip,
1296 const struct nand_ecc_caps *caps, int oobavail);
1297
1298int nand_maximize_ecc(struct nand_chip *chip,
1299 const struct nand_ecc_caps *caps, int oobavail);
1300
1301
1302int nand_reset(struct nand_chip *chip, int chipnr);
1303
1304
1305int nand_reset_op(struct nand_chip *chip);
1306int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1307 unsigned int len);
1308int nand_status_op(struct nand_chip *chip, u8 *status);
1309int nand_exit_status_op(struct nand_chip *chip);
1310int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1311int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1312 unsigned int offset_in_page, void *buf, unsigned int len);
1313int nand_change_read_column_op(struct nand_chip *chip,
1314 unsigned int offset_in_page, void *buf,
1315 unsigned int len, bool force_8bit);
1316int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1317 unsigned int offset_in_page, void *buf, unsigned int len);
1318int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1319 unsigned int offset_in_page, const void *buf,
1320 unsigned int len);
1321int nand_prog_page_end_op(struct nand_chip *chip);
1322int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1323 unsigned int offset_in_page, const void *buf,
1324 unsigned int len);
1325int nand_change_write_column_op(struct nand_chip *chip,
1326 unsigned int offset_in_page, const void *buf,
1327 unsigned int len, bool force_8bit);
1328int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1329 bool force_8bit);
1330int nand_write_data_op(struct nand_chip *chip, const void *buf,
1331 unsigned int len, bool force_8bit);
1332
1333#endif
1334