1
2
3
4
5
6
7#ifndef __LINUX_MTD_SPI_NOR_H
8#define __LINUX_MTD_SPI_NOR_H
9
10#include <mtd.h>
11#include <linux/bitops.h>
12#include <linux/mtd/cfi.h>
13#include <linux/mtd/mtd.h>
14
15
16
17
18
19
20
21#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
22#define SNOR_MFR_GIGADEVICE 0xc8
23#define SNOR_MFR_INTEL CFI_MFR_INTEL
24#define SNOR_MFR_ST CFI_MFR_ST
25#define SNOR_MFR_MICRON CFI_MFR_MICRON
26#define SNOR_MFR_ISSI CFI_MFR_PMC
27#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
28#define SNOR_MFR_SPANSION CFI_MFR_AMD
29#define SNOR_MFR_SST CFI_MFR_SST
30#define SNOR_MFR_WINBOND 0xef
31#define SNOR_MFR_CYPRESS 0x34
32
33
34
35
36
37
38
39
40
41
42#define SPINOR_OP_WREN 0x06
43#define SPINOR_OP_RDSR 0x05
44#define SPINOR_OP_WRSR 0x01
45#define SPINOR_OP_RDSR2 0x3f
46#define SPINOR_OP_WRSR2 0x3e
47#define SPINOR_OP_READ 0x03
48#define SPINOR_OP_READ_FAST 0x0b
49#define SPINOR_OP_READ_1_1_2 0x3b
50#define SPINOR_OP_READ_1_2_2 0xbb
51#define SPINOR_OP_READ_1_1_4 0x6b
52#define SPINOR_OP_READ_1_4_4 0xeb
53#define SPINOR_OP_READ_1_1_8 0x8b
54#define SPINOR_OP_READ_1_8_8 0xcb
55#define SPINOR_OP_PP 0x02
56#define SPINOR_OP_PP_1_1_4 0x32
57#define SPINOR_OP_PP_1_4_4 0x38
58#define SPINOR_OP_PP_1_1_8 0x82
59#define SPINOR_OP_PP_1_8_8 0xc2
60#define SPINOR_OP_BE_4K 0x20
61#define SPINOR_OP_BE_4K_PMC 0xd7
62#define SPINOR_OP_BE_32K 0x52
63#define SPINOR_OP_CHIP_ERASE 0xc7
64#define SPINOR_OP_SE 0xd8
65#define SPINOR_OP_RDID 0x9f
66#define SPINOR_OP_RDSFDP 0x5a
67#define SPINOR_OP_RDCR 0x35
68#define SPINOR_OP_RDFSR 0x70
69#define SPINOR_OP_CLFSR 0x50
70#define SPINOR_OP_RDEAR 0xc8
71#define SPINOR_OP_WREAR 0xc5
72#define SPINOR_OP_SRSTEN 0x66
73#define SPINOR_OP_SRST 0x99
74
75
76#define SPINOR_OP_READ_4B 0x13
77#define SPINOR_OP_READ_FAST_4B 0x0c
78#define SPINOR_OP_READ_1_1_2_4B 0x3c
79#define SPINOR_OP_READ_1_2_2_4B 0xbc
80#define SPINOR_OP_READ_1_1_4_4B 0x6c
81#define SPINOR_OP_READ_1_4_4_4B 0xec
82#define SPINOR_OP_READ_1_1_8_4B 0x7c
83#define SPINOR_OP_READ_1_8_8_4B 0xcc
84#define SPINOR_OP_PP_4B 0x12
85#define SPINOR_OP_PP_1_1_4_4B 0x34
86#define SPINOR_OP_PP_1_4_4_4B 0x3e
87#define SPINOR_OP_PP_1_1_8_4B 0x84
88#define SPINOR_OP_PP_1_8_8_4B 0x8e
89#define SPINOR_OP_BE_4K_4B 0x21
90#define SPINOR_OP_BE_32K_4B 0x5c
91#define SPINOR_OP_SE_4B 0xdc
92
93
94#define SPINOR_OP_READ_1_1_1_DTR 0x0d
95#define SPINOR_OP_READ_1_2_2_DTR 0xbd
96#define SPINOR_OP_READ_1_4_4_DTR 0xed
97
98#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
99#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
100#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
101
102
103#define SPINOR_OP_BP 0x02
104#define SPINOR_OP_WRDI 0x04
105#define SPINOR_OP_AAI_WP 0xad
106
107
108#define SPINOR_OP_READ_BPR 0x72
109#define SPINOR_OP_WRITE_BPR 0x42
110
111
112#define SPINOR_OP_XSE 0x50
113#define SPINOR_OP_XPP 0x82
114#define SPINOR_OP_XRDSR 0xd7
115
116#define XSR_PAGESIZE BIT(0)
117#define XSR_RDY BIT(7)
118
119
120#define SPINOR_OP_EN4B 0xb7
121#define SPINOR_OP_EX4B 0xe9
122
123
124#define SPINOR_OP_BRWR 0x17
125#define SPINOR_OP_BRRD 0x16
126#define SPINOR_OP_CLSR 0x30
127#define SPINOR_OP_EX4B_CYPRESS 0xB8
128#define SPINOR_OP_RDAR 0x65
129#define SPINOR_OP_WRAR 0x71
130#define SPINOR_REG_ADDR_STR1V 0x00800000
131#define SPINOR_REG_ADDR_CFR1V 0x00800002
132#define SPINOR_REG_ADDR_CFR3V 0x00800004
133#define CFR3V_UNHYSA BIT(3)
134#define CFR3V_PGMBUF BIT(4)
135
136
137#define SPINOR_OP_RD_EVCR 0x65
138#define SPINOR_OP_WD_EVCR 0x61
139#define SPINOR_OP_MT_DTR_RD 0xfd
140#define SPINOR_OP_MT_RD_ANY_REG 0x85
141#define SPINOR_OP_MT_WR_ANY_REG 0x81
142#define SPINOR_REG_MT_CFR0V 0x00
143#define SPINOR_REG_MT_CFR1V 0x01
144#define SPINOR_MT_OCT_DTR 0xe7
145
146
147#define SR_WIP BIT(0)
148#define SR_WEL BIT(1)
149
150#define SR_BP0 BIT(2)
151#define SR_BP1 BIT(3)
152#define SR_BP2 BIT(4)
153#define SR_TB BIT(5)
154#define SR_SRWD BIT(7)
155
156#define SR_E_ERR BIT(5)
157#define SR_P_ERR BIT(6)
158
159#define SR_QUAD_EN_MX BIT(6)
160
161
162#define EVCR_QUAD_EN_MICRON BIT(7)
163
164
165#define FSR_READY BIT(7)
166#define FSR_E_ERR BIT(5)
167#define FSR_P_ERR BIT(4)
168#define FSR_PT_ERR BIT(1)
169
170
171#define CR_QUAD_EN_SPAN BIT(1)
172
173
174#define SR2_QUAD_EN_BIT7 BIT(7)
175
176
177#define SPINOR_OP_RD_ANY_REG 0x65
178#define SPINOR_OP_WR_ANY_REG 0x71
179#define SPINOR_OP_S28_SE_4K 0x21
180#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
181#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
182#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
183#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4)
184#define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3)
185#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
186#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
187#define SPINOR_OP_CYPRESS_RD_FAST 0xee
188
189
190#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
191#define SNOR_PROTO_INST_SHIFT 16
192#define SNOR_PROTO_INST(_nbits) \
193 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
194 SNOR_PROTO_INST_MASK)
195
196#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
197#define SNOR_PROTO_ADDR_SHIFT 8
198#define SNOR_PROTO_ADDR(_nbits) \
199 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
200 SNOR_PROTO_ADDR_MASK)
201
202#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
203#define SNOR_PROTO_DATA_SHIFT 0
204#define SNOR_PROTO_DATA(_nbits) \
205 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
206 SNOR_PROTO_DATA_MASK)
207
208#define SNOR_PROTO_IS_DTR BIT(24)
209
210#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
211 (SNOR_PROTO_INST(_inst_nbits) | \
212 SNOR_PROTO_ADDR(_addr_nbits) | \
213 SNOR_PROTO_DATA(_data_nbits))
214#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
215 (SNOR_PROTO_IS_DTR | \
216 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
217
218enum spi_nor_protocol {
219 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
220 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
221 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
222 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
223 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
224 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
225 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
226 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
227 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
228 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
229
230 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
231 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
232 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
233 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
234 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
235};
236
237static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
238{
239 return !!(proto & SNOR_PROTO_IS_DTR);
240}
241
242static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
243{
244 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
245 SNOR_PROTO_INST_SHIFT;
246}
247
248static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
249{
250 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
251 SNOR_PROTO_ADDR_SHIFT;
252}
253
254static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
255{
256 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
257 SNOR_PROTO_DATA_SHIFT;
258}
259
260static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
261{
262 return spi_nor_get_protocol_data_nbits(proto);
263}
264
265#define SPI_NOR_MAX_CMD_SIZE 8
266enum spi_nor_ops {
267 SPI_NOR_OPS_READ = 0,
268 SPI_NOR_OPS_WRITE,
269 SPI_NOR_OPS_ERASE,
270 SPI_NOR_OPS_LOCK,
271 SPI_NOR_OPS_UNLOCK,
272};
273
274enum spi_nor_option_flags {
275 SNOR_F_USE_FSR = BIT(0),
276 SNOR_F_HAS_SR_TB = BIT(1),
277 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
278 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
279 SNOR_F_READY_XSR_RDY = BIT(4),
280 SNOR_F_USE_CLSR = BIT(5),
281 SNOR_F_BROKEN_RESET = BIT(6),
282 SNOR_F_SOFT_RESET = BIT(7),
283};
284
285struct spi_nor;
286
287
288
289
290
291
292struct spi_nor_hwcaps {
293 u32 mask;
294};
295
296
297
298
299
300
301
302
303#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
304#define SNOR_HWCAPS_READ BIT(0)
305#define SNOR_HWCAPS_READ_FAST BIT(1)
306#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
307
308#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
309#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
310#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
311#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
312#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
313
314#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
315#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
316#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
317#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
318#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
319
320#define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
321#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
322#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
323#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
324#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
325#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
326
327
328
329
330
331
332
333
334
335
336#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
337#define SNOR_HWCAPS_PP BIT(16)
338
339#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
340#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
341#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
342#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
343
344#define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
345#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
346#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
347#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
348#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
349
350#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
351 SNOR_HWCAPS_READ_4_4_4 | \
352 SNOR_HWCAPS_READ_8_8_8 | \
353 SNOR_HWCAPS_PP_4_4_4 | \
354 SNOR_HWCAPS_PP_8_8_8)
355
356#define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
357 SNOR_HWCAPS_PP_8_8_8_DTR)
358
359#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
360 SNOR_HWCAPS_READ_1_2_2_DTR | \
361 SNOR_HWCAPS_READ_1_4_4_DTR | \
362 SNOR_HWCAPS_READ_1_8_8_DTR)
363
364#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
365 SNOR_HWCAPS_PP_MASK)
366
367struct spi_nor_read_command {
368 u8 num_mode_clocks;
369 u8 num_wait_states;
370 u8 opcode;
371 enum spi_nor_protocol proto;
372};
373
374struct spi_nor_pp_command {
375 u8 opcode;
376 enum spi_nor_protocol proto;
377};
378
379enum spi_nor_read_command_index {
380 SNOR_CMD_READ,
381 SNOR_CMD_READ_FAST,
382 SNOR_CMD_READ_1_1_1_DTR,
383
384
385 SNOR_CMD_READ_1_1_2,
386 SNOR_CMD_READ_1_2_2,
387 SNOR_CMD_READ_2_2_2,
388 SNOR_CMD_READ_1_2_2_DTR,
389
390
391 SNOR_CMD_READ_1_1_4,
392 SNOR_CMD_READ_1_4_4,
393 SNOR_CMD_READ_4_4_4,
394 SNOR_CMD_READ_1_4_4_DTR,
395
396
397 SNOR_CMD_READ_1_1_8,
398 SNOR_CMD_READ_1_8_8,
399 SNOR_CMD_READ_8_8_8,
400 SNOR_CMD_READ_1_8_8_DTR,
401 SNOR_CMD_READ_8_8_8_DTR,
402
403 SNOR_CMD_READ_MAX
404};
405
406enum spi_nor_pp_command_index {
407 SNOR_CMD_PP,
408
409
410 SNOR_CMD_PP_1_1_4,
411 SNOR_CMD_PP_1_4_4,
412 SNOR_CMD_PP_4_4_4,
413
414
415 SNOR_CMD_PP_1_1_8,
416 SNOR_CMD_PP_1_8_8,
417 SNOR_CMD_PP_8_8_8,
418 SNOR_CMD_PP_8_8_8_DTR,
419
420 SNOR_CMD_PP_MAX
421};
422
423struct spi_nor_flash_parameter {
424 u64 size;
425 u32 page_size;
426 u8 rdsr_dummy;
427 u8 rdsr_addr_nbytes;
428
429 struct spi_nor_hwcaps hwcaps;
430 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
431 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
432
433 int (*quad_enable)(struct spi_nor *nor);
434};
435
436
437
438
439
440
441
442
443
444
445enum spi_nor_cmd_ext {
446 SPI_NOR_EXT_NONE = 0,
447 SPI_NOR_EXT_REPEAT,
448 SPI_NOR_EXT_INVERT,
449 SPI_NOR_EXT_HEX,
450};
451
452
453
454
455
456struct flash_info;
457
458
459
460
461
462
463
464
465#ifndef DT_PLAT_C
466#define spi_flash spi_nor
467#endif
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516struct spi_nor {
517 struct mtd_info mtd;
518 struct udevice *dev;
519 struct spi_slave *spi;
520 const struct flash_info *info;
521 u8 *manufacturer_sfdp;
522 u32 page_size;
523 u8 addr_width;
524 u8 erase_opcode;
525 u8 read_opcode;
526 u8 read_dummy;
527 u8 program_opcode;
528 u8 rdsr_dummy;
529 u8 rdsr_addr_nbytes;
530#ifdef CONFIG_SPI_FLASH_BAR
531 u8 bank_read_cmd;
532 u8 bank_write_cmd;
533 u8 bank_curr;
534#endif
535 enum spi_nor_protocol read_proto;
536 enum spi_nor_protocol write_proto;
537 enum spi_nor_protocol reg_proto;
538 bool sst_write_second;
539 u32 flags;
540 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
541 enum spi_nor_cmd_ext cmd_ext_type;
542 struct spi_nor_fixups *fixups;
543
544 int (*setup)(struct spi_nor *nor, const struct flash_info *info,
545 const struct spi_nor_flash_parameter *params);
546 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
547 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
548 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
549 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
550
551 ssize_t (*read)(struct spi_nor *nor, loff_t from,
552 size_t len, u_char *read_buf);
553 ssize_t (*write)(struct spi_nor *nor, loff_t to,
554 size_t len, const u_char *write_buf);
555 int (*erase)(struct spi_nor *nor, loff_t offs);
556
557 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
558 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
559 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
560 int (*quad_enable)(struct spi_nor *nor);
561 int (*octal_dtr_enable)(struct spi_nor *nor);
562 int (*ready)(struct spi_nor *nor);
563
564 void *priv;
565 char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
566
567 const char *name;
568 u32 size;
569 u32 sector_size;
570 u32 erase_size;
571};
572
573#ifndef __UBOOT__
574static inline void spi_nor_set_flash_node(struct spi_nor *nor,
575 const struct device_node *np)
576{
577 mtd_set_of_node(&nor->mtd, np);
578}
579
580static inline const struct
581device_node *spi_nor_get_flash_node(struct spi_nor *nor)
582{
583 return mtd_get_of_node(&nor->mtd);
584}
585#endif
586
587
588
589
590
591
592
593
594
595
596
597int spi_nor_scan(struct spi_nor *nor);
598
599#if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
600static inline int spi_nor_remove(struct spi_nor *nor)
601{
602 return 0;
603}
604#else
605
606
607
608
609
610
611int spi_nor_remove(struct spi_nor *nor);
612#endif
613
614#endif
615