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9#ifndef _PHY_H
10#define _PHY_H
11
12#include <log.h>
13#include <phy_interface.h>
14#include <dm/ofnode.h>
15#include <dm/read.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/mii.h>
19#include <linux/ethtool.h>
20#include <linux/mdio.h>
21
22struct udevice;
23
24#define PHY_FIXED_ID 0xa5a55a5a
25#define PHY_NCSI_ID 0xbeefcafe
26
27
28
29
30
31#define PHY_GMII2RGMII_ID 0x5a5a5a5a
32
33#define PHY_MAX_ADDR 32
34
35#define PHY_FLAG_BROKEN_RESET (1 << 0)
36
37#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
38 SUPPORTED_TP | \
39 SUPPORTED_MII)
40
41#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
42 SUPPORTED_10baseT_Full)
43
44#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
45 SUPPORTED_100baseT_Full)
46
47#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
48 SUPPORTED_1000baseT_Full)
49
50#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
51 PHY_100BT_FEATURES | \
52 PHY_DEFAULT_FEATURES)
53
54#define PHY_100BT1_FEATURES (SUPPORTED_TP | \
55 SUPPORTED_MII | \
56 SUPPORTED_100baseT_Full)
57
58#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
59 PHY_1000BT_FEATURES)
60
61#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
62 SUPPORTED_10000baseT_Full)
63
64#ifndef PHY_ANEG_TIMEOUT
65#define PHY_ANEG_TIMEOUT 4000
66#endif
67
68
69struct phy_device;
70
71#define MDIO_NAME_LEN 32
72
73struct mii_dev {
74 struct list_head link;
75 char name[MDIO_NAME_LEN];
76 void *priv;
77 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
78 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
79 u16 val);
80 int (*reset)(struct mii_dev *bus);
81 struct phy_device *phymap[PHY_MAX_ADDR];
82 u32 phy_mask;
83};
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94
95struct phy_driver {
96 char *name;
97 unsigned int uid;
98 unsigned int mask;
99 unsigned int mmds;
100
101 u32 features;
102
103
104
105 int (*probe)(struct phy_device *phydev);
106
107
108
109 int (*config)(struct phy_device *phydev);
110
111
112 int (*startup)(struct phy_device *phydev);
113
114
115 int (*shutdown)(struct phy_device *phydev);
116
117 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
118 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
119 u16 val);
120
121
122 int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
123
124
125 int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
126 u16 val);
127
128 struct list_head list;
129
130
131 ulong data;
132};
133
134struct phy_device {
135
136
137 struct mii_dev *bus;
138 struct phy_driver *drv;
139 void *priv;
140
141#ifdef CONFIG_DM_ETH
142 struct udevice *dev;
143 ofnode node;
144#else
145 struct eth_device *dev;
146#endif
147
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150
151 int speed;
152 int duplex;
153
154
155 int link;
156 int port;
157 phy_interface_t interface;
158
159 u32 advertising;
160 u32 supported;
161 u32 mmds;
162
163 int autoneg;
164 int addr;
165 int pause;
166 int asym_pause;
167 u32 phy_id;
168 bool is_c45;
169 u32 flags;
170};
171
172struct fixed_link {
173 int phy_id;
174 int duplex;
175 int link_speed;
176 int pause;
177 int asym_pause;
178};
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186
187static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
188{
189 struct mii_dev *bus = phydev->bus;
190
191 if (!bus || !bus->read) {
192 debug("%s: No bus configured\n", __func__);
193 return -1;
194 }
195
196 return bus->read(bus, phydev->addr, devad, regnum);
197}
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207static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
208 u16 val)
209{
210 struct mii_dev *bus = phydev->bus;
211
212 if (!bus || !bus->write) {
213 debug("%s: No bus configured\n", __func__);
214 return -1;
215 }
216
217 return bus->write(bus, phydev->addr, devad, regnum, val);
218}
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226
227static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
228 int regnum)
229{
230
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
232
233
234 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
235
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237 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
238 (devad | MII_MMD_CTRL_NOINCR));
239}
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249static inline int phy_read_mmd(struct phy_device *phydev, int devad,
250 int regnum)
251{
252 struct phy_driver *drv = phydev->drv;
253
254 if (regnum > (u16)~0 || devad > 32)
255 return -EINVAL;
256
257
258 if (drv->read_mmd)
259 return drv->read_mmd(phydev, devad, regnum);
260
261
262 if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
263 devad == MDIO_DEVAD_NONE || !devad)
264 return phy_read(phydev, devad, regnum);
265
266
267 phy_mmd_start_indirect(phydev, devad, regnum);
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270 return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
271}
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282static inline int phy_write_mmd(struct phy_device *phydev, int devad,
283 int regnum, u16 val)
284{
285 struct phy_driver *drv = phydev->drv;
286
287 if (regnum > (u16)~0 || devad > 32)
288 return -EINVAL;
289
290
291 if (drv->write_mmd)
292 return drv->write_mmd(phydev, devad, regnum, val);
293
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295 if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
296 devad == MDIO_DEVAD_NONE || !devad)
297 return phy_write(phydev, devad, regnum, val);
298
299
300 phy_mmd_start_indirect(phydev, devad, regnum);
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303 return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
304}
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315static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
316 u32 regnum, u16 val)
317{
318 int value, ret;
319
320 value = phy_read_mmd(phydev, devad, regnum);
321 if (value < 0)
322 return value;
323
324 value |= val;
325
326 ret = phy_write_mmd(phydev, devad, regnum, value);
327 if (ret < 0)
328 return ret;
329
330 return 0;
331}
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341
342static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
343 u32 regnum, u16 val)
344{
345 int value, ret;
346
347 value = phy_read_mmd(phydev, devad, regnum);
348 if (value < 0)
349 return value;
350
351 value &= ~val;
352
353 ret = phy_write_mmd(phydev, devad, regnum, value);
354 if (ret < 0)
355 return ret;
356
357 return 0;
358}
359
360#ifdef CONFIG_PHYLIB_10G
361extern struct phy_driver gen10g_driver;
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367static inline int is_10g_interface(phy_interface_t interface)
368{
369 return interface == PHY_INTERFACE_MODE_XGMII ||
370 interface == PHY_INTERFACE_MODE_USXGMII ||
371 interface == PHY_INTERFACE_MODE_10GBASER;
372}
373
374#endif
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382int phy_init(void);
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391int phy_reset(struct phy_device *phydev);
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406struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
407 phy_interface_t interface);
408
409#ifdef CONFIG_PHY_FIXED
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419struct phy_device *fixed_phy_create(ofnode node);
420
421#else
422
423static inline struct phy_device *fixed_phy_create(ofnode node)
424{
425 return NULL;
426}
427
428#endif
429
430#ifdef CONFIG_DM_ETH
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437void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
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454struct phy_device *phy_connect(struct mii_dev *bus, int addr,
455 struct udevice *dev,
456 phy_interface_t interface);
457
458static inline ofnode phy_get_ofnode(struct phy_device *phydev)
459{
460 if (ofnode_valid(phydev->node))
461 return phydev->node;
462 else
463 return dev_ofnode(phydev->dev);
464}
465#else
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472void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
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489struct phy_device *phy_connect(struct mii_dev *bus, int addr,
490 struct eth_device *dev,
491 phy_interface_t interface);
492
493static inline ofnode phy_get_ofnode(struct phy_device *phydev)
494{
495 return ofnode_null();
496}
497#endif
498int phy_startup(struct phy_device *phydev);
499int phy_config(struct phy_device *phydev);
500int phy_shutdown(struct phy_device *phydev);
501int phy_register(struct phy_driver *drv);
502int phy_set_supported(struct phy_device *phydev, u32 max_speed);
503int genphy_config_aneg(struct phy_device *phydev);
504int genphy_restart_aneg(struct phy_device *phydev);
505int genphy_update_link(struct phy_device *phydev);
506int genphy_parse_link(struct phy_device *phydev);
507int genphy_config(struct phy_device *phydev);
508int genphy_startup(struct phy_device *phydev);
509int genphy_shutdown(struct phy_device *phydev);
510int gen10g_config(struct phy_device *phydev);
511int gen10g_startup(struct phy_device *phydev);
512int gen10g_shutdown(struct phy_device *phydev);
513int gen10g_discover_mmds(struct phy_device *phydev);
514
515int phy_b53_init(void);
516int phy_mv88e61xx_init(void);
517int phy_aquantia_init(void);
518int phy_atheros_init(void);
519int phy_broadcom_init(void);
520int phy_cortina_init(void);
521int phy_cortina_access_init(void);
522int phy_davicom_init(void);
523int phy_et1011c_init(void);
524int phy_lxt_init(void);
525int phy_marvell_init(void);
526int phy_micrel_ksz8xxx_init(void);
527int phy_micrel_ksz90x1_init(void);
528int phy_meson_gxl_init(void);
529int phy_natsemi_init(void);
530int phy_nxp_tja11xx_init(void);
531int phy_realtek_init(void);
532int phy_smsc_init(void);
533int phy_teranetics_init(void);
534int phy_ti_init(void);
535int phy_vitesse_init(void);
536int phy_xilinx_init(void);
537int phy_mscc_init(void);
538int phy_fixed_init(void);
539int phy_ncsi_init(void);
540int phy_xilinx_gmii2rgmii_init(void);
541
542int board_phy_config(struct phy_device *phydev);
543int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
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550
551int phy_get_interface_by_name(const char *str);
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559static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
560{
561 return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
562 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
563}
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571static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
572{
573 return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
574 phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
575}
576
577
578#define PHY_UID_CS4340 0x13e51002
579#define PHY_UID_CS4223 0x03e57003
580#define PHY_UID_TN2020 0x00a19410
581#define PHY_UID_IN112525_S03 0x02107440
582
583#endif
584