1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * USB HOST XHCI Controller 4 * 5 * Based on xHCI host controller driver in linux-kernel 6 * by Sarah Sharp. 7 * 8 * Copyright (C) 2008 Intel Corp. 9 * Author: Sarah Sharp 10 * 11 * Copyright (C) 2013 Samsung Electronics Co.Ltd 12 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 13 * Vikas Sajjan <vikas.sajjan@samsung.com> 14 */ 15 16#ifndef HOST_XHCI_H_ 17#define HOST_XHCI_H_ 18 19#include <phys2bus.h> 20#include <asm/types.h> 21#include <asm/cache.h> 22#include <asm/io.h> 23#include <linux/list.h> 24#include <linux/compat.h> 25 26#define MAX_EP_CTX_NUM 31 27#define XHCI_ALIGNMENT 64 28/* Generic timeout for XHCI events */ 29#define XHCI_TIMEOUT 5000 30/* Max number of USB devices for any host controller - limit in section 6.1 */ 31#define MAX_HC_SLOTS 256 32/* Section 5.3.3 - MaxPorts */ 33#define MAX_HC_PORTS 255 34 35/* Up to 16 ms to halt an HC */ 36#define XHCI_MAX_HALT_USEC (16*1000) 37 38#define XHCI_MAX_RESET_USEC (250*1000) 39 40/* 41 * These bits are Read Only (RO) and should be saved and written to the 42 * registers: 0, 3, 10:13, 30 43 * connect status, over-current status, port speed, and device removable. 44 * connect status and port speed are also sticky - meaning they're in 45 * the AUX well and they aren't changed by a hot, warm, or cold reset. 46 */ 47#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) 48/* 49 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 50 * bits 5:8, 9, 14:15, 25:27 51 * link state, port power, port indicator state, "wake on" enable state 52 */ 53#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) 54/* 55 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 56 * bit 4 (port reset) 57 */ 58#define XHCI_PORT_RW1S ((1 << 4)) 59/* 60 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 61 * bits 1, 17, 18, 19, 20, 21, 22, 23 62 * port enable/disable, and 63 * change bits: connect, PED, 64 * warm port reset changed (reserved zero for USB 2.0 ports), 65 * over-current, reset, link state, and L1 change 66 */ 67#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) 68/* 69 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 70 * latched in 71 */ 72#define XHCI_PORT_RW ((1 << 16)) 73/* 74 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 75 * bits 2, 24, 28:31 76 */ 77#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) 78 79/* 80 * XHCI Register Space. 81 */ 82struct xhci_hccr { 83 uint32_t cr_capbase; 84 uint32_t cr_hcsparams1; 85 uint32_t cr_hcsparams2; 86 uint32_t cr_hcsparams3; 87 uint32_t cr_hccparams; 88 uint32_t cr_dboff; 89 uint32_t cr_rtsoff; 90 91/* hc_capbase bitmasks */ 92/* bits 7:0 - how long is the Capabilities register */ 93#define HC_LENGTH(p) XHCI_HC_LENGTH(p) 94/* bits 31:16 */ 95#define HC_VERSION(p) (((p) >> 16) & 0xffff) 96 97/* HCSPARAMS1 - hcs_params1 - bitmasks */ 98/* bits 0:7, Max Device Slots */ 99#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 100#define HCS_SLOTS_MASK 0xff 101/* bits 8:18, Max Interrupters */ 102#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 103/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 104#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 105 106/* HCSPARAMS2 - hcs_params2 - bitmasks */ 107/* bits 0:3, frames or uframes that SW needs to queue transactions 108 * ahead of the HW to meet periodic deadlines */ 109#define HCS_IST(p) (((p) >> 0) & 0xf) 110/* bits 4:7, max number of Event Ring segments */ 111#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 112/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 113/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 114/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 115#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 116 117/* HCSPARAMS3 - hcs_params3 - bitmasks */ 118/* bits 0:7, Max U1 to U0 latency for the roothub ports */ 119#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 120/* bits 16:31, Max U2 to U0 latency for the roothub ports */ 121#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 122 123/* HCCPARAMS - hcc_params - bitmasks */ 124/* true: HC can use 64-bit address pointers */ 125#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 126/* true: HC can do bandwidth negotiation */ 127#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 128/* true: HC uses 64-byte Device Context structures 129 * FIXME 64-byte context structures aren't supported yet. 130 */ 131#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 132/* true: HC has port power switches */ 133#define HCC_PPC(p) ((p) & (1 << 3)) 134/* true: HC has port indicators */ 135#define HCS_INDICATOR(p) ((p) & (1 << 4)) 136/* true: HC has Light HC Reset Capability */ 137#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 138/* true: HC supports latency tolerance messaging */ 139#define HCC_LTC(p) ((p) & (1 << 6)) 140/* true: no secondary Stream ID Support */ 141#define HCC_NSS(p) ((p) & (1 << 7)) 142/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 143#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 144/* Extended Capabilities pointer from PCI base - section 5.3.6 */ 145#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 146 147/* db_off bitmask - bits 0:1 reserved */ 148#define DBOFF_MASK (~0x3) 149 150/* run_regs_off bitmask - bits 0:4 reserved */ 151#define RTSOFF_MASK (~0x1f) 152 153}; 154 155struct xhci_hcor_port_regs { 156 volatile uint32_t or_portsc; 157 volatile uint32_t or_portpmsc; 158 volatile uint32_t or_portli; 159 volatile uint32_t reserved_3; 160}; 161 162struct xhci_hcor { 163 volatile uint32_t or_usbcmd; 164 volatile uint32_t or_usbsts; 165 volatile uint32_t or_pagesize; 166 volatile uint32_t reserved_0[2]; 167 volatile uint32_t or_dnctrl; 168 volatile uint64_t or_crcr; 169 volatile uint32_t reserved_1[4]; 170 volatile uint64_t or_dcbaap; 171 volatile uint32_t or_config; 172 volatile uint32_t reserved_2[241]; 173 struct xhci_hcor_port_regs portregs[MAX_HC_PORTS]; 174}; 175 176/* USBCMD - USB command - command bitmasks */ 177/* start/stop HC execution - do not write unless HC is halted*/ 178#define CMD_RUN XHCI_CMD_RUN 179/* Reset HC - resets internal HC state machine and all registers (except 180 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 181 * The xHCI driver must reinitialize the xHC after setting this bit. 182 */ 183#define CMD_RESET (1 << 1) 184/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 185#define CMD_EIE XHCI_CMD_EIE 186/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 187#define CMD_HSEIE XHCI_CMD_HSEIE 188/* bits 4:6 are reserved (and should be preserved on writes). */ 189/* light reset (port status stays unchanged) - reset completed when this is 0 */ 190#define CMD_LRESET (1 << 7) 191/* host controller save/restore state. */ 192#define CMD_CSS (1 << 8) 193#define CMD_CRS (1 << 9) 194/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 195#define CMD_EWE XHCI_CMD_EWE 196/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 197 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 198 * '0' means the xHC can power it off if all ports are in the disconnect, 199 * disabled, or powered-off state. 200 */ 201#define CMD_PM_INDEX (1 << 11) 202/* bits 12:31 are reserved (and should be preserved on writes). */ 203 204/* USBSTS - USB status - status bitmasks */ 205/* HC not running - set to 1 when run/stop bit is cleared. */ 206#define STS_HALT XHCI_STS_HALT 207/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 208#define STS_FATAL (1 << 2) 209/* event interrupt - clear this prior to clearing any IP flags in IR set*/ 210#define STS_EINT (1 << 3) 211/* port change detect */ 212#define STS_PORT (1 << 4) 213/* bits 5:7 reserved and zeroed */ 214/* save state status - '1' means xHC is saving state */ 215#define STS_SAVE (1 << 8) 216/* restore state status - '1' means xHC is restoring state */ 217#define STS_RESTORE (1 << 9) 218/* true: save or restore error */ 219#define STS_SRE (1 << 10) 220/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 221#define STS_CNR XHCI_STS_CNR 222/* true: internal Host Controller Error - SW needs to reset and reinitialize */ 223#define STS_HCE (1 << 12) 224/* bits 13:31 reserved and should be preserved */ 225 226/* 227 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 228 * Generate a device notification event when the HC sees a transaction with a 229 * notification type that matches a bit set in this bit field. 230 */ 231#define DEV_NOTE_MASK (0xffff) 232#define ENABLE_DEV_NOTE(x) (1 << (x)) 233/* Most of the device notification types should only be used for debug. 234 * SW does need to pay attention to function wake notifications. 235 */ 236#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 237 238/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 239/* bit 0 is the command ring cycle state */ 240/* stop ring operation after completion of the currently executing command */ 241#define CMD_RING_PAUSE (1 << 1) 242/* stop ring immediately - abort the currently executing command */ 243#define CMD_RING_ABORT (1 << 2) 244/* true: command ring is running */ 245#define CMD_RING_RUNNING (1 << 3) 246/* bits 4:5 reserved and should be preserved */ 247/* Command Ring pointer - bit mask for the lower 32 bits. */ 248#define CMD_RING_RSVD_BITS (0x3f) 249 250/* CONFIG - Configure Register - config_reg bitmasks */ 251/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 252#define MAX_DEVS(p) ((p) & 0xff) 253/* bits 8:31 - reserved and should be preserved */ 254 255/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 256/* true: device connected */ 257#define PORT_CONNECT (1 << 0) 258/* true: port enabled */ 259#define PORT_PE (1 << 1) 260/* bit 2 reserved and zeroed */ 261/* true: port has an over-current condition */ 262#define PORT_OC (1 << 3) 263/* true: port reset signaling asserted */ 264#define PORT_RESET (1 << 4) 265/* Port Link State - bits 5:8 266 * A read gives the current link PM state of the port, 267 * a write with Link State Write Strobe set sets the link state. 268 */ 269#define PORT_PLS_MASK (0xf << 5) 270#define XDEV_U0 (0x0 << 5) 271#define XDEV_U2 (0x2 << 5) 272#define XDEV_U3 (0x3 << 5) 273#define XDEV_RESUME (0xf << 5) 274/* true: port has power (see HCC_PPC) */ 275#define PORT_POWER (1 << 9) 276/* bits 10:13 indicate device speed: 277 * 0 - undefined speed - port hasn't be initialized by a reset yet 278 * 1 - full speed 279 * 2 - low speed 280 * 3 - high speed 281 * 4 - super speed 282 * 5-15 reserved 283 */ 284#define DEV_SPEED_MASK (0xf << 10) 285#define XDEV_FS (0x1 << 10) 286#define XDEV_LS (0x2 << 10) 287#define XDEV_HS (0x3 << 10) 288#define XDEV_SS (0x4 << 10) 289#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 290#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 291#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 292#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 293#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 294/* Bits 20:23 in the Slot Context are the speed for the device */ 295#define SLOT_SPEED_FS (XDEV_FS << 10) 296#define SLOT_SPEED_LS (XDEV_LS << 10) 297#define SLOT_SPEED_HS (XDEV_HS << 10) 298#define SLOT_SPEED_SS (XDEV_SS << 10) 299/* Port Indicator Control */ 300#define PORT_LED_OFF (0 << 14) 301#define PORT_LED_AMBER (1 << 14) 302#define PORT_LED_GREEN (2 << 14) 303#define PORT_LED_MASK (3 << 14) 304/* Port Link State Write Strobe - set this when changing link state */ 305#define PORT_LINK_STROBE (1 << 16) 306/* true: connect status change */ 307#define PORT_CSC (1 << 17) 308/* true: port enable change */ 309#define PORT_PEC (1 << 18) 310/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 311 * into an enabled state, and the device into the default state. A "warm" reset 312 * also resets the link, forcing the device through the link training sequence. 313 * SW can also look at the Port Reset register to see when warm reset is done. 314 */ 315#define PORT_WRC (1 << 19) 316/* true: over-current change */ 317#define PORT_OCC (1 << 20) 318/* true: reset change - 1 to 0 transition of PORT_RESET */ 319#define PORT_RC (1 << 21) 320/* port link status change - set on some port link state transitions: 321 * Transition Reason 322 * -------------------------------------------------------------------------- 323 * - U3 to Resume Wakeup signaling from a device 324 * - Resume to Recovery to U0 USB 3.0 device resume 325 * - Resume to U0 USB 2.0 device resume 326 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 327 * - U3 to U0 Software resume of USB 2.0 device complete 328 * - U2 to U0 L1 resume of USB 2.1 device complete 329 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 330 * - U0 to disabled L1 entry error with USB 2.1 device 331 * - Any state to inactive Error on USB 3.0 port 332 */ 333#define PORT_PLC (1 << 22) 334/* port configure error change - port failed to configure its link partner */ 335#define PORT_CEC (1 << 23) 336/* bit 24 reserved */ 337/* wake on connect (enable) */ 338#define PORT_WKCONN_E (1 << 25) 339/* wake on disconnect (enable) */ 340#define PORT_WKDISC_E (1 << 26) 341/* wake on over-current (enable) */ 342#define PORT_WKOC_E (1 << 27) 343/* bits 28:29 reserved */ 344/* true: device is removable - for USB 3.0 roothub emulation */ 345#define PORT_DEV_REMOVE (1 << 30) 346/* Initiate a warm port reset - complete when PORT_WRC is '1' */ 347#define PORT_WR (1 << 31) 348 349/* We mark duplicate entries with -1 */ 350#define DUPLICATE_ENTRY ((u8)(-1)) 351 352/* Port Power Management Status and Control - port_power_base bitmasks */ 353/* Inactivity timer value for transitions into U1, in microseconds. 354 * Timeout can be up to 127us. 0xFF means an infinite timeout. 355 */ 356#define PORT_U1_TIMEOUT(p) ((p) & 0xff) 357/* Inactivity timer value for transitions into U2 */ 358#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 359/* Bits 24:31 for port testing */ 360 361/* USB2 Protocol PORTSPMSC */ 362#define PORT_L1S_MASK 7 363#define PORT_L1S_SUCCESS 1 364#define PORT_RWE (1 << 3) 365#define PORT_HIRD(p) (((p) & 0xf) << 4) 366#define PORT_HIRD_MASK (0xf << 4) 367#define PORT_L1DS(p) (((p) & 0xff) << 8) 368#define PORT_HLE (1 << 16) 369 370/** 371* struct xhci_intr_reg - Interrupt Register Set 372* @irq_pending: IMAN - Interrupt Management Register. Used to enable 373* interrupts and check for pending interrupts. 374* @irq_control: IMOD - Interrupt Moderation Register. 375* Used to throttle interrupts. 376* @erst_size: Number of segments in the 377 Event Ring Segment Table (ERST). 378* @erst_base: ERST base address. 379* @erst_dequeue: Event ring dequeue pointer. 380* 381* Each interrupter (defined by a MSI-X vector) has an event ring and an Event 382* Ring Segment Table (ERST) associated with it. 383* The event ring is comprised of multiple segments of the same size. 384* The HC places events on the ring and "updates the Cycle bit in the TRBs to 385* indicate to software the current position of the Enqueue Pointer." 386* The HCD (Linux) processes those events and updates the dequeue pointer. 387*/ 388struct xhci_intr_reg { 389 volatile __le32 irq_pending; 390 volatile __le32 irq_control; 391 volatile __le32 erst_size; 392 volatile __le32 rsvd; 393 volatile __le64 erst_base; 394 volatile __le64 erst_dequeue; 395}; 396 397/* irq_pending bitmasks */ 398#define ER_IRQ_PENDING(p) ((p) & 0x1) 399/* bits 2:31 need to be preserved */ 400/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 401#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 402#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 403#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 404 405/* irq_control bitmasks */ 406/* Minimum interval between interrupts (in 250ns intervals). The interval 407 * between interrupts will be longer if there are no events on the event ring. 408 * Default is 4000 (1 ms). 409 */ 410#define ER_IRQ_INTERVAL_MASK (0xffff) 411/* Counter used to count down the time to the next interrupt - HW use only */ 412#define ER_IRQ_COUNTER_MASK (0xffff << 16) 413 414/* erst_size bitmasks */ 415/* Preserve bits 16:31 of erst_size */ 416#define ERST_SIZE_MASK (0xffff << 16) 417 418/* erst_dequeue bitmasks */ 419/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 420 * where the current dequeue pointer lies. This is an optional HW hint. 421 */ 422#define ERST_DESI_MASK (0x7) 423/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 424 * a work queue (or delayed service routine)? 425 */ 426#define ERST_EHB (1 << 3) 427#define ERST_PTR_MASK (0xf) 428 429/** 430 * struct xhci_run_regs 431 * @microframe_index: MFINDEX - current microframe number 432 * 433 * Section 5.5 Host Controller Runtime Registers: 434 * "Software should read and write these registers using only Dword (32 bit) 435 * or larger accesses" 436 */ 437struct xhci_run_regs { 438 __le32 microframe_index; 439 __le32 rsvd[7]; 440 struct xhci_intr_reg ir_set[128]; 441}; 442 443/** 444 * struct doorbell_array 445 * 446 * Bits 0 - 7: Endpoint target 447 * Bits 8 - 15: RsvdZ 448 * Bits 16 - 31: Stream ID 449 * 450 * Section 5.6 451 */ 452struct xhci_doorbell_array { 453 volatile __le32 doorbell[256]; 454}; 455 456#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 457#define DB_VALUE_HOST 0x00000000 458 459/** 460 * struct xhci_protocol_caps 461 * @revision: major revision, minor revision, capability ID, 462 * and next capability pointer. 463 * @name_string: Four ASCII characters to say which spec this xHC 464 * follows, typically "USB ". 465 * @port_info: Port offset, count, and protocol-defined information. 466 */ 467struct xhci_protocol_caps { 468 u32 revision; 469 u32 name_string; 470 u32 port_info; 471}; 472 473#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 474#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 475#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 476 477/** 478 * struct xhci_container_ctx 479 * @type: Type of context. Used to calculated offsets to contained contexts. 480 * @size: Size of the context data 481 * @bytes: The raw context data given to HW 482 * 483 * Represents either a Device or Input context. Holds a pointer to the raw 484 * memory used for the context (bytes). 485 */ 486struct xhci_container_ctx { 487 unsigned type; 488#define XHCI_CTX_TYPE_DEVICE 0x1 489#define XHCI_CTX_TYPE_INPUT 0x2 490 491 int size; 492 u8 *bytes; 493}; 494 495/** 496 * struct xhci_slot_ctx 497 * @dev_info: Route string, device speed, hub info, and last valid endpoint 498 * @dev_info2: Max exit latency for device number, root hub port number 499 * @tt_info: tt_info is used to construct split transaction tokens 500 * @dev_state: slot state and device address 501 * 502 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 503 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 504 * reserved at the end of the slot context for HC internal use. 505 */ 506struct xhci_slot_ctx { 507 __le32 dev_info; 508 __le32 dev_info2; 509 __le32 tt_info; 510 __le32 dev_state; 511 /* offset 0x10 to 0x1f reserved for HC internal use */ 512 __le32 reserved[4]; 513}; 514 515/* dev_info bitmasks */ 516/* Route String - 0:19 */ 517#define ROUTE_STRING_MASK (0xfffff) 518/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 519#define DEV_SPEED (0xf << 20) 520/* bit 24 reserved */ 521/* Is this LS/FS device connected through a HS hub? - bit 25 */ 522#define DEV_MTT (0x1 << 25) 523/* Set if the device is a hub - bit 26 */ 524#define DEV_HUB (0x1 << 26) 525/* Index of the last valid endpoint context in this device context - 27:31 */ 526#define LAST_CTX_MASK (0x1f << 27) 527#define LAST_CTX(p) ((p) << 27) 528#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 529#define SLOT_FLAG (1 << 0) 530#define EP0_FLAG (1 << 1) 531 532/* dev_info2 bitmasks */ 533/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 534#define MAX_EXIT (0xffff) 535/* Root hub port number that is needed to access the USB device */ 536#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 537#define ROOT_HUB_PORT_MASK (0xff) 538#define ROOT_HUB_PORT_SHIFT (16) 539#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 540/* Maximum number of ports under a hub device */ 541#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 542 543/* tt_info bitmasks */ 544/* 545 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 546 * The Slot ID of the hub that isolates the high speed signaling from 547 * this low or full-speed device. '0' if attached to root hub port. 548 */ 549#define TT_SLOT(p) (((p) & 0xff) << 0) 550/* 551 * The number of the downstream facing port of the high-speed hub 552 * '0' if the device is not low or full speed. 553 */ 554#define TT_PORT(p) (((p) & 0xff) << 8) 555#define TT_THINK_TIME(p) (((p) & 0x3) << 16) 556 557/* dev_state bitmasks */ 558/* USB device address - assigned by the HC */ 559#define DEV_ADDR_MASK (0xff) 560/* bits 8:26 reserved */ 561/* Slot state */ 562#define SLOT_STATE (0x1f << 27) 563#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 564 565#define SLOT_STATE_DISABLED 0 566#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 567#define SLOT_STATE_DEFAULT 1 568#define SLOT_STATE_ADDRESSED 2 569#define SLOT_STATE_CONFIGURED 3 570 571/** 572 * struct xhci_ep_ctx 573 * @ep_info: endpoint state, streams, mult, and interval information. 574 * @ep_info2: information on endpoint type, max packet size, max burst size, 575 * error count, and whether the HC will force an event for all 576 * transactions. 577 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 578 * defines one stream, this points to the endpoint transfer ring. 579 * Otherwise, it points to a stream context array, which has a 580 * ring pointer for each flow. 581 * @tx_info: 582 * Average TRB lengths for the endpoint ring and 583 * max payload within an Endpoint Service Interval Time (ESIT). 584 * 585 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context 586 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes 587 * reserved at the end of the endpoint context for HC internal use. 588 */ 589struct xhci_ep_ctx { 590 __le32 ep_info; 591 __le32 ep_info2; 592 __le64 deq; 593 __le32 tx_info; 594 /* offset 0x14 - 0x1f reserved for HC internal use */ 595 __le32 reserved[3]; 596}; 597 598/* ep_info bitmasks */ 599/* 600 * Endpoint State - bits 0:2 601 * 0 - disabled 602 * 1 - running 603 * 2 - halted due to halt condition - ok to manipulate endpoint ring 604 * 3 - stopped 605 * 4 - TRB error 606 * 5-7 - reserved 607 */ 608#define EP_STATE_MASK (0xf) 609#define EP_STATE_DISABLED 0 610#define EP_STATE_RUNNING 1 611#define EP_STATE_HALTED 2 612#define EP_STATE_STOPPED 3 613#define EP_STATE_ERROR 4 614/* Mult - Max number of burtst within an interval, in EP companion desc. */ 615#define EP_MULT(p) (((p) & 0x3) << 8) 616#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 617/* bits 10:14 are Max Primary Streams */ 618/* bit 15 is Linear Stream Array */ 619/* Interval - period between requests to an endpoint - 125u increments. */ 620#define EP_INTERVAL(p) (((p) & 0xff) << 16) 621#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 622#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 623#define EP_MAXPSTREAMS_MASK (0x1f << 10) 624#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 625/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 626#define EP_HAS_LSA (1 << 15) 627 628/* ep_info2 bitmasks */ 629/* 630 * Force Event - generate transfer events for all TRBs for this endpoint 631 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 632 */ 633#define FORCE_EVENT (0x1) 634#define ERROR_COUNT(p) (((p) & 0x3) << 1) 635#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 636#define EP_TYPE(p) ((p) << 3) 637#define ISOC_OUT_EP 1 638#define BULK_OUT_EP 2 639#define INT_OUT_EP 3 640#define CTRL_EP 4 641#define ISOC_IN_EP 5 642#define BULK_IN_EP 6 643#define INT_IN_EP 7 644/* bit 6 reserved */ 645/* bit 7 is Host Initiate Disable - for disabling stream selection */ 646#define MAX_BURST(p) (((p)&0xff) << 8) 647#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 648#define MAX_PACKET(p) (((p)&0xffff) << 16) 649#define MAX_PACKET_MASK (0xffff) 650#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 651 652/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 653 * USB2.0 spec 9.6.6. 654 */ 655#define GET_MAX_PACKET(p) ((p) & 0x7ff) 656 657/* tx_info bitmasks */ 658#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 659#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 660#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 661#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 662 663/* deq bitmasks */ 664#define EP_CTX_CYCLE_MASK (1 << 0) 665 666/* reserved[0] bitmasks, MediaTek xHCI used */ 667#define EP_BPKTS(p) (((p) & 0x7f) << 0) 668#define EP_BBM(p) (((p) & 0x1) << 11) 669 670/** 671 * struct xhci_input_control_context 672 * Input control context; see section 6.2.5. 673 * 674 * @drop_context: set the bit of the endpoint context you want to disable 675 * @add_context: set the bit of the endpoint context you want to enable 676 */ 677struct xhci_input_control_ctx { 678 volatile __le32 drop_flags; 679 volatile __le32 add_flags; 680 __le32 rsvd2[6]; 681}; 682 683 684/** 685 * struct xhci_device_context_array 686 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 687 */ 688struct xhci_device_context_array { 689 /* 64-bit device addresses; we only write 32-bit addresses */ 690 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 691}; 692/* TODO: write function to set the 64-bit device DMA address */ 693/* 694 * TODO: change this to be dynamically sized at HC mem init time since the HC 695 * might not be able to handle the maximum number of devices possible. 696 */ 697 698 699struct xhci_transfer_event { 700 /* 64-bit buffer address, or immediate data */ 701 __le64 buffer; 702 __le32 transfer_len; 703 /* This field is interpreted differently based on the type of TRB */ 704 volatile __le32 flags; 705}; 706 707/* Transfer event TRB length bit mask */ 708/* bits 0:23 */ 709#define EVENT_TRB_LEN(p) ((p) & 0xffffff) 710 711/** Transfer Event bit fields **/ 712#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 713 714/* Completion Code - only applicable for some types of TRBs */ 715#define COMP_CODE_MASK (0xff << 24) 716#define COMP_CODE_SHIFT (24) 717#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 718 719typedef enum { 720 COMP_SUCCESS = 1, 721 /* Data Buffer Error */ 722 COMP_DB_ERR, /* 2 */ 723 /* Babble Detected Error */ 724 COMP_BABBLE, /* 3 */ 725 /* USB Transaction Error */ 726 COMP_TX_ERR, /* 4 */ 727 /* TRB Error - some TRB field is invalid */ 728 COMP_TRB_ERR, /* 5 */ 729 /* Stall Error - USB device is stalled */ 730 COMP_STALL, /* 6 */ 731 /* Resource Error - HC doesn't have memory for that device configuration */ 732 COMP_ENOMEM, /* 7 */ 733 /* Bandwidth Error - not enough room in schedule for this dev config */ 734 COMP_BW_ERR, /* 8 */ 735 /* No Slots Available Error - HC ran out of device slots */ 736 COMP_ENOSLOTS, /* 9 */ 737 /* Invalid Stream Type Error */ 738 COMP_STREAM_ERR, /* 10 */ 739 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 740 COMP_EBADSLT, /* 11 */ 741 /* Endpoint Not Enabled Error */ 742 COMP_EBADEP,/* 12 */ 743 /* Short Packet */ 744 COMP_SHORT_TX, /* 13 */ 745 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 746 COMP_UNDERRUN, /* 14 */ 747 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 748 COMP_OVERRUN, /* 15 */ 749 /* Virtual Function Event Ring Full Error */ 750 COMP_VF_FULL, /* 16 */ 751 /* Parameter Error - Context parameter is invalid */ 752 COMP_EINVAL, /* 17 */ 753 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 754 COMP_BW_OVER,/* 18 */ 755 /* Context State Error - illegal context state transition requested */ 756 COMP_CTX_STATE,/* 19 */ 757 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 758 COMP_PING_ERR,/* 20 */ 759 /* Event Ring is full */ 760 COMP_ER_FULL,/* 21 */ 761 /* Incompatible Device Error */ 762 COMP_DEV_ERR,/* 22 */ 763 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 764 COMP_MISSED_INT,/* 23 */ 765 /* Successfully stopped command ring */ 766 COMP_CMD_STOP, /* 24 */ 767 /* Successfully aborted current command and stopped command ring */ 768 COMP_CMD_ABORT, /* 25 */ 769 /* Stopped - transfer was terminated by a stop endpoint command */ 770 COMP_STOP,/* 26 */ 771 /* Same as COMP_EP_STOPPED, but the transferred length in the event 772 * is invalid */ 773 COMP_STOP_INVAL, /* 27*/ 774 /* Control Abort Error - Debug Capability - control pipe aborted */ 775 COMP_DBG_ABORT, /* 28 */ 776 /* Max Exit Latency Too Large Error */ 777 COMP_MEL_ERR,/* 29 */ 778 /* TRB type 30 reserved */ 779 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 780 COMP_BUFF_OVER = 31, 781 /* Event Lost Error - xHC has an "internal event overrun condition" */ 782 COMP_ISSUES, /* 32 */ 783 /* Undefined Error - reported when other error codes don't apply */ 784 COMP_UNKNOWN, /* 33 */ 785 /* Invalid Stream ID Error */ 786 COMP_STRID_ERR, /* 34 */ 787 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 788 COMP_2ND_BW_ERR, /* 35 */ 789 /* Split Transaction Error */ 790 COMP_SPLIT_ERR /* 36 */ 791 792} xhci_comp_code; 793 794struct xhci_link_trb { 795 /* 64-bit segment pointer*/ 796 volatile __le64 segment_ptr; 797 volatile __le32 intr_target; 798 volatile __le32 control; 799}; 800 801/* control bitfields */ 802#define LINK_TOGGLE (0x1 << 1) 803 804/* Command completion event TRB */ 805struct xhci_event_cmd { 806 /* Pointer to command TRB, or the value passed by the event data trb */ 807 volatile __le64 cmd_trb; 808 volatile __le32 status; 809 volatile __le32 flags; 810}; 811 812/* flags bitmasks */ 813/* bits 16:23 are the virtual function ID */ 814/* bits 24:31 are the slot ID */ 815#define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) 816#define TRB_TO_SLOT_ID_SHIFT (24) 817#define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) 818#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 819#define SLOT_ID_FOR_TRB_MASK (0xff) 820#define SLOT_ID_FOR_TRB_SHIFT (24) 821 822/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 823#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 824#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 825 826#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 827#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 828#define LAST_EP_INDEX 30 829 830/* Set TR Dequeue Pointer command TRB fields */ 831#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 832#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 833 834 835/* Port Status Change Event TRB fields */ 836/* Port ID - bits 31:24 */ 837#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 838#define PORT_ID_SHIFT (24) 839#define PORT_ID_MASK (0xff << PORT_ID_SHIFT) 840 841/* Normal TRB fields */ 842/* transfer_len bitmasks - bits 0:16 */ 843#define TRB_LEN(p) ((p) & 0x1ffff) 844/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 845#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 846/* Interrupter Target - which MSI-X vector to target the completion event at */ 847#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 848#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 849#define TRB_TBC(p) (((p) & 0x3) << 7) 850#define TRB_TLBPC(p) (((p) & 0xf) << 16) 851 852/* Cycle bit - indicates TRB ownership by HC or HCD */ 853#define TRB_CYCLE (1<<0) 854/* 855 * Force next event data TRB to be evaluated before task switch. 856 * Used to pass OS data back after a TD completes. 857 */ 858#define TRB_ENT (1<<1) 859/* Interrupt on short packet */ 860#define TRB_ISP (1<<2) 861/* Set PCIe no snoop attribute */ 862#define TRB_NO_SNOOP (1<<3) 863/* Chain multiple TRBs into a TD */ 864#define TRB_CHAIN (1<<4) 865/* Interrupt on completion */ 866#define TRB_IOC (1<<5) 867/* The buffer pointer contains immediate data */ 868#define TRB_IDT (1<<6) 869 870/* Block Event Interrupt */ 871#define TRB_BEI (1<<9) 872 873/* Control transfer TRB specific fields */ 874#define TRB_DIR_IN (1<<16) 875#define TRB_TX_TYPE(p) ((p) << 16) 876#define TRB_DATA_OUT 2 877#define TRB_DATA_IN 3 878 879/* Isochronous TRB specific fields */ 880#define TRB_SIA (1 << 31) 881 882struct xhci_generic_trb { 883 volatile __le32 field[4]; 884}; 885 886union xhci_trb { 887 struct xhci_link_trb link; 888 struct xhci_transfer_event trans_event; 889 struct xhci_event_cmd event_cmd; 890 struct xhci_generic_trb generic; 891}; 892 893/* TRB bit mask */ 894#define TRB_TYPE_BITMASK (0xfc00) 895#define TRB_TYPE(p) ((p) << 10) 896#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 897 898/* TRB type IDs */ 899typedef enum { 900 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 901 TRB_NORMAL = 1, 902 /* setup stage for control transfers */ 903 TRB_SETUP, /* 2 */ 904 /* data stage for control transfers */ 905 TRB_DATA, /* 3 */ 906 /* status stage for control transfers */ 907 TRB_STATUS, /* 4 */ 908 /* isoc transfers */ 909 TRB_ISOC, /* 5 */ 910 /* TRB for linking ring segments */ 911 TRB_LINK, /* 6 */ 912 /* TRB for EVENT DATA */ 913 TRB_EVENT_DATA, /* 7 */ 914 /* Transfer Ring No-op (not for the command ring) */ 915 TRB_TR_NOOP, /* 8 */ 916 /* Command TRBs */ 917 /* Enable Slot Command */ 918 TRB_ENABLE_SLOT, /* 9 */ 919 /* Disable Slot Command */ 920 TRB_DISABLE_SLOT, /* 10 */ 921 /* Address Device Command */ 922 TRB_ADDR_DEV, /* 11 */ 923 /* Configure Endpoint Command */ 924 TRB_CONFIG_EP, /* 12 */ 925 /* Evaluate Context Command */ 926 TRB_EVAL_CONTEXT, /* 13 */ 927 /* Reset Endpoint Command */ 928 TRB_RESET_EP, /* 14 */ 929 /* Stop Transfer Ring Command */ 930 TRB_STOP_RING, /* 15 */ 931 /* Set Transfer Ring Dequeue Pointer Command */ 932 TRB_SET_DEQ, /* 16 */ 933 /* Reset Device Command */ 934 TRB_RESET_DEV, /* 17 */ 935 /* Force Event Command (opt) */ 936 TRB_FORCE_EVENT, /* 18 */ 937 /* Negotiate Bandwidth Command (opt) */ 938 TRB_NEG_BANDWIDTH, /* 19 */ 939 /* Set Latency Tolerance Value Command (opt) */ 940 TRB_SET_LT, /* 20 */ 941 /* Get port bandwidth Command */ 942 TRB_GET_BW, /* 21 */ 943 /* Force Header Command - generate a transaction or link management packet */ 944 TRB_FORCE_HEADER, /* 22 */ 945 /* No-op Command - not for transfer rings */ 946 TRB_CMD_NOOP, /* 23 */ 947 /* TRB IDs 24-31 reserved */ 948 /* Event TRBS */ 949 /* Transfer Event */ 950 TRB_TRANSFER = 32, 951 /* Command Completion Event */ 952 TRB_COMPLETION, /* 33 */ 953 /* Port Status Change Event */ 954 TRB_PORT_STATUS, /* 34 */ 955 /* Bandwidth Request Event (opt) */ 956 TRB_BANDWIDTH_EVENT, /* 35 */ 957 /* Doorbell Event (opt) */ 958 TRB_DOORBELL, /* 36 */ 959 /* Host Controller Event */ 960 TRB_HC_EVENT, /* 37 */ 961 /* Device Notification Event - device sent function wake notification */ 962 TRB_DEV_NOTE, /* 38 */ 963 /* MFINDEX Wrap Event - microframe counter wrapped */ 964 TRB_MFINDEX_WRAP, /* 39 */ 965 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 966 /* Nec vendor-specific command completion event. */ 967 TRB_NEC_CMD_COMP = 48, /* 48 */ 968 /* Get NEC firmware revision. */ 969 TRB_NEC_GET_FW, /* 49 */ 970} trb_type; 971 972#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 973/* Above, but for __le32 types -- can avoid work by swapping constants: */ 974#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 975 cpu_to_le32(TRB_TYPE(TRB_LINK))) 976#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 977 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 978 979/* 980 * TRBS_PER_SEGMENT must be a multiple of 4, 981 * since the command ring is 64-byte aligned. 982 * It must also be greater than 16. 983 */ 984#define TRBS_PER_SEGMENT 64 985/* Allow two commands + a link TRB, along with any reserved command TRBs */ 986#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 987#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 988/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 989 * Change this if you change TRBS_PER_SEGMENT! 990 */ 991#define SEGMENT_SHIFT 10 992/* TRB buffer pointers can't cross 64KB boundaries */ 993#define TRB_MAX_BUFF_SHIFT 16 994#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 995 996struct xhci_segment { 997 union xhci_trb *trbs; 998 /* private to HCD */ 999 struct xhci_segment *next; 1000};
1001 1002struct xhci_ring { 1003 struct xhci_segment *first_seg; 1004 union xhci_trb *enqueue; 1005 struct xhci_segment *enq_seg; 1006 union xhci_trb *dequeue; 1007 struct xhci_segment *deq_seg; 1008 /* 1009 * Write the cycle state into the TRB cycle field to give ownership of 1010 * the TRB to the host controller (if we are the producer), or to check 1011 * if we own the TRB (if we are the consumer). See section 4.9.1. 1012 */ 1013 volatile u32 cycle_state; 1014 unsigned int num_segs; 1015}; 1016 1017struct xhci_erst_entry { 1018 /* 64-bit event ring segment address */ 1019 __le64 seg_addr; 1020 __le32 seg_size; 1021 /* Set to zero */ 1022 __le32 rsvd; 1023}; 1024 1025struct xhci_erst { 1026 struct xhci_erst_entry *entries; 1027 unsigned int num_entries; 1028 /* Num entries the ERST can contain */ 1029 unsigned int erst_size; 1030}; 1031 1032struct xhci_scratchpad { 1033 u64 *sp_array; 1034}; 1035 1036/* 1037 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1038 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1039 * meaning 64 ring segments. 1040 * Initial allocated size of the ERST, in number of entries */ 1041#define ERST_NUM_SEGS 1 1042/* Initial number of event segment rings allocated */ 1043#define ERST_ENTRIES 1 1044/* Initial allocated size of the ERST, in number of entries */ 1045#define ERST_SIZE 64 1046/* Poll every 60 seconds */ 1047#define POLL_TIMEOUT 60 1048/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1049#define XHCI_STOP_EP_CMD_TIMEOUT 5 1050/* XXX: Make these module parameters */ 1051 1052struct xhci_virt_ep { 1053 struct xhci_ring *ring; 1054 unsigned int ep_state; 1055#define SET_DEQ_PENDING (1 << 0) 1056#define EP_HALTED (1 << 1) /* For stall handling */ 1057#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 1058/* Transitioning the endpoint to using streams, don't enqueue URBs */ 1059#define EP_GETTING_STREAMS (1 << 3) 1060#define EP_HAS_STREAMS (1 << 4) 1061/* Transitioning the endpoint to not using streams, don't enqueue URBs */ 1062#define EP_GETTING_NO_STREAMS (1 << 5) 1063}; 1064 1065#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 1066 1067struct xhci_virt_device { 1068 struct usb_device *udev; 1069 /* 1070 * Commands to the hardware are passed an "input context" that 1071 * tells the hardware what to change in its data structures. 1072 * The hardware will return changes in an "output context" that 1073 * software must allocate for the hardware. We need to keep 1074 * track of input and output contexts separately because 1075 * these commands might fail and we don't trust the hardware. 1076 */ 1077 struct xhci_container_ctx *out_ctx; 1078 /* Used for addressing devices and configuration changes */ 1079 struct xhci_container_ctx *in_ctx; 1080 /* Rings saved to ensure old alt settings can be re-instated */ 1081#define XHCI_MAX_RINGS_CACHED 31 1082 struct xhci_virt_ep eps[31]; 1083}; 1084 1085/* TODO: copied from ehci.h - can be refactored? */ 1086/* xHCI spec says all registers are little endian */ 1087static inline unsigned int xhci_readl(uint32_t volatile *regs) 1088{ 1089 return readl(regs); 1090} 1091 1092static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) 1093{ 1094 writel(val, regs); 1095} 1096 1097/* 1098 * Registers should always be accessed with double word or quad word accesses. 1099 * Some xHCI implementations may support 64-bit address pointers. Registers 1100 * with 64-bit address pointers should be written to with dword accesses by 1101 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1102 * xHCI implementations that do not support 64-bit address pointers will ignore 1103 * the high dword, and write order is irrelevant. 1104 */ 1105static inline u64 xhci_readq(__le64 volatile *regs) 1106{ 1107 __u32 *ptr = (__u32 *)regs; 1108 u64 val_lo = readl(ptr); 1109 u64 val_hi = readl(ptr + 1); 1110 return val_lo + (val_hi << 32); 1111} 1112 1113static inline void xhci_writeq(__le64 volatile *regs, const u64 val) 1114{ 1115 __u32 *ptr = (__u32 *)regs; 1116 u32 val_lo = lower_32_bits(val); 1117 /* FIXME */ 1118 u32 val_hi = upper_32_bits(val); 1119 writel(val_lo, ptr); 1120 writel(val_hi, ptr + 1); 1121} 1122 1123int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, 1124 struct xhci_hcor **ret_hcor); 1125void xhci_hcd_stop(int index); 1126 1127 1128/************************************************************* 1129 EXTENDED CAPABILITY DEFINITIONS 1130*************************************************************/ 1131/* Up to 16 ms to halt an HC */ 1132#define XHCI_MAX_HALT_USEC (16*1000) 1133/* HC not running - set to 1 when run/stop bit is cleared. */ 1134#define XHCI_STS_HALT (1 << 0) 1135 1136/* HCCPARAMS offset from PCI base address */ 1137#define XHCI_HCC_PARAMS_OFFSET 0x10 1138/* HCCPARAMS contains the first extended capability pointer */ 1139#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 1140 1141/* Command and Status registers offset from the Operational Registers address */ 1142#define XHCI_CMD_OFFSET 0x00 1143#define XHCI_STS_OFFSET 0x04 1144 1145#define XHCI_MAX_EXT_CAPS 50 1146 1147/* Capability Register */ 1148/* bits 7:0 - how long is the Capabilities register */ 1149#define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) 1150 1151/* Extended capability register fields */ 1152#define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) 1153#define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) 1154#define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) 1155/* Extended capability IDs - ID 0 reserved */ 1156#define XHCI_EXT_CAPS_LEGACY 1 1157#define XHCI_EXT_CAPS_PROTOCOL 2 1158#define XHCI_EXT_CAPS_PM 3 1159#define XHCI_EXT_CAPS_VIRT 4 1160#define XHCI_EXT_CAPS_ROUTE 5 1161/* IDs 6-9 reserved */ 1162#define XHCI_EXT_CAPS_DEBUG 10 1163/* USB Legacy Support Capability - section 7.1.1 */ 1164#define XHCI_HC_BIOS_OWNED (1 << 16) 1165#define XHCI_HC_OS_OWNED (1 << 24) 1166 1167/* USB Legacy Support Capability - section 7.1.1 */ 1168/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1169#define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 1170 1171/* USB Legacy Support Control and Status Register - section 7.1.2 */ 1172/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1173#define XHCI_LEGACY_CONTROL_OFFSET (0x04) 1174/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 1175#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 1176 1177/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 1178#define XHCI_L1C (1 << 16) 1179 1180/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 1181#define XHCI_HLC (1 << 19) 1182 1183/* command register values to disable interrupts and halt the HC */ 1184/* start/stop HC execution - do not write unless HC is halted*/ 1185#define XHCI_CMD_RUN (1 << 0) 1186/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 1187#define XHCI_CMD_EIE (1 << 2) 1188/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 1189#define XHCI_CMD_HSEIE (1 << 3) 1190/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 1191#define XHCI_CMD_EWE (1 << 10) 1192 1193#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 1194 1195/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 1196#define XHCI_STS_CNR (1 << 11) 1197 1198struct xhci_ctrl { 1199#if CONFIG_IS_ENABLED(DM_USB) 1200 struct udevice *dev; 1201#endif 1202 struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ 1203 struct xhci_hcor *hcor; 1204 struct xhci_doorbell_array *dba; 1205 struct xhci_run_regs *run_regs; 1206 struct xhci_device_context_array *dcbaa \ 1207 __attribute__ ((aligned(ARCH_DMA_MINALIGN))); 1208 struct xhci_ring *event_ring; 1209 struct xhci_ring *cmd_ring; 1210 struct xhci_ring *transfer_ring; 1211 struct xhci_segment *seg; 1212 struct xhci_intr_reg *ir_set; 1213 struct xhci_erst erst; 1214 struct xhci_erst_entry entry[ERST_NUM_SEGS]; 1215 struct xhci_scratchpad *scratchpad; 1216 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1217 int rootdev; 1218 u16 hci_version; 1219 u32 quirks; 1220#define XHCI_MTK_HOST BIT(0) 1221}; 1222 1223#if CONFIG_IS_ENABLED(DM_USB) 1224#define xhci_to_dev(_ctrl) _ctrl->dev 1225#else 1226#define xhci_to_dev(_ctrl) NULL 1227#endif 1228 1229unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); 1230struct xhci_input_control_ctx 1231 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1232struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, 1233 struct xhci_container_ctx *ctx); 1234struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, 1235 struct xhci_container_ctx *ctx, 1236 unsigned int ep_index); 1237void xhci_endpoint_copy(struct xhci_ctrl *ctrl, 1238 struct xhci_container_ctx *in_ctx, 1239 struct xhci_container_ctx *out_ctx, 1240 unsigned int ep_index); 1241void xhci_slot_copy(struct xhci_ctrl *ctrl, 1242 struct xhci_container_ctx *in_ctx, 1243 struct xhci_container_ctx *out_ctx); 1244void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, 1245 struct usb_device *udev, int hop_portnr); 1246void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, 1247 u32 slot_id, u32 ep_index, trb_type cmd); 1248void xhci_acknowledge_event(struct xhci_ctrl *ctrl); 1249union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); 1250int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, 1251 int length, void *buffer); 1252int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, 1253 struct devrequest *req, int length, void *buffer); 1254int xhci_check_maxpacket(struct usb_device *udev); 1255void xhci_flush_cache(uintptr_t addr, u32 type_len); 1256void xhci_inval_cache(uintptr_t addr, u32 type_len); 1257void xhci_cleanup(struct xhci_ctrl *ctrl); 1258struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs, 1259 bool link_trbs); 1260int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id); 1261int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, 1262 struct xhci_hcor *hcor); 1263 1264/** 1265 * xhci_deregister() - Unregister an XHCI controller 1266 * 1267 * @dev: Controller device 1268 * @return 0 if registered, -ve on error 1269 */ 1270int xhci_deregister(struct udevice *dev); 1271 1272/** 1273 * xhci_register() - Register a new XHCI controller 1274 * 1275 * @dev: Controller device 1276 * @hccr: Host controller control registers 1277 * @hcor: Not sure what this means 1278 * @return 0 if registered, -ve on error 1279 */ 1280int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1281 struct xhci_hcor *hcor); 1282 1283extern struct dm_usb_ops xhci_usb_ops; 1284 1285struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); 1286 1287static inline dma_addr_t xhci_virt_to_bus(struct xhci_ctrl *ctrl, void *addr) 1288{ 1289 return dev_phys_to_bus(xhci_to_dev(ctrl), virt_to_phys(addr)); 1290} 1291 1292static inline void *xhci_bus_to_virt(struct xhci_ctrl *ctrl, dma_addr_t addr) 1293{ 1294 return phys_to_virt(dev_bus_to_phys(xhci_to_dev(ctrl), addr)); 1295} 1296 1297#endif /* HOST_XHCI_H_ */ 1298