LXR uboot/test/dm/mdio

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2019
   4 * Alex Marginean, NXP
   5 */
   6
   7#include <common.h>
   8#include <dm.h>
   9#include <miiphy.h>
  10#include <misc.h>
  11#include <dm/test.h>
  12#include <test/test.h>
  13#include <test/ut.h>
  14
  15/* macros copied over from mdio_sandbox.c */
  16#define SANDBOX_PHY_ADDR        5
  17#define SANDBOX_PHY_REG_CNT     2
  18
  19#define TEST_REG_VALUE          0xabcd
  20
  21static int dm_test_mdio_mux(struct unit_test_state *uts)
  22{
  23        struct uclass *uc;
  24        struct udevice *mux;
  25        struct udevice *mdio_ch0, *mdio_ch1, *mdio;
  26        struct mdio_ops *ops, *ops_parent;
  27        struct mdio_mux_ops *mmops;
  28        u16 reg;
  29
  30        ut_assertok(uclass_get(UCLASS_MDIO_MUX, &uc));
  31
  32        ut_assertok(uclass_get_device_by_name(UCLASS_MDIO_MUX, "mdio-mux-test",
  33                                              &mux));
  34
  35        ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@0",
  36                                              &mdio_ch0));
  37        ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@1",
  38                                              &mdio_ch1));
  39
  40        ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio));
  41
  42        ops = mdio_get_ops(mdio_ch0);
  43        ut_assertnonnull(ops);
  44        ut_assertnonnull(ops->read);
  45        ut_assertnonnull(ops->write);
  46
  47        mmops = mdio_mux_get_ops(mux);
  48        ut_assertnonnull(mmops);
  49        ut_assertnonnull(mmops->select);
  50
  51        ops_parent = mdio_get_ops(mdio);
  52        ut_assertnonnull(ops);
  53        ut_assertnonnull(ops->read);
  54
  55        /*
  56         * mux driver sets last register on the emulated PHY whenever a group
  57         * is selected to the selection #.  Just reading that register from
  58         * either of the child buses should return the id of the child bus
  59         */
  60        reg = ops->read(mdio_ch0, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
  61                        SANDBOX_PHY_REG_CNT - 1);
  62        ut_asserteq(reg, 0);
  63
  64        reg = ops->read(mdio_ch1, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
  65                        SANDBOX_PHY_REG_CNT - 1);
  66        ut_asserteq(reg, 1);
  67
  68        mmops->select(mux, MDIO_MUX_SELECT_NONE, 5);
  69        reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
  70                        SANDBOX_PHY_REG_CNT - 1);
  71        ut_asserteq(reg, 5);
  72
  73        mmops->deselect(mux, 5);
  74        reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
  75                        SANDBOX_PHY_REG_CNT - 1);
  76        ut_asserteq(reg, (u16)MDIO_MUX_SELECT_NONE);
  77
  78        return 0;
  79}
  80
  81DM_TEST(dm_test_mdio_mux, UT_TESTF_SCAN_FDT);
  82