1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2008 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 */ 7 8#ifndef _KWBIMAGE_H_ 9#define _KWBIMAGE_H_ 10 11#include <compiler.h> 12#include <stdint.h> 13 14#ifdef __GNUC__ 15#define __packed __attribute((packed)) 16#else 17#define __packed 18#endif 19 20#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) 21#define MAX_TEMPBUF_LEN 32 22 23/* NAND ECC Mode */ 24#define IBR_HDR_ECC_DEFAULT 0x00 25#define IBR_HDR_ECC_FORCED_HAMMING 0x01 26#define IBR_HDR_ECC_FORCED_RS 0x02 27#define IBR_HDR_ECC_DISABLED 0x03 28 29/* Boot Type - block ID */ 30#define IBR_HDR_I2C_ID 0x4D 31#define IBR_HDR_SPI_ID 0x5A 32#define IBR_HDR_NAND_ID 0x8B 33#define IBR_HDR_SATA_ID 0x78 34#define IBR_HDR_PEX_ID 0x9C 35#define IBR_HDR_UART_ID 0x69 36#define IBR_HDR_SDIO_ID 0xAE 37#define IBR_DEF_ATTRIB 0x00 38 39/* Structure of the main header, version 0 (Kirkwood, Dove) */ 40struct main_hdr_v0 { 41 uint8_t blockid; /* 0x0 */ 42 uint8_t nandeccmode; /* 0x1 */ 43 uint16_t nandpagesize; /* 0x2-0x3 */ 44 uint32_t blocksize; /* 0x4-0x7 */ 45 uint8_t version; /* 0x8 */ 46 uint8_t rsvd1[3]; /* 0x9-0xB */ 47 uint32_t srcaddr; /* 0xC-0xF */ 48 uint32_t destaddr; /* 0x10-0x13 */ 49 uint32_t execaddr; /* 0x14-0x17 */ 50 uint8_t satapiomode; /* 0x18 */ 51 uint8_t rsvd3; /* 0x19 */ 52 uint16_t ddrinitdelay; /* 0x1A-0x1B */ 53 uint16_t rsvd2; /* 0x1C-0x1D */ 54 uint8_t ext; /* 0x1E */ 55 uint8_t checksum; /* 0x1F */ 56} __packed; 57 58struct ext_hdr_v0_reg { 59 uint32_t raddr; 60 uint32_t rdata; 61} __packed; 62 63#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) 64 65struct ext_hdr_v0 { 66 uint32_t offset; 67 uint8_t reserved[0x20 - sizeof(uint32_t)]; 68 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; 69 uint8_t reserved2[7]; 70 uint8_t checksum; 71} __packed; 72 73/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */ 74struct main_hdr_v1 { 75 uint8_t blockid; /* 0x0 */ 76 uint8_t flags; /* 0x1 */ 77 uint16_t nandpagesize; /* 0x2-0x3 */ 78 uint32_t blocksize; /* 0x4-0x7 */ 79 uint8_t version; /* 0x8 */ 80 uint8_t headersz_msb; /* 0x9 */ 81 uint16_t headersz_lsb; /* 0xA-0xB */ 82 uint32_t srcaddr; /* 0xC-0xF */ 83 uint32_t destaddr; /* 0x10-0x13 */ 84 uint32_t execaddr; /* 0x14-0x17 */ 85 uint8_t options; /* 0x18 */ 86 uint8_t nandblocksize; /* 0x19 */ 87 uint8_t nandbadblklocation; /* 0x1A */ 88 uint8_t reserved4; /* 0x1B */ 89 uint16_t reserved5; /* 0x1C-0x1D */ 90 uint8_t ext; /* 0x1E */ 91 uint8_t checksum; /* 0x1F */ 92} __packed; 93 94/* 95 * Main header options 96 */ 97#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0 98#define MAIN_HDR_V1_OPT_BAUD_2400 0x1 99#define MAIN_HDR_V1_OPT_BAUD_4800 0x2 100#define MAIN_HDR_V1_OPT_BAUD_9600 0x3 101#define MAIN_HDR_V1_OPT_BAUD_19200 0x4 102#define MAIN_HDR_V1_OPT_BAUD_38400 0x5 103#define MAIN_HDR_V1_OPT_BAUD_57600 0x6 104#define MAIN_HDR_V1_OPT_BAUD_115200 0x7 105 106/* 107 * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x) 108 */ 109struct opt_hdr_v1 { 110 uint8_t headertype; 111 uint8_t headersz_msb; 112 uint16_t headersz_lsb; 113 char data[0]; 114} __packed; 115 116/* 117 * Public Key data in DER format 118 */ 119struct pubkey_der_v1 { 120 uint8_t key[524]; 121} __packed; 122 123/* 124 * Signature (RSA 2048) 125 */ 126struct sig_v1 { 127 uint8_t sig[256]; 128} __packed; 129 130/* 131 * Structure of secure header (Armada XP/375/38x/39x) 132 */ 133struct secure_hdr_v1 { 134 uint8_t headertype; /* 0x0 */ 135 uint8_t headersz_msb; /* 0x1 */ 136 uint16_t headersz_lsb; /* 0x2 - 0x3 */ 137 uint32_t reserved1; /* 0x4 - 0x7 */ 138 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */ 139 uint8_t jtag_delay; /* 0x214 */ 140 uint8_t reserved2; /* 0x215 */ 141 uint16_t reserved3; /* 0x216 - 0x217 */ 142 uint32_t boxid; /* 0x218 - 0x21B */ 143 uint32_t flashid; /* 0x21C - 0x21F */ 144 struct sig_v1 hdrsig; /* 0x220 - 0x31F */ 145 struct sig_v1 imgsig; /* 0x320 - 0x41F */ 146 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */ 147 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */ 148 uint8_t next; /* 0x25E0 */ 149 uint8_t reserved4; /* 0x25E1 */ 150 uint16_t reserved5; /* 0x25E2 - 0x25E3 */ 151} __packed; 152 153/* 154 * Structure of register set 155 */ 156struct register_set_hdr_v1 { 157 uint8_t headertype; /* 0x0 */ 158 uint8_t headersz_msb; /* 0x1 */ 159 uint16_t headersz_lsb; /* 0x2 - 0x3 */ 160 union { 161 struct { 162 uint32_t address; /* 0x4+8*N - 0x7+8*N */ 163 uint32_t value; /* 0x8+8*N - 0xB+8*N */ 164 } __packed entry; 165 struct { 166 uint8_t next; /* 0xC+8*N */ 167 uint8_t delay; /* 0xD+8*N */ 168 uint16_t reserved; /* 0xE+8*N - 0xF+8*N */ 169 } __packed last_entry; 170 } data[]; 171} __packed; 172 173/* 174 * Value 0 in register_set_hdr_v1 delay field is special. 175 * Instead of delay it setup SDRAM Controller. 176 */ 177#define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0 178#define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1) 179 180/* 181 * Various values for the opt_hdr_v1->headertype field, describing the 182 * different types of optional headers. The "secure" header contains 183 * informations related to secure boot (encryption keys, etc.). The 184 * "binary" header contains ARM binary code to be executed prior to 185 * executing the main payload (usually the bootloader). This is 186 * typically used to execute DDR3 training code. The "register" header 187 * allows to describe a set of (address, value) tuples that are 188 * generally used to configure the DRAM controller. 189 */ 190#define OPT_HDR_V1_SECURE_TYPE 0x1 191#define OPT_HDR_V1_BINARY_TYPE 0x2 192#define OPT_HDR_V1_REGISTER_TYPE 0x3 193 194/* 195 * Byte 8 of the image header contains the version number. In the v0 196 * header, byte 8 was reserved, and always set to 0. In the v1 header, 197 * byte 8 has been changed to a proper field, set to 1. 198 */ 199static inline unsigned int kwbimage_version(const void *header) 200{ 201 const unsigned char *ptr = header; 202 return ptr[8]; 203} 204 205static inline size_t kwbheader_size(const void *header) 206{ 207 if (kwbimage_version(header) == 0) { 208 const struct main_hdr_v0 *hdr = header; 209 210 return sizeof(*hdr) + 211 (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0; 212 } else { 213 const struct main_hdr_v1 *hdr = header; 214 215 return (hdr->headersz_msb << 16) | 216 le16_to_cpu(hdr->headersz_lsb); 217 } 218} 219 220static inline size_t kwbheader_size_for_csum(const void *header) 221{ 222 if (kwbimage_version(header) == 0) 223 return sizeof(struct main_hdr_v0); 224 else 225 return kwbheader_size(header); 226} 227 228static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr) 229{ 230 return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb); 231} 232 233static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr, 234 const void *mhdr_end) 235{ 236 uint32_t ohdr_size; 237 238 if ((void *)(ohdr + 1) > mhdr_end) 239 return 0; 240 241 ohdr_size = opt_hdr_v1_size(ohdr); 242 if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end) 243 return 0; 244 245 return 1; 246} 247 248static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) { 249 struct main_hdr_v1 *mhdr; 250 251 if (kwbimage_version(img) != 1) 252 return NULL; 253 254 mhdr = img; 255 if (mhdr->ext & 0x1) 256 return (struct opt_hdr_v1 *)(mhdr + 1); 257 else 258 return NULL; 259} 260 261static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur) 262{ 263 uint32_t size = opt_hdr_v1_size(cur); 264 265 return (uint8_t *)cur + size - 4; 266} 267 268static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur) 269{ 270 return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur)); 271} 272 273static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur) 274{ 275 if (*opt_hdr_v1_ext(cur) & 0x1) 276 return _opt_hdr_v1_next(cur); 277 else 278 return NULL; 279} 280 281#define for_each_opt_hdr_v1(ohdr, img) \ 282 for ((ohdr) = opt_hdr_v1_first((img)); \ 283 (ohdr) != NULL; \ 284 (ohdr) = opt_hdr_v1_next((ohdr))) 285 286#endif /* _KWBIMAGE_H_ */ 287