LXR xlnxembeddedsw/mcap/linux/mcap

   1/******************************************************************************
   2* Copyright (C) 2014-2015 Xilinx, Inc.  All rights reserved.
   3*
   4* Permission is hereby granted, free of charge, to any person obtaining a copy
   5* of this software and associated documentation files (the "Software"), to deal
   6* in the Software without restriction, including without limitation the rights
   7* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8* copies of the Software, and to permit persons to whom the Software is
   9* furnished to do so, subject to the following conditions:
  10*
  11* The above copyright notice and this permission notice shall be included in
  12* all copies or substantial portions of the Software.
  13*
  14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20* THE SOFTWARE.
  21*
  22* 
  23*
  24******************************************************************************/
  25/*****************************************************************************/
  26/**
  27*
  28* @file mcap_lib.h
  29*  MCAP Interface Library support header file
  30*
  31******************************************************************************/
  32
  33#include <stdio.h>
  34#include <stdlib.h>
  35#include <string.h>
  36#include <ctype.h>
  37#include <sys/types.h>
  38
  39#include "pci.h"
  40#include "lspci.h"
  41#include "byteswap.h"
  42
  43/* Register Definitions */
  44#define MCAP_EXT_CAP_HEADER     0x00
  45#define MCAP_VEND_SPEC_HEADER   0x04
  46#define MCAP_FPGA_JTAG_ID       0x08
  47#define MCAP_FPGA_BIT_VERSION   0x0C
  48#define MCAP_STATUS             0x10
  49#define MCAP_CONTROL            0x14
  50#define MCAP_DATA               0x18
  51#define MCAP_READ_DATA_0        0x1C
  52#define MCAP_READ_DATA_1        0x20
  53#define MCAP_READ_DATA_2        0x24
  54#define MCAP_READ_DATA_3        0x28
  55
  56#define MCAP_CTRL_MODE_MASK             (1 << 0)
  57#define MCAP_CTRL_REG_READ_MASK         (1 << 1)
  58#define MCAP_CTRL_RESET_MASK            (1 << 4)
  59#define MCAP_CTRL_MOD_RESET_MASK        (1 << 5)
  60#define MCAP_CTRL_IN_USE_MASK           (1 << 8)
  61#define MCAP_CTRL_DESIGN_SWITCH_MASK    (1 << 12)
  62#define MCAP_CTRL_DATA_REG_PROT_MASK    (1 << 16)
  63
  64#define MCAP_STS_ERR_MASK               (1 << 0)
  65#define MCAP_STS_EOS_MASK               (1 << 1)
  66#define MCAP_STS_REG_READ_CMP_MASK      (1 << 4)
  67#define MCAP_STS_REG_READ_COUNT_MASK    (7 << 5)
  68#define MCAP_STS_FIFO_OVERFLOW_MASK     (1 << 8)
  69#define MCAP_STS_FIFO_OCCUPANCY_MASK    (15 << 12)
  70#define MCAP_STS_CFG_MCAP_REQ_MASK      (1 << 24)
  71
  72/* Maximum FIFO Depth */
  73#define MCAP_FIFO_DEPTH         16
  74
  75/* PCIe Extended Capability Id */
  76#define MCAP_EXT_CAP_ID         0xB
  77
  78/* Error Values */
  79#define EMCAPREQ        120
  80#define EMCAPRESET      121
  81#define EMCAPMODRESET   122
  82#define EMCAPFULLRESET  123
  83#define EMCAPWRITE      124
  84#define EMCAPREAD       125
  85#define EMCAPCFG        126
  86#define EMCAPBUSWALK    127
  87#define EMCAPCFGACC     128
  88
  89#define EMCAP_EOS_RETRY_COUNT 10
  90#define EMCAP_EOS_LOOP_COUNT 100
  91#define EMCAP_NOOP_VAL  0x2000000
  92
  93/* Bitfile Type */
  94#define EMCAP_CONFIG_FILE        0
  95#define EMCAP_PARTIALCONFIG_FILE 1
  96#undef DEBUG
  97
  98#ifndef DEBUG
  99#define pr_dbg(fmt, ...)        do {} while (0)
 100#else
 101#define pr_dbg  printf
 102#endif
 103
 104#define pr_info printf
 105#define pr_err  printf
 106
 107/* MCAP Device Information */
 108struct mcap_dev {
 109        struct pci_dev *pdev;
 110        struct pci_access *pacc;
 111        unsigned int reg_base;
 112        u32 is_multiplebit;
 113};
 114
 115#define MCapRegWrite(mdev, offset, value) \
 116        pci_write_long(mdev->pdev, mdev->reg_base + offset, value)
 117
 118#define MCapRegRead(mdev, offset) \
 119        pci_read_long(mdev->pdev, mdev->reg_base + offset)
 120
 121#define IsResetSet(mdev) \
 122        (MCapRegRead(mdev, MCAP_CONTROL) & \
 123                MCAP_CTRL_RESET_MASK ? 1 : 0)
 124
 125#define IsModuleResetSet(mdev) \
 126        (MCapRegRead(mdev, MCAP_CONTROL) & \
 127                MCAP_CTRL_MOD_RESET_MASK ? 1 : 0)
 128
 129#define IsConfigureMCapReqSet(mdev) \
 130        (MCapRegRead(mdev, MCAP_STATUS) & \
 131                MCAP_STS_CFG_MCAP_REQ_MASK ? 1 : 0)
 132
 133#define IsErrSet(mdev) \
 134        (MCapRegRead(mdev, MCAP_STATUS) & \
 135                MCAP_STS_ERR_MASK ? 1 : 0)
 136
 137#define IsRegReadComplete(mdev) \
 138        (MCapRegRead(mdev, MCAP_STATUS) & \
 139                MCAP_STS_REG_READ_CMP_MASK ? 1 : 0)
 140
 141#define IsFifoOverflow(mdev) \
 142        (MCapRegRead(mdev, MCAP_STATUS) & \
 143                MCAP_STS_FIFO_OVERFLOW_MASK ? 1 : 0)
 144
 145#define GetRegReadCount(mdev) \
 146        ((MCapRegRead(mdev, MCAP_STATUS) & \
 147                MCAP_STS_REG_READ_COUNT_MASK) >> 5)
 148
 149/* Function Prototypes */
 150struct mcap_dev *MCapLibInit(int device_id);
 151void MCapLibFree(struct mcap_dev *mdev);
 152void MCapDumpRegs(struct mcap_dev *mdev);
 153void MCapDumpReadRegs(struct mcap_dev *mdev);
 154int MCapReset(struct mcap_dev *mdev);
 155int MCapModuleReset(struct mcap_dev *mdev);
 156int MCapFullReset(struct mcap_dev *mdev);
 157int MCapShowDevice(struct mcap_dev *mdev, int verbose);
 158int MCapConfigureFPGA(struct mcap_dev *mdev, char *file_path, u32 bitfile_type);
 159int MCapReadRegisters(struct mcap_dev *mdev, u32 *data);
 160int MCapAccessConfigSpace(struct mcap_dev *mdev, int argc, char **argv);
 161