LXR linux/arch/arm/mach-at91/board-yl-9200.c

   1/*
   2 * linux/arch/arm/mach-at91/board-yl-9200.c
   3 *
   4 * Adapted from various board files in arch/arm/mach-at91
   5 *
   6 * Modifications for YL-9200 platform:
   7 *  Copyright (C) 2007 S. Birtles
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24#include <linux/types.h>
  25#include <linux/init.h>
  26#include <linux/mm.h>
  27#include <linux/module.h>
  28#include <linux/dma-mapping.h>
  29#include <linux/platform_device.h>
  30#include <linux/spi/spi.h>
  31#include <linux/spi/ads7846.h>
  32#include <linux/mtd/physmap.h>
  33#include <linux/gpio_keys.h>
  34#include <linux/input.h>
  35
  36#include <asm/setup.h>
  37#include <asm/mach-types.h>
  38#include <asm/irq.h>
  39
  40#include <asm/mach/arch.h>
  41#include <asm/mach/map.h>
  42#include <asm/mach/irq.h>
  43
  44#include <mach/hardware.h>
  45#include <mach/board.h>
  46#include <mach/gpio.h>
  47#include <mach/at91rm9200_mc.h>
  48
  49#include "generic.h"
  50
  51
  52static void __init yl9200_map_io(void)
  53{
  54        /* Initialize processor: 18.432 MHz crystal */
  55        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
  56
  57        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
  58        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
  59
  60        /* DBGU on ttyS0. (Rx & Tx only) */
  61        at91_register_uart(0, 0, 0);
  62
  63        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
  64        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
  65                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
  66                        | ATMEL_UART_RI);
  67
  68        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
  69        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
  70
  71        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
  72        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
  73
  74        /* set serial console to ttyS0 (ie, DBGU) */
  75        at91_set_serial_console(0);
  76}
  77
  78static void __init yl9200_init_irq(void)
  79{
  80        at91rm9200_init_interrupts(NULL);
  81}
  82
  83
  84/*
  85 * LEDs
  86 */
  87static struct gpio_led yl9200_leds[] = {
  88        {       /* D2 */
  89                .name                   = "led2",
  90                .gpio                   = AT91_PIN_PB17,
  91                .active_low             = 1,
  92                .default_trigger        = "timer",
  93        },
  94        {       /* D3 */
  95                .name                   = "led3",
  96                .gpio                   = AT91_PIN_PB16,
  97                .active_low             = 1,
  98                .default_trigger        = "heartbeat",
  99        },
 100        {       /* D4 */
 101                .name                   = "led4",
 102                .gpio                   = AT91_PIN_PB15,
 103                .active_low             = 1,
 104        },
 105        {       /* D5 */
 106                .name                   = "led5",
 107                .gpio                   = AT91_PIN_PB8,
 108                .active_low             = 1,
 109        }
 110};
 111
 112/*
 113 * Ethernet
 114 */
 115static struct at91_eth_data __initdata yl9200_eth_data = {
 116        .phy_irq_pin            = AT91_PIN_PB28,
 117        .is_rmii                = 1,
 118};
 119
 120/*
 121 * USB Host
 122 */
 123static struct at91_usbh_data __initdata yl9200_usbh_data = {
 124        .ports                  = 1,    /* PQFP version of AT91RM9200 */
 125};
 126
 127/*
 128 * USB Device
 129 */
 130static struct at91_udc_data __initdata yl9200_udc_data = {
 131        .pullup_pin             = AT91_PIN_PC4,
 132        .vbus_pin               = AT91_PIN_PC5,
 133        .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
 134
 135};
 136
 137/*
 138 * MMC
 139 */
 140static struct at91_mmc_data __initdata yl9200_mmc_data = {
 141        .det_pin        = AT91_PIN_PB9,
 142        // .wp_pin      = ... not connected
 143        .wire4          = 1,
 144};
 145
 146/*
 147 * NAND Flash
 148 */
 149static struct mtd_partition __initdata yl9200_nand_partition[] = {
 150        {
 151                .name   = "AT91 NAND partition 1, boot",
 152                .offset = 0,
 153                .size   = SZ_256K
 154        },
 155        {
 156                .name   = "AT91 NAND partition 2, kernel",
 157                .offset = MTDPART_OFS_NXTBLK,
 158                .size   = (2 * SZ_1M) - SZ_256K
 159        },
 160        {
 161                .name   = "AT91 NAND partition 3, filesystem",
 162                .offset = MTDPART_OFS_NXTBLK,
 163                .size   = 14 * SZ_1M
 164        },
 165        {
 166                .name   = "AT91 NAND partition 4, storage",
 167                .offset = MTDPART_OFS_NXTBLK,
 168                .size   = SZ_16M
 169        },
 170        {
 171                .name   = "AT91 NAND partition 5, ext-fs",
 172                .offset = MTDPART_OFS_NXTBLK,
 173                .size   = SZ_32M
 174        }
 175};
 176
 177static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
 178{
 179        *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
 180        return yl9200_nand_partition;
 181}
 182
 183static struct atmel_nand_data __initdata yl9200_nand_data = {
 184        .ale            = 6,
 185        .cle            = 7,
 186        // .det_pin     = ... not connected
 187        .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
 188        .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
 189        .partition_info = nand_partitions,
 190};
 191
 192/*
 193 * NOR Flash
 194 */
 195#define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
 196#define YL9200_FLASH_SIZE       SZ_16M
 197
 198static struct mtd_partition yl9200_flash_partitions[] = {
 199        {
 200                .name           = "Bootloader",
 201                .offset         = 0,
 202                .size           = SZ_256K,
 203                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 204        },
 205        {
 206                .name           = "Kernel",
 207                .offset         = MTDPART_OFS_NXTBLK,
 208                .size           = (2 * SZ_1M) - SZ_256K
 209        },
 210        {
 211                .name           = "Filesystem",
 212                .offset         = MTDPART_OFS_NXTBLK,
 213                .size           = MTDPART_SIZ_FULL
 214        }
 215};
 216
 217static struct physmap_flash_data yl9200_flash_data = {
 218        .width          = 2,
 219        .parts          = yl9200_flash_partitions,
 220        .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
 221};
 222
 223static struct resource yl9200_flash_resources[] = {
 224        {
 225                .start  = YL9200_FLASH_BASE,
 226                .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
 227                .flags  = IORESOURCE_MEM,
 228        }
 229};
 230
 231static struct platform_device yl9200_flash = {
 232        .name           = "physmap-flash",
 233        .id             = 0,
 234        .dev            = {
 235                                .platform_data  = &yl9200_flash_data,
 236                        },
 237        .resource       = yl9200_flash_resources,
 238        .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
 239};
 240
 241/*
 242 * I2C (TWI)
 243 */
 244static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
 245        {       /* EEPROM */
 246                I2C_BOARD_INFO("24c128", 0x50),
 247        }
 248};
 249
 250/*
 251 * GPIO Buttons
 252*/
 253#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 254static struct gpio_keys_button yl9200_buttons[] = {
 255        {
 256                .gpio           = AT91_PIN_PA24,
 257                .code           = BTN_2,
 258                .desc           = "SW2",
 259                .active_low     = 1,
 260                .wakeup         = 1,
 261        },
 262        {
 263                .gpio           = AT91_PIN_PB1,
 264                .code           = BTN_3,
 265                .desc           = "SW3",
 266                .active_low     = 1,
 267                .wakeup         = 1,
 268        },
 269        {
 270                .gpio           = AT91_PIN_PB2,
 271                .code           = BTN_4,
 272                .desc           = "SW4",
 273                .active_low     = 1,
 274                .wakeup         = 1,
 275        },
 276        {
 277                .gpio           = AT91_PIN_PB6,
 278                .code           = BTN_5,
 279                .desc           = "SW5",
 280                .active_low     = 1,
 281                .wakeup         = 1,
 282        }
 283};
 284
 285static struct gpio_keys_platform_data yl9200_button_data = {
 286        .buttons        = yl9200_buttons,
 287        .nbuttons       = ARRAY_SIZE(yl9200_buttons),
 288};
 289
 290static struct platform_device yl9200_button_device = {
 291        .name           = "gpio-keys",
 292        .id             = -1,
 293        .num_resources  = 0,
 294        .dev            = {
 295                .platform_data  = &yl9200_button_data,
 296        }
 297};
 298
 299static void __init yl9200_add_device_buttons(void)
 300{
 301        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
 302        at91_set_deglitch(AT91_PIN_PA24, 1);
 303        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
 304        at91_set_deglitch(AT91_PIN_PB1, 1);
 305        at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
 306        at91_set_deglitch(AT91_PIN_PB2, 1);
 307        at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
 308        at91_set_deglitch(AT91_PIN_PB6, 1);
 309
 310        /* Enable buttons (Sheet 5) */
 311        at91_set_gpio_output(AT91_PIN_PB7, 1);
 312
 313        platform_device_register(&yl9200_button_device);
 314}
 315#else
 316static void __init yl9200_add_device_buttons(void) {}
 317#endif
 318
 319/*
 320 * Touchscreen
 321 */
 322#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 323static int ads7843_pendown_state(void)
 324{
 325        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
 326}
 327
 328static struct ads7846_platform_data ads_info = {
 329        .model                  = 7843,
 330        .x_min                  = 150,
 331        .x_max                  = 3830,
 332        .y_min                  = 190,
 333        .y_max                  = 3830,
 334        .vref_delay_usecs       = 100,
 335
 336        /* For a 8" touch-screen */
 337        // .x_plate_ohms                = 603,
 338        // .y_plate_ohms                = 332,
 339
 340        /* For a 10.4" touch-screen */
 341        // .x_plate_ohms                = 611,
 342        // .y_plate_ohms                = 325,
 343
 344        .x_plate_ohms           = 576,
 345        .y_plate_ohms           = 366,
 346
 347        .pressure_max           = 15000, /* generally nonsense on the 7843 */
 348        .debounce_max           = 1,
 349        .debounce_rep           = 0,
 350        .debounce_tol           = (~0),
 351        .get_pendown_state      = ads7843_pendown_state,
 352};
 353
 354static void __init yl9200_add_device_ts(void)
 355{
 356        at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
 357        at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
 358}
 359#else
 360static void __init yl9200_add_device_ts(void) {}
 361#endif
 362
 363/*
 364 * SPI devices
 365 */
 366static struct spi_board_info yl9200_spi_devices[] = {
 367#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 368        {       /* Touchscreen */
 369                .modalias       = "ads7846",
 370                .chip_select    = 0,
 371                .max_speed_hz   = 5000 * 26,
 372                .platform_data  = &ads_info,
 373                .irq            = AT91_PIN_PB11,
 374        },
 375#endif
 376        {       /* CAN */
 377                .modalias       = "mcp2510",
 378                .chip_select    = 1,
 379                .max_speed_hz   = 25000 * 26,
 380                .irq            = AT91_PIN_PC0,
 381        }
 382};
 383
 384/*
 385 * LCD / VGA
 386 *
 387 * EPSON S1D13806 FB (discontinued chip)
 388 * EPSON S1D13506 FB
 389 */
 390#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 391#include <video/s1d13xxxfb.h>
 392
 393
 394static void __init yl9200_init_video(void)
 395{
 396        /* NWAIT Signal */
 397        at91_set_A_periph(AT91_PIN_PC6, 0);
 398
 399        /* Initialization of the Static Memory Controller for Chip Select 2 */
 400        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
 401                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
 402                        | AT91_SMC_TDF_(0x100)                  /* float time */
 403        );
 404}
 405
 406static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
 407{
 408        {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
 409        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 410        {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
 411        {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
 412        {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
 413        {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
 414        {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
 415        {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
 416        {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
 417        {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
 418        {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
 419        {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
 420        {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
 421        {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
 422        {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
 423        {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
 424        {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
 425        {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
 426        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
 427        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
 428        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
 429        {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
 430        {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
 431        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
 432        {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
 433        {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
 434        {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
 435        {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
 436        {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
 437        {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
 438        {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
 439        {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
 440        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
 441        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
 442        {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
 443        {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
 444        {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
 445        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
 446        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
 447        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
 448        {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
 449        {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
 450        {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
 451        {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
 452        {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
 453        {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
 454        {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
 455        {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
 456        {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
 457        {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
 458        {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
 459        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
 460        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
 461        {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
 462        {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
 463        {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
 464        {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
 465        {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
 466        {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
 467        {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
 468        {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
 469        {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
 470        {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
 471        {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
 472        {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
 473        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
 474        {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
 475        {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
 476        {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
 477        {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
 478        {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
 479        {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
 480        {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
 481        {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
 482        {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
 483        {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
 484        {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
 485        {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
 486        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
 487        {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
 488        {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
 489        {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
 490        {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
 491        {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
 492        {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
 493        {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
 494        {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
 495        {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
 496        {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
 497        {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
 498        {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
 499        {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
 500        {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
 501        {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
 502        {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
 503        {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
 504        {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
 505        {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
 506        {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
 507        {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
 508        {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
 509        {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
 510        {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
 511        {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
 512        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 513};
 514
 515static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
 516        .initregs               = yl9200_s1dfb_initregs,
 517        .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
 518        .platform_init_video    = yl9200_init_video,
 519};
 520
 521#define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
 522#define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
 523#define YL9200_FB_VMEM_SIZE     SZ_2M
 524
 525static struct resource yl9200_s1dfb_resource[] = {
 526        [0] = { /* video mem */
 527                .name   = "s1d13xxxfb memory",
 528                .start  = YL9200_FB_VMEM_BASE,
 529                .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
 530                .flags  = IORESOURCE_MEM,
 531        },
 532        [1] = { /* video registers */
 533                .name   = "s1d13xxxfb registers",
 534                .start  = YL9200_FB_REG_BASE,
 535                .end    = YL9200_FB_REG_BASE + SZ_512 -1,
 536                .flags  = IORESOURCE_MEM,
 537        },
 538};
 539
 540static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
 541
 542static struct platform_device yl9200_s1dfb_device = {
 543        .name           = "s1d13806fb",
 544        .id             = -1,
 545        .dev    = {
 546                .dma_mask               = &s1dfb_dmamask,
 547                .coherent_dma_mask      = DMA_BIT_MASK(32),
 548                .platform_data          = &yl9200_s1dfb_pdata,
 549        },
 550        .resource       = yl9200_s1dfb_resource,
 551        .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
 552};
 553
 554void __init yl9200_add_device_video(void)
 555{
 556        platform_device_register(&yl9200_s1dfb_device);
 557}
 558#else
 559void __init yl9200_add_device_video(void) {}
 560#endif
 561
 562
 563static void __init yl9200_board_init(void)
 564{
 565        /* Serial */
 566        at91_add_device_serial();
 567        /* Ethernet */
 568        at91_add_device_eth(&yl9200_eth_data);
 569        /* USB Host */
 570        at91_add_device_usbh(&yl9200_usbh_data);
 571        /* USB Device */
 572        at91_add_device_udc(&yl9200_udc_data);
 573        /* I2C */
 574        at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
 575        /* MMC */
 576        at91_add_device_mmc(0, &yl9200_mmc_data);
 577        /* NAND */
 578        at91_add_device_nand(&yl9200_nand_data);
 579        /* NOR Flash */
 580        platform_device_register(&yl9200_flash);
 581#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 582        /* SPI */
 583        at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
 584        /* Touchscreen */
 585        yl9200_add_device_ts();
 586#endif
 587        /* LEDs. */
 588        at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
 589        /* Push Buttons */
 590        yl9200_add_device_buttons();
 591        /* VGA */
 592        yl9200_add_device_video();
 593}
 594
 595MACHINE_START(YL9200, "uCdragon YL-9200")
 596        /* Maintainer: S.Birtles */
 597        .phys_io        = AT91_BASE_SYS,
 598        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
 599        .boot_params    = AT91_SDRAM_BASE + 0x100,
 600        .timer          = &at91rm9200_timer,
 601        .map_io         = yl9200_map_io,
 602        .init_irq       = yl9200_init_irq,
 603        .init_machine   = yl9200_board_init,
 604MACHINE_END
 605