LXR qemu/exec-all.h

   1/*
   2 * internal execution defines for qemu
   3 *
   4 *  Copyright (c) 2003 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef _EXEC_ALL_H_
  21#define _EXEC_ALL_H_
  22
  23#include "qemu-common.h"
  24
  25/* allow to see translation results - the slowdown should be negligible, so we leave it */
  26#define DEBUG_DISAS
  27
  28/* Page tracking code uses ram addresses in system mode, and virtual
  29   addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30   type.  */
  31#if defined(CONFIG_USER_ONLY)
  32typedef abi_ulong tb_page_addr_t;
  33#else
  34typedef ram_addr_t tb_page_addr_t;
  35#endif
  36
  37/* is_jmp field values */
  38#define DISAS_NEXT    0 /* next instruction can be analyzed */
  39#define DISAS_JUMP    1 /* only pc was modified dynamically */
  40#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41#define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43typedef struct TranslationBlock TranslationBlock;
  44
  45/* XXX: make safe guess about sizes */
  46#define MAX_OP_PER_INSTR 96
  47
  48#if HOST_LONG_BITS == 32
  49#define MAX_OPC_PARAM_PER_ARG 2
  50#else
  51#define MAX_OPC_PARAM_PER_ARG 1
  52#endif
  53#define MAX_OPC_PARAM_IARGS 4
  54#define MAX_OPC_PARAM_OARGS 1
  55#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  56
  57/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  58 * and up to 4 + N parameters on 64-bit archs
  59 * (N = number of input arguments + output arguments).  */
  60#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  61#define OPC_BUF_SIZE 640
  62#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  63
  64/* Maximum size a TCG op can expand to.  This is complicated because a
  65   single op may require several host instructions and register reloads.
  66   For now take a wild guess at 192 bytes, which should allow at least
  67   a couple of fixup instructions per argument.  */
  68#define TCG_MAX_OP_SIZE 192
  69
  70#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  71
  72extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  73extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  74extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  75
  76#include "qemu-log.h"
  77
  78void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  79void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  80void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  81                 unsigned long searched_pc, int pc_pos, void *puc);
  82
  83void cpu_gen_init(void);
  84int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  85                 int *gen_code_size_ptr);
  86int cpu_restore_state(struct TranslationBlock *tb,
  87                      CPUState *env, unsigned long searched_pc,
  88                      void *puc);
  89void cpu_resume_from_signal(CPUState *env1, void *puc);
  90void cpu_io_recompile(CPUState *env, void *retaddr);
  91TranslationBlock *tb_gen_code(CPUState *env, 
  92                              target_ulong pc, target_ulong cs_base, int flags,
  93                              int cflags);
  94void cpu_exec_init(CPUState *env);
  95void QEMU_NORETURN cpu_loop_exit(void);
  96int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  97void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  98                                   int is_cpu_write_access);
  99void tb_invalidate_page_range(target_ulong start, target_ulong end);
 100void tlb_flush_page(CPUState *env, target_ulong addr);
 101void tlb_flush(CPUState *env, int flush_global);
 102#if !defined(CONFIG_USER_ONLY)
 103void tlb_set_page(CPUState *env, target_ulong vaddr,
 104                  target_phys_addr_t paddr, int prot,
 105                  int mmu_idx, target_ulong size);
 106#endif
 107
 108#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 109
 110#define CODE_GEN_PHYS_HASH_BITS     15
 111#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 112
 113#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 114
 115/* estimated block size for TB allocation */
 116/* XXX: use a per code average code fragment size and modulate it
 117   according to the host CPU */
 118#if defined(CONFIG_SOFTMMU)
 119#define CODE_GEN_AVG_BLOCK_SIZE 128
 120#else
 121#define CODE_GEN_AVG_BLOCK_SIZE 64
 122#endif
 123
 124#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
 125#define USE_DIRECT_JUMP
 126#endif
 127
 128struct TranslationBlock {
 129    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 130    target_ulong cs_base; /* CS base for this block */
 131    uint64_t flags; /* flags defining in which context the code was generated */
 132    uint16_t size;      /* size of target code for this block (1 <=
 133                           size <= TARGET_PAGE_SIZE) */
 134    uint16_t cflags;    /* compile flags */
 135#define CF_COUNT_MASK  0x7fff
 136#define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 137
 138    uint8_t *tc_ptr;    /* pointer to the translated code */
 139    /* next matching tb for physical address. */
 140    struct TranslationBlock *phys_hash_next;
 141    /* first and second physical page containing code. The lower bit
 142       of the pointer tells the index in page_next[] */
 143    struct TranslationBlock *page_next[2];
 144    tb_page_addr_t page_addr[2];
 145
 146    /* the following data are used to directly call another TB from
 147       the code of this one. */
 148    uint16_t tb_next_offset[2]; /* offset of original jump target */
 149#ifdef USE_DIRECT_JUMP
 150    uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 151#else
 152    unsigned long tb_next[2]; /* address of jump generated code */
 153#endif
 154    /* list of TBs jumping to this one. This is a circular list using
 155       the two least significant bits of the pointers to tell what is
 156       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 157       jmp_first */
 158    struct TranslationBlock *jmp_next[2];
 159    struct TranslationBlock *jmp_first;
 160    uint32_t icount;
 161};
 162
 163static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 164{
 165    target_ulong tmp;
 166    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 167    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 168}
 169
 170static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 171{
 172    target_ulong tmp;
 173    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 174    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 175            | (tmp & TB_JMP_ADDR_MASK));
 176}
 177
 178static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 179{
 180    return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
 181}
 182
 183TranslationBlock *tb_alloc(target_ulong pc);
 184void tb_free(TranslationBlock *tb);
 185void tb_flush(CPUState *env);
 186void tb_link_page(TranslationBlock *tb,
 187                  tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
 188void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 189
 190extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 191
 192#if defined(USE_DIRECT_JUMP)
 193
 194#if defined(_ARCH_PPC)
 195void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 196#define tb_set_jmp_target1 ppc_tb_set_jmp_target
 197#elif defined(__i386__) || defined(__x86_64__)
 198static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 199{
 200    /* patch the branch destination */
 201    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 202    /* no need to flush icache explicitly */
 203}
 204#elif defined(__arm__)
 205static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 206{
 207#if !QEMU_GNUC_PREREQ(4, 1)
 208    register unsigned long _beg __asm ("a1");
 209    register unsigned long _end __asm ("a2");
 210    register unsigned long _flg __asm ("a3");
 211#endif
 212
 213    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 214    *(uint32_t *)jmp_addr =
 215        (*(uint32_t *)jmp_addr & ~0xffffff)
 216        | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 217
 218#if QEMU_GNUC_PREREQ(4, 1)
 219    __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 220#else
 221    /* flush icache */
 222    _beg = jmp_addr;
 223    _end = jmp_addr + 4;
 224    _flg = 0;
 225    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 226#endif
 227}
 228#endif
 229
 230static inline void tb_set_jmp_target(TranslationBlock *tb,
 231                                     int n, unsigned long addr)
 232{
 233    unsigned long offset;
 234
 235    offset = tb->tb_jmp_offset[n];
 236    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 237}
 238
 239#else
 240
 241/* set the jump target */
 242static inline void tb_set_jmp_target(TranslationBlock *tb,
 243                                     int n, unsigned long addr)
 244{
 245    tb->tb_next[n] = addr;
 246}
 247
 248#endif
 249
 250static inline void tb_add_jump(TranslationBlock *tb, int n,
 251                               TranslationBlock *tb_next)
 252{
 253    /* NOTE: this test is only needed for thread safety */
 254    if (!tb->jmp_next[n]) {
 255        /* patch the native jump address */
 256        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 257
 258        /* add in TB jmp circular list */
 259        tb->jmp_next[n] = tb_next->jmp_first;
 260        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 261    }
 262}
 263
 264TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 265
 266#include "qemu-lock.h"
 267
 268extern spinlock_t tb_lock;
 269
 270extern int tb_invalidated_flag;
 271
 272#if !defined(CONFIG_USER_ONLY)
 273
 274extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 275extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 276extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 277
 278void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 279              void *retaddr);
 280
 281#include "softmmu_defs.h"
 282
 283#define ACCESS_TYPE (NB_MMU_MODES + 1)
 284#define MEMSUFFIX _code
 285#define env cpu_single_env
 286
 287#define DATA_SIZE 1
 288#include "softmmu_header.h"
 289
 290#define DATA_SIZE 2
 291#include "softmmu_header.h"
 292
 293#define DATA_SIZE 4
 294#include "softmmu_header.h"
 295
 296#define DATA_SIZE 8
 297#include "softmmu_header.h"
 298
 299#undef ACCESS_TYPE
 300#undef MEMSUFFIX
 301#undef env
 302
 303#endif
 304
 305#if defined(CONFIG_USER_ONLY)
 306static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 307{
 308    return addr;
 309}
 310#else
 311/* NOTE: this function can trigger an exception */
 312/* NOTE2: the returned address is not exactly the physical address: it
 313   is the offset relative to phys_ram_base */
 314static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 315{
 316    int mmu_idx, page_index, pd;
 317    void *p;
 318
 319    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 320    mmu_idx = cpu_mmu_index(env1);
 321    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 322                 (addr & TARGET_PAGE_MASK))) {
 323        ldub_code(addr);
 324    }
 325    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 326    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 327#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 328        do_unassigned_access(addr, 0, 1, 0, 4);
 329#else
 330        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 331#endif
 332    }
 333    p = (void *)(unsigned long)addr
 334        + env1->tlb_table[mmu_idx][page_index].addend;
 335    return qemu_ram_addr_from_host_nofail(p);
 336}
 337#endif
 338
 339typedef void (CPUDebugExcpHandler)(CPUState *env);
 340
 341CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 342
 343/* vl.c */
 344extern int singlestep;
 345
 346/* cpu-exec.c */
 347extern volatile sig_atomic_t exit_request;
 348
 349#endif
 350