1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include "config.h"
20#include "qemu-common.h"
21#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
28#include <fcntl.h>
29
30#include "qemu.h"
31#else
32#include "monitor.h"
33#include "qemu-char.h"
34#include "sysemu.h"
35#include "gdbstub.h"
36#endif
37
38#define MAX_PACKET_LENGTH 4096
39
40#include "cpu.h"
41#include "qemu_socket.h"
42#include "kvm.h"
43
44
45enum {
46 GDB_SIGNAL_0 = 0,
47 GDB_SIGNAL_INT = 2,
48 GDB_SIGNAL_QUIT = 3,
49 GDB_SIGNAL_TRAP = 5,
50 GDB_SIGNAL_ABRT = 6,
51 GDB_SIGNAL_ALRM = 14,
52 GDB_SIGNAL_IO = 23,
53 GDB_SIGNAL_XCPU = 24,
54 GDB_SIGNAL_UNKNOWN = 143
55};
56
57#ifdef CONFIG_USER_ONLY
58
59
60
61
62
63
64static int gdb_signal_table[] = {
65 0,
66 TARGET_SIGHUP,
67 TARGET_SIGINT,
68 TARGET_SIGQUIT,
69 TARGET_SIGILL,
70 TARGET_SIGTRAP,
71 TARGET_SIGABRT,
72 -1,
73 TARGET_SIGFPE,
74 TARGET_SIGKILL,
75 TARGET_SIGBUS,
76 TARGET_SIGSEGV,
77 TARGET_SIGSYS,
78 TARGET_SIGPIPE,
79 TARGET_SIGALRM,
80 TARGET_SIGTERM,
81 TARGET_SIGURG,
82 TARGET_SIGSTOP,
83 TARGET_SIGTSTP,
84 TARGET_SIGCONT,
85 TARGET_SIGCHLD,
86 TARGET_SIGTTIN,
87 TARGET_SIGTTOU,
88 TARGET_SIGIO,
89 TARGET_SIGXCPU,
90 TARGET_SIGXFSZ,
91 TARGET_SIGVTALRM,
92 TARGET_SIGPROF,
93 TARGET_SIGWINCH,
94 -1,
95 TARGET_SIGUSR1,
96 TARGET_SIGUSR2,
97#ifdef TARGET_SIGPWR
98 TARGET_SIGPWR,
99#else
100 -1,
101#endif
102 -1,
103 -1,
104 -1,
105 -1,
106 -1,
107 -1,
108 -1,
109 -1,
110 -1,
111 -1,
112 -1,
113 -1,
114#ifdef __SIGRTMIN
115 __SIGRTMIN + 1,
116 __SIGRTMIN + 2,
117 __SIGRTMIN + 3,
118 __SIGRTMIN + 4,
119 __SIGRTMIN + 5,
120 __SIGRTMIN + 6,
121 __SIGRTMIN + 7,
122 __SIGRTMIN + 8,
123 __SIGRTMIN + 9,
124 __SIGRTMIN + 10,
125 __SIGRTMIN + 11,
126 __SIGRTMIN + 12,
127 __SIGRTMIN + 13,
128 __SIGRTMIN + 14,
129 __SIGRTMIN + 15,
130 __SIGRTMIN + 16,
131 __SIGRTMIN + 17,
132 __SIGRTMIN + 18,
133 __SIGRTMIN + 19,
134 __SIGRTMIN + 20,
135 __SIGRTMIN + 21,
136 __SIGRTMIN + 22,
137 __SIGRTMIN + 23,
138 __SIGRTMIN + 24,
139 __SIGRTMIN + 25,
140 __SIGRTMIN + 26,
141 __SIGRTMIN + 27,
142 __SIGRTMIN + 28,
143 __SIGRTMIN + 29,
144 __SIGRTMIN + 30,
145 __SIGRTMIN + 31,
146 -1,
147 __SIGRTMIN,
148 __SIGRTMIN + 32,
149 __SIGRTMIN + 33,
150 __SIGRTMIN + 34,
151 __SIGRTMIN + 35,
152 __SIGRTMIN + 36,
153 __SIGRTMIN + 37,
154 __SIGRTMIN + 38,
155 __SIGRTMIN + 39,
156 __SIGRTMIN + 40,
157 __SIGRTMIN + 41,
158 __SIGRTMIN + 42,
159 __SIGRTMIN + 43,
160 __SIGRTMIN + 44,
161 __SIGRTMIN + 45,
162 __SIGRTMIN + 46,
163 __SIGRTMIN + 47,
164 __SIGRTMIN + 48,
165 __SIGRTMIN + 49,
166 __SIGRTMIN + 50,
167 __SIGRTMIN + 51,
168 __SIGRTMIN + 52,
169 __SIGRTMIN + 53,
170 __SIGRTMIN + 54,
171 __SIGRTMIN + 55,
172 __SIGRTMIN + 56,
173 __SIGRTMIN + 57,
174 __SIGRTMIN + 58,
175 __SIGRTMIN + 59,
176 __SIGRTMIN + 60,
177 __SIGRTMIN + 61,
178 __SIGRTMIN + 62,
179 __SIGRTMIN + 63,
180 __SIGRTMIN + 64,
181 __SIGRTMIN + 65,
182 __SIGRTMIN + 66,
183 __SIGRTMIN + 67,
184 __SIGRTMIN + 68,
185 __SIGRTMIN + 69,
186 __SIGRTMIN + 70,
187 __SIGRTMIN + 71,
188 __SIGRTMIN + 72,
189 __SIGRTMIN + 73,
190 __SIGRTMIN + 74,
191 __SIGRTMIN + 75,
192 __SIGRTMIN + 76,
193 __SIGRTMIN + 77,
194 __SIGRTMIN + 78,
195 __SIGRTMIN + 79,
196 __SIGRTMIN + 80,
197 __SIGRTMIN + 81,
198 __SIGRTMIN + 82,
199 __SIGRTMIN + 83,
200 __SIGRTMIN + 84,
201 __SIGRTMIN + 85,
202 __SIGRTMIN + 86,
203 __SIGRTMIN + 87,
204 __SIGRTMIN + 88,
205 __SIGRTMIN + 89,
206 __SIGRTMIN + 90,
207 __SIGRTMIN + 91,
208 __SIGRTMIN + 92,
209 __SIGRTMIN + 93,
210 __SIGRTMIN + 94,
211 __SIGRTMIN + 95,
212 -1,
213 -1,
214 -1,
215 -1,
216 -1,
217 -1,
218 -1,
219 -1,
220 -1
221#endif
222};
223#else
224
225
226
227enum {
228 TARGET_SIGINT = 2,
229 TARGET_SIGTRAP = 5
230};
231
232static int gdb_signal_table[] = {
233 -1,
234 -1,
235 TARGET_SIGINT,
236 -1,
237 -1,
238 TARGET_SIGTRAP
239};
240#endif
241
242#ifdef CONFIG_USER_ONLY
243static int target_signal_to_gdb (int sig)
244{
245 int i;
246 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
247 if (gdb_signal_table[i] == sig)
248 return i;
249 return GDB_SIGNAL_UNKNOWN;
250}
251#endif
252
253static int gdb_signal_to_target (int sig)
254{
255 if (sig < ARRAY_SIZE (gdb_signal_table))
256 return gdb_signal_table[sig];
257 else
258 return -1;
259}
260
261
262
263typedef struct GDBRegisterState {
264 int base_reg;
265 int num_regs;
266 gdb_reg_cb get_reg;
267 gdb_reg_cb set_reg;
268 const char *xml;
269 struct GDBRegisterState *next;
270} GDBRegisterState;
271
272enum RSState {
273 RS_INACTIVE,
274 RS_IDLE,
275 RS_GETLINE,
276 RS_CHKSUM1,
277 RS_CHKSUM2,
278 RS_SYSCALL,
279};
280typedef struct GDBState {
281 CPUState *c_cpu;
282 CPUState *g_cpu;
283 CPUState *query_cpu;
284 enum RSState state;
285 char line_buf[MAX_PACKET_LENGTH];
286 int line_buf_index;
287 int line_csum;
288 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
289 int last_packet_len;
290 int signal;
291#ifdef CONFIG_USER_ONLY
292 int fd;
293 int running_state;
294#else
295 CharDriverState *chr;
296 CharDriverState *mon_chr;
297#endif
298} GDBState;
299
300
301
302
303static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
304
305static GDBState *gdbserver_state;
306
307
308
309
310static int gdb_has_xml;
311
312#ifdef CONFIG_USER_ONLY
313
314static int gdbserver_fd = -1;
315
316static int get_char(GDBState *s)
317{
318 uint8_t ch;
319 int ret;
320
321 for(;;) {
322 ret = qemu_recv(s->fd, &ch, 1, 0);
323 if (ret < 0) {
324 if (errno == ECONNRESET)
325 s->fd = -1;
326 if (errno != EINTR && errno != EAGAIN)
327 return -1;
328 } else if (ret == 0) {
329 close(s->fd);
330 s->fd = -1;
331 return -1;
332 } else {
333 break;
334 }
335 }
336 return ch;
337}
338#endif
339
340static gdb_syscall_complete_cb gdb_current_syscall_cb;
341
342static enum {
343 GDB_SYS_UNKNOWN,
344 GDB_SYS_ENABLED,
345 GDB_SYS_DISABLED,
346} gdb_syscall_mode;
347
348
349
350int use_gdb_syscalls(void)
351{
352 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
353 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
354 : GDB_SYS_DISABLED);
355 }
356 return gdb_syscall_mode == GDB_SYS_ENABLED;
357}
358
359
360static inline void gdb_continue(GDBState *s)
361{
362#ifdef CONFIG_USER_ONLY
363 s->running_state = 1;
364#else
365 vm_start();
366#endif
367}
368
369static void put_buffer(GDBState *s, const uint8_t *buf, int len)
370{
371#ifdef CONFIG_USER_ONLY
372 int ret;
373
374 while (len > 0) {
375 ret = send(s->fd, buf, len, 0);
376 if (ret < 0) {
377 if (errno != EINTR && errno != EAGAIN)
378 return;
379 } else {
380 buf += ret;
381 len -= ret;
382 }
383 }
384#else
385 qemu_chr_write(s->chr, buf, len);
386#endif
387}
388
389static inline int fromhex(int v)
390{
391 if (v >= '0' && v <= '9')
392 return v - '0';
393 else if (v >= 'A' && v <= 'F')
394 return v - 'A' + 10;
395 else if (v >= 'a' && v <= 'f')
396 return v - 'a' + 10;
397 else
398 return 0;
399}
400
401static inline int tohex(int v)
402{
403 if (v < 10)
404 return v + '0';
405 else
406 return v - 10 + 'a';
407}
408
409static void memtohex(char *buf, const uint8_t *mem, int len)
410{
411 int i, c;
412 char *q;
413 q = buf;
414 for(i = 0; i < len; i++) {
415 c = mem[i];
416 *q++ = tohex(c >> 4);
417 *q++ = tohex(c & 0xf);
418 }
419 *q = '\0';
420}
421
422static void hextomem(uint8_t *mem, const char *buf, int len)
423{
424 int i;
425
426 for(i = 0; i < len; i++) {
427 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
428 buf += 2;
429 }
430}
431
432
433static int put_packet_binary(GDBState *s, const char *buf, int len)
434{
435 int csum, i;
436 uint8_t *p;
437
438 for(;;) {
439 p = s->last_packet;
440 *(p++) = '$';
441 memcpy(p, buf, len);
442 p += len;
443 csum = 0;
444 for(i = 0; i < len; i++) {
445 csum += buf[i];
446 }
447 *(p++) = '#';
448 *(p++) = tohex((csum >> 4) & 0xf);
449 *(p++) = tohex((csum) & 0xf);
450
451 s->last_packet_len = p - s->last_packet;
452 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
453
454#ifdef CONFIG_USER_ONLY
455 i = get_char(s);
456 if (i < 0)
457 return -1;
458 if (i == '+')
459 break;
460#else
461 break;
462#endif
463 }
464 return 0;
465}
466
467
468static int put_packet(GDBState *s, const char *buf)
469{
470#ifdef DEBUG_GDB
471 printf("reply='%s'\n", buf);
472#endif
473
474 return put_packet_binary(s, buf, strlen(buf));
475}
476
477
478
479
480
481#define GET_REG8(val) do { \
482 stb_p(mem_buf, val); \
483 return 1; \
484 } while(0)
485#define GET_REG16(val) do { \
486 stw_p(mem_buf, val); \
487 return 2; \
488 } while(0)
489#define GET_REG32(val) do { \
490 stl_p(mem_buf, val); \
491 return 4; \
492 } while(0)
493#define GET_REG64(val) do { \
494 stq_p(mem_buf, val); \
495 return 8; \
496 } while(0)
497
498#if TARGET_LONG_BITS == 64
499#define GET_REGL(val) GET_REG64(val)
500#define ldtul_p(addr) ldq_p(addr)
501#else
502#define GET_REGL(val) GET_REG32(val)
503#define ldtul_p(addr) ldl_p(addr)
504#endif
505
506#if defined(TARGET_I386)
507
508#ifdef TARGET_X86_64
509static const int gpr_map[16] = {
510 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
511 8, 9, 10, 11, 12, 13, 14, 15
512};
513#else
514#define gpr_map gpr_map32
515#endif
516static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
517
518#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
519
520#define IDX_IP_REG CPU_NB_REGS
521#define IDX_FLAGS_REG (IDX_IP_REG + 1)
522#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
523#define IDX_FP_REGS (IDX_SEG_REGS + 6)
524#define IDX_XMM_REGS (IDX_FP_REGS + 16)
525#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
526
527static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
528{
529 if (n < CPU_NB_REGS) {
530 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
531 GET_REG64(env->regs[gpr_map[n]]);
532 } else if (n < CPU_NB_REGS32) {
533 GET_REG32(env->regs[gpr_map32[n]]);
534 }
535 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
536#ifdef USE_X86LDOUBLE
537
538 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
539#else
540 memset(mem_buf, 0, 10);
541#endif
542 return 10;
543 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
544 n -= IDX_XMM_REGS;
545 if (n < CPU_NB_REGS32 ||
546 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
547 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
548 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
549 return 16;
550 }
551 } else {
552 switch (n) {
553 case IDX_IP_REG:
554 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
555 GET_REG64(env->eip);
556 } else {
557 GET_REG32(env->eip);
558 }
559 case IDX_FLAGS_REG: GET_REG32(env->eflags);
560
561 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
562 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
563 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
564 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
565 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
566 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
567
568 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
569 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
570 (env->fpstt & 0x7) << 11);
571 case IDX_FP_REGS + 10: GET_REG32(0);
572 case IDX_FP_REGS + 11: GET_REG32(0);
573 case IDX_FP_REGS + 12: GET_REG32(0);
574 case IDX_FP_REGS + 13: GET_REG32(0);
575 case IDX_FP_REGS + 14: GET_REG32(0);
576 case IDX_FP_REGS + 15: GET_REG32(0);
577
578 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
579 }
580 }
581 return 0;
582}
583
584static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
585{
586 uint16_t selector = ldl_p(mem_buf);
587
588 if (selector != env->segs[sreg].selector) {
589#if defined(CONFIG_USER_ONLY)
590 cpu_x86_load_seg(env, sreg, selector);
591#else
592 unsigned int limit, flags;
593 target_ulong base;
594
595 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
596 base = selector << 4;
597 limit = 0xffff;
598 flags = 0;
599 } else {
600 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
601 return 4;
602 }
603 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
604#endif
605 }
606 return 4;
607}
608
609static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
610{
611 uint32_t tmp;
612
613 if (n < CPU_NB_REGS) {
614 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
615 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
616 return sizeof(target_ulong);
617 } else if (n < CPU_NB_REGS32) {
618 n = gpr_map32[n];
619 env->regs[n] &= ~0xffffffffUL;
620 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
621 return 4;
622 }
623 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
624#ifdef USE_X86LDOUBLE
625
626 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
627#endif
628 return 10;
629 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
630 n -= IDX_XMM_REGS;
631 if (n < CPU_NB_REGS32 ||
632 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
633 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
634 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
635 return 16;
636 }
637 } else {
638 switch (n) {
639 case IDX_IP_REG:
640 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
641 env->eip = ldq_p(mem_buf);
642 return 8;
643 } else {
644 env->eip &= ~0xffffffffUL;
645 env->eip |= (uint32_t)ldl_p(mem_buf);
646 return 4;
647 }
648 case IDX_FLAGS_REG:
649 env->eflags = ldl_p(mem_buf);
650 return 4;
651
652 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
653 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
654 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
655 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
656 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
657 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
658
659 case IDX_FP_REGS + 8:
660 env->fpuc = ldl_p(mem_buf);
661 return 4;
662 case IDX_FP_REGS + 9:
663 tmp = ldl_p(mem_buf);
664 env->fpstt = (tmp >> 11) & 7;
665 env->fpus = tmp & ~0x3800;
666 return 4;
667 case IDX_FP_REGS + 10: return 4;
668 case IDX_FP_REGS + 11: return 4;
669 case IDX_FP_REGS + 12: return 4;
670 case IDX_FP_REGS + 13: return 4;
671 case IDX_FP_REGS + 14: return 4;
672 case IDX_FP_REGS + 15: return 4;
673
674 case IDX_MXCSR_REG:
675 env->mxcsr = ldl_p(mem_buf);
676 return 4;
677 }
678 }
679
680 return 0;
681}
682
683#elif defined (TARGET_PPC)
684
685
686
687
688
689
690#define NUM_CORE_REGS 71
691#if defined (TARGET_PPC64)
692#define GDB_CORE_XML "power64-core.xml"
693#else
694#define GDB_CORE_XML "power-core.xml"
695#endif
696
697static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
698{
699 if (n < 32) {
700
701 GET_REGL(env->gpr[n]);
702 } else if (n < 64) {
703
704 if (gdb_has_xml)
705 return 0;
706 stfq_p(mem_buf, env->fpr[n-32]);
707 return 8;
708 } else {
709 switch (n) {
710 case 64: GET_REGL(env->nip);
711 case 65: GET_REGL(env->msr);
712 case 66:
713 {
714 uint32_t cr = 0;
715 int i;
716 for (i = 0; i < 8; i++)
717 cr |= env->crf[i] << (32 - ((i + 1) * 4));
718 GET_REG32(cr);
719 }
720 case 67: GET_REGL(env->lr);
721 case 68: GET_REGL(env->ctr);
722 case 69: GET_REGL(env->xer);
723 case 70:
724 {
725 if (gdb_has_xml)
726 return 0;
727 GET_REG32(0);
728 }
729 }
730 }
731 return 0;
732}
733
734static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
735{
736 if (n < 32) {
737
738 env->gpr[n] = ldtul_p(mem_buf);
739 return sizeof(target_ulong);
740 } else if (n < 64) {
741
742 if (gdb_has_xml)
743 return 0;
744 env->fpr[n-32] = ldfq_p(mem_buf);
745 return 8;
746 } else {
747 switch (n) {
748 case 64:
749 env->nip = ldtul_p(mem_buf);
750 return sizeof(target_ulong);
751 case 65:
752 ppc_store_msr(env, ldtul_p(mem_buf));
753 return sizeof(target_ulong);
754 case 66:
755 {
756 uint32_t cr = ldl_p(mem_buf);
757 int i;
758 for (i = 0; i < 8; i++)
759 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
760 return 4;
761 }
762 case 67:
763 env->lr = ldtul_p(mem_buf);
764 return sizeof(target_ulong);
765 case 68:
766 env->ctr = ldtul_p(mem_buf);
767 return sizeof(target_ulong);
768 case 69:
769 env->xer = ldtul_p(mem_buf);
770 return sizeof(target_ulong);
771 case 70:
772
773 if (gdb_has_xml)
774 return 0;
775 return 4;
776 }
777 }
778 return 0;
779}
780
781#elif defined (TARGET_SPARC)
782
783#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
784#define NUM_CORE_REGS 86
785#else
786#define NUM_CORE_REGS 72
787#endif
788
789#ifdef TARGET_ABI32
790#define GET_REGA(val) GET_REG32(val)
791#else
792#define GET_REGA(val) GET_REGL(val)
793#endif
794
795static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
796{
797 if (n < 8) {
798
799 GET_REGA(env->gregs[n]);
800 }
801 if (n < 32) {
802
803 GET_REGA(env->regwptr[n - 8]);
804 }
805#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
806 if (n < 64) {
807
808 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
809 }
810
811 switch (n) {
812 case 64: GET_REGA(env->y);
813 case 65: GET_REGA(cpu_get_psr(env));
814 case 66: GET_REGA(env->wim);
815 case 67: GET_REGA(env->tbr);
816 case 68: GET_REGA(env->pc);
817 case 69: GET_REGA(env->npc);
818 case 70: GET_REGA(env->fsr);
819 case 71: GET_REGA(0);
820 default: GET_REGA(0);
821 }
822#else
823 if (n < 64) {
824
825 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
826 }
827 if (n < 80) {
828
829 uint64_t val;
830
831 val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
832 val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
833 GET_REG64(val);
834 }
835 switch (n) {
836 case 80: GET_REGL(env->pc);
837 case 81: GET_REGL(env->npc);
838 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
839 ((env->asi & 0xff) << 24) |
840 ((env->pstate & 0xfff) << 8) |
841 cpu_get_cwp64(env));
842 case 83: GET_REGL(env->fsr);
843 case 84: GET_REGL(env->fprs);
844 case 85: GET_REGL(env->y);
845 }
846#endif
847 return 0;
848}
849
850static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
851{
852#if defined(TARGET_ABI32)
853 abi_ulong tmp;
854
855 tmp = ldl_p(mem_buf);
856#else
857 target_ulong tmp;
858
859 tmp = ldtul_p(mem_buf);
860#endif
861
862 if (n < 8) {
863
864 env->gregs[n] = tmp;
865 } else if (n < 32) {
866
867 env->regwptr[n - 8] = tmp;
868 }
869#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
870 else if (n < 64) {
871
872 *((uint32_t *)&env->fpr[n - 32]) = tmp;
873 } else {
874
875 switch (n) {
876 case 64: env->y = tmp; break;
877 case 65: cpu_put_psr(env, tmp); break;
878 case 66: env->wim = tmp; break;
879 case 67: env->tbr = tmp; break;
880 case 68: env->pc = tmp; break;
881 case 69: env->npc = tmp; break;
882 case 70: env->fsr = tmp; break;
883 default: return 0;
884 }
885 }
886 return 4;
887#else
888 else if (n < 64) {
889
890 env->fpr[n] = ldfl_p(mem_buf);
891 return 4;
892 } else if (n < 80) {
893
894 *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
895 *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
896 } else {
897 switch (n) {
898 case 80: env->pc = tmp; break;
899 case 81: env->npc = tmp; break;
900 case 82:
901 cpu_put_ccr(env, tmp >> 32);
902 env->asi = (tmp >> 24) & 0xff;
903 env->pstate = (tmp >> 8) & 0xfff;
904 cpu_put_cwp64(env, tmp & 0xff);
905 break;
906 case 83: env->fsr = tmp; break;
907 case 84: env->fprs = tmp; break;
908 case 85: env->y = tmp; break;
909 default: return 0;
910 }
911 }
912 return 8;
913#endif
914}
915#elif defined (TARGET_ARM)
916
917
918
919
920
921
922#define NUM_CORE_REGS 26
923#define GDB_CORE_XML "arm-core.xml"
924
925static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
926{
927 if (n < 16) {
928
929 GET_REG32(env->regs[n]);
930 }
931 if (n < 24) {
932
933 if (gdb_has_xml)
934 return 0;
935 memset(mem_buf, 0, 12);
936 return 12;
937 }
938 switch (n) {
939 case 24:
940
941 if (gdb_has_xml)
942 return 0;
943 GET_REG32(0);
944 case 25:
945
946 GET_REG32(cpsr_read(env));
947 }
948
949 return 0;
950}
951
952static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
953{
954 uint32_t tmp;
955
956 tmp = ldl_p(mem_buf);
957
958
959
960 if (n == 15)
961 tmp &= ~1;
962
963 if (n < 16) {
964
965 env->regs[n] = tmp;
966 return 4;
967 }
968 if (n < 24) {
969
970 if (gdb_has_xml)
971 return 0;
972 return 12;
973 }
974 switch (n) {
975 case 24:
976
977 if (gdb_has_xml)
978 return 0;
979 return 4;
980 case 25:
981
982 cpsr_write (env, tmp, 0xffffffff);
983 return 4;
984 }
985
986 return 0;
987}
988
989#elif defined (TARGET_M68K)
990
991#define NUM_CORE_REGS 18
992
993#define GDB_CORE_XML "cf-core.xml"
994
995static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
996{
997 if (n < 8) {
998
999 GET_REG32(env->dregs[n]);
1000 } else if (n < 16) {
1001
1002 GET_REG32(env->aregs[n - 8]);
1003 } else {
1004 switch (n) {
1005 case 16: GET_REG32(env->sr);
1006 case 17: GET_REG32(env->pc);
1007 }
1008 }
1009
1010
1011 return 0;
1012}
1013
1014static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1015{
1016 uint32_t tmp;
1017
1018 tmp = ldl_p(mem_buf);
1019
1020 if (n < 8) {
1021
1022 env->dregs[n] = tmp;
1023 } else if (n < 16) {
1024
1025 env->aregs[n - 8] = tmp;
1026 } else {
1027 switch (n) {
1028 case 16: env->sr = tmp; break;
1029 case 17: env->pc = tmp; break;
1030 default: return 0;
1031 }
1032 }
1033 return 4;
1034}
1035#elif defined (TARGET_MIPS)
1036
1037#define NUM_CORE_REGS 73
1038
1039static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1040{
1041 if (n < 32) {
1042 GET_REGL(env->active_tc.gpr[n]);
1043 }
1044 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1045 if (n >= 38 && n < 70) {
1046 if (env->CP0_Status & (1 << CP0St_FR))
1047 GET_REGL(env->active_fpu.fpr[n - 38].d);
1048 else
1049 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1050 }
1051 switch (n) {
1052 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1053 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1054 }
1055 }
1056 switch (n) {
1057 case 32: GET_REGL((int32_t)env->CP0_Status);
1058 case 33: GET_REGL(env->active_tc.LO[0]);
1059 case 34: GET_REGL(env->active_tc.HI[0]);
1060 case 35: GET_REGL(env->CP0_BadVAddr);
1061 case 36: GET_REGL((int32_t)env->CP0_Cause);
1062 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1063 case 72: GET_REGL(0);
1064 case 89: GET_REGL((int32_t)env->CP0_PRid);
1065 }
1066 if (n >= 73 && n <= 88) {
1067
1068 GET_REGL(0);
1069 }
1070
1071 return 0;
1072}
1073
1074
1075static unsigned int ieee_rm[] =
1076 {
1077 float_round_nearest_even,
1078 float_round_to_zero,
1079 float_round_up,
1080 float_round_down
1081 };
1082#define RESTORE_ROUNDING_MODE \
1083 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1084
1085static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1086{
1087 target_ulong tmp;
1088
1089 tmp = ldtul_p(mem_buf);
1090
1091 if (n < 32) {
1092 env->active_tc.gpr[n] = tmp;
1093 return sizeof(target_ulong);
1094 }
1095 if (env->CP0_Config1 & (1 << CP0C1_FP)
1096 && n >= 38 && n < 73) {
1097 if (n < 70) {
1098 if (env->CP0_Status & (1 << CP0St_FR))
1099 env->active_fpu.fpr[n - 38].d = tmp;
1100 else
1101 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1102 }
1103 switch (n) {
1104 case 70:
1105 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1106
1107 RESTORE_ROUNDING_MODE;
1108 break;
1109 case 71: env->active_fpu.fcr0 = tmp; break;
1110 }
1111 return sizeof(target_ulong);
1112 }
1113 switch (n) {
1114 case 32: env->CP0_Status = tmp; break;
1115 case 33: env->active_tc.LO[0] = tmp; break;
1116 case 34: env->active_tc.HI[0] = tmp; break;
1117 case 35: env->CP0_BadVAddr = tmp; break;
1118 case 36: env->CP0_Cause = tmp; break;
1119 case 37:
1120 env->active_tc.PC = tmp & ~(target_ulong)1;
1121 if (tmp & 1) {
1122 env->hflags |= MIPS_HFLAG_M16;
1123 } else {
1124 env->hflags &= ~(MIPS_HFLAG_M16);
1125 }
1126 break;
1127 case 72: break;
1128 default:
1129 if (n > 89)
1130 return 0;
1131
1132 break;
1133 }
1134
1135 return sizeof(target_ulong);
1136}
1137#elif defined (TARGET_SH4)
1138
1139
1140
1141
1142#define NUM_CORE_REGS 59
1143
1144static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1145{
1146 if (n < 8) {
1147 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1148 GET_REGL(env->gregs[n + 16]);
1149 } else {
1150 GET_REGL(env->gregs[n]);
1151 }
1152 } else if (n < 16) {
1153 GET_REGL(env->gregs[n]);
1154 } else if (n >= 25 && n < 41) {
1155 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1156 } else if (n >= 43 && n < 51) {
1157 GET_REGL(env->gregs[n - 43]);
1158 } else if (n >= 51 && n < 59) {
1159 GET_REGL(env->gregs[n - (51 - 16)]);
1160 }
1161 switch (n) {
1162 case 16: GET_REGL(env->pc);
1163 case 17: GET_REGL(env->pr);
1164 case 18: GET_REGL(env->gbr);
1165 case 19: GET_REGL(env->vbr);
1166 case 20: GET_REGL(env->mach);
1167 case 21: GET_REGL(env->macl);
1168 case 22: GET_REGL(env->sr);
1169 case 23: GET_REGL(env->fpul);
1170 case 24: GET_REGL(env->fpscr);
1171 case 41: GET_REGL(env->ssr);
1172 case 42: GET_REGL(env->spc);
1173 }
1174
1175 return 0;
1176}
1177
1178static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1179{
1180 uint32_t tmp;
1181
1182 tmp = ldl_p(mem_buf);
1183
1184 if (n < 8) {
1185 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1186 env->gregs[n + 16] = tmp;
1187 } else {
1188 env->gregs[n] = tmp;
1189 }
1190 return 4;
1191 } else if (n < 16) {
1192 env->gregs[n] = tmp;
1193 return 4;
1194 } else if (n >= 25 && n < 41) {
1195 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1196 return 4;
1197 } else if (n >= 43 && n < 51) {
1198 env->gregs[n - 43] = tmp;
1199 return 4;
1200 } else if (n >= 51 && n < 59) {
1201 env->gregs[n - (51 - 16)] = tmp;
1202 return 4;
1203 }
1204 switch (n) {
1205 case 16: env->pc = tmp; break;
1206 case 17: env->pr = tmp; break;
1207 case 18: env->gbr = tmp; break;
1208 case 19: env->vbr = tmp; break;
1209 case 20: env->mach = tmp; break;
1210 case 21: env->macl = tmp; break;
1211 case 22: env->sr = tmp; break;
1212 case 23: env->fpul = tmp; break;
1213 case 24: env->fpscr = tmp; break;
1214 case 41: env->ssr = tmp; break;
1215 case 42: env->spc = tmp; break;
1216 default: return 0;
1217 }
1218
1219 return 4;
1220}
1221#elif defined (TARGET_MICROBLAZE)
1222
1223#define NUM_CORE_REGS (32 + 5)
1224
1225static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1226{
1227 if (n < 32) {
1228 GET_REG32(env->regs[n]);
1229 } else {
1230 GET_REG32(env->sregs[n - 32]);
1231 }
1232 return 0;
1233}
1234
1235static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1236{
1237 uint32_t tmp;
1238
1239 if (n > NUM_CORE_REGS)
1240 return 0;
1241
1242 tmp = ldl_p(mem_buf);
1243
1244 if (n < 32) {
1245 env->regs[n] = tmp;
1246 } else {
1247 env->sregs[n - 32] = tmp;
1248 }
1249 return 4;
1250}
1251#elif defined (TARGET_CRIS)
1252
1253#define NUM_CORE_REGS 49
1254
1255static int
1256read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
1257{
1258 if (n < 15) {
1259 GET_REG32(env->regs[n]);
1260 }
1261
1262 if (n == 15) {
1263 GET_REG32(env->pc);
1264 }
1265
1266 if (n < 32) {
1267 switch (n) {
1268 case 16:
1269 GET_REG8(env->pregs[n - 16]);
1270 break;
1271 case 17:
1272 GET_REG8(env->pregs[n - 16]);
1273 break;
1274 case 20:
1275 case 21:
1276 GET_REG16(env->pregs[n - 16]);
1277 break;
1278 default:
1279 if (n >= 23) {
1280 GET_REG32(env->pregs[n - 16]);
1281 }
1282 break;
1283 }
1284 }
1285 return 0;
1286}
1287
1288static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1289{
1290 uint8_t srs;
1291
1292 if (env->pregs[PR_VR] < 32)
1293 return read_register_crisv10(env, mem_buf, n);
1294
1295 srs = env->pregs[PR_SRS];
1296 if (n < 16) {
1297 GET_REG32(env->regs[n]);
1298 }
1299
1300 if (n >= 21 && n < 32) {
1301 GET_REG32(env->pregs[n - 16]);
1302 }
1303 if (n >= 33 && n < 49) {
1304 GET_REG32(env->sregs[srs][n - 33]);
1305 }
1306 switch (n) {
1307 case 16: GET_REG8(env->pregs[0]);
1308 case 17: GET_REG8(env->pregs[1]);
1309 case 18: GET_REG32(env->pregs[2]);
1310 case 19: GET_REG8(srs);
1311 case 20: GET_REG16(env->pregs[4]);
1312 case 32: GET_REG32(env->pc);
1313 }
1314
1315 return 0;
1316}
1317
1318static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1319{
1320 uint32_t tmp;
1321
1322 if (n > 49)
1323 return 0;
1324
1325 tmp = ldl_p(mem_buf);
1326
1327 if (n < 16) {
1328 env->regs[n] = tmp;
1329 }
1330
1331 if (n >= 21 && n < 32) {
1332 env->pregs[n - 16] = tmp;
1333 }
1334
1335
1336 switch (n) {
1337 case 16: return 1;
1338 case 17: return 1;
1339 case 18: env->pregs[PR_PID] = tmp; break;
1340 case 19: return 1;
1341 case 20: return 2;
1342 case 32: env->pc = tmp; break;
1343 }
1344
1345 return 4;
1346}
1347#elif defined (TARGET_ALPHA)
1348
1349#define NUM_CORE_REGS 67
1350
1351static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1352{
1353 uint64_t val;
1354 CPU_DoubleU d;
1355
1356 switch (n) {
1357 case 0 ... 30:
1358 val = env->ir[n];
1359 break;
1360 case 32 ... 62:
1361 d.d = env->fir[n - 32];
1362 val = d.ll;
1363 break;
1364 case 63:
1365 val = cpu_alpha_load_fpcr(env);
1366 break;
1367 case 64:
1368 val = env->pc;
1369 break;
1370 case 66:
1371 val = env->unique;
1372 break;
1373 case 31:
1374 case 65:
1375
1376
1377 val = 0;
1378 break;
1379 default:
1380 return 0;
1381 }
1382 GET_REGL(val);
1383}
1384
1385static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1386{
1387 target_ulong tmp = ldtul_p(mem_buf);
1388 CPU_DoubleU d;
1389
1390 switch (n) {
1391 case 0 ... 30:
1392 env->ir[n] = tmp;
1393 break;
1394 case 32 ... 62:
1395 d.ll = tmp;
1396 env->fir[n - 32] = d.d;
1397 break;
1398 case 63:
1399 cpu_alpha_store_fpcr(env, tmp);
1400 break;
1401 case 64:
1402 env->pc = tmp;
1403 break;
1404 case 66:
1405 env->unique = tmp;
1406 break;
1407 case 31:
1408 case 65:
1409
1410
1411 break;
1412 default:
1413 return 0;
1414 }
1415 return 8;
1416}
1417#elif defined (TARGET_S390X)
1418
1419#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1420
1421static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1422{
1423 switch (n) {
1424 case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1425 case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1426 case S390_R0_REGNUM ... S390_R15_REGNUM:
1427 GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1428 case S390_A0_REGNUM ... S390_A15_REGNUM:
1429 GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1430 case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1431 case S390_F0_REGNUM ... S390_F15_REGNUM:
1432
1433 break;
1434 case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1435 case S390_CC_REGNUM:
1436 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
1437 env->cc_vr);
1438 GET_REG32(env->cc_op);
1439 break;
1440 }
1441
1442 return 0;
1443}
1444
1445static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1446{
1447 target_ulong tmpl;
1448 uint32_t tmp32;
1449 int r = 8;
1450 tmpl = ldtul_p(mem_buf);
1451 tmp32 = ldl_p(mem_buf);
1452
1453 switch (n) {
1454 case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1455 case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1456 case S390_R0_REGNUM ... S390_R15_REGNUM:
1457 env->regs[n-S390_R0_REGNUM] = tmpl; break;
1458 case S390_A0_REGNUM ... S390_A15_REGNUM:
1459 env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1460 case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1461 case S390_F0_REGNUM ... S390_F15_REGNUM:
1462
1463 break;
1464 case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1465 case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
1466 }
1467
1468 return r;
1469}
1470#elif defined (TARGET_LM32)
1471
1472#include "hw/lm32_pic.h"
1473#define NUM_CORE_REGS (32 + 7)
1474
1475static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1476{
1477 if (n < 32) {
1478 GET_REG32(env->regs[n]);
1479 } else {
1480 switch (n) {
1481 case 32:
1482 GET_REG32(env->pc);
1483 break;
1484
1485 case 33:
1486 GET_REG32(0);
1487 break;
1488 case 34:
1489 GET_REG32(env->eba);
1490 break;
1491 case 35:
1492 GET_REG32(env->deba);
1493 break;
1494 case 36:
1495 GET_REG32(env->ie);
1496 break;
1497 case 37:
1498 GET_REG32(lm32_pic_get_im(env->pic_state));
1499 break;
1500 case 38:
1501 GET_REG32(lm32_pic_get_ip(env->pic_state));
1502 break;
1503 }
1504 }
1505 return 0;
1506}
1507
1508static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1509{
1510 uint32_t tmp;
1511
1512 if (n > NUM_CORE_REGS) {
1513 return 0;
1514 }
1515
1516 tmp = ldl_p(mem_buf);
1517
1518 if (n < 32) {
1519 env->regs[n] = tmp;
1520 } else {
1521 switch (n) {
1522 case 32:
1523 env->pc = tmp;
1524 break;
1525 case 34:
1526 env->eba = tmp;
1527 break;
1528 case 35:
1529 env->deba = tmp;
1530 break;
1531 case 36:
1532 env->ie = tmp;
1533 break;
1534 case 37:
1535 lm32_pic_set_im(env->pic_state, tmp);
1536 break;
1537 case 38:
1538 lm32_pic_set_ip(env->pic_state, tmp);
1539 break;
1540 }
1541 }
1542 return 4;
1543}
1544#else
1545
1546#define NUM_CORE_REGS 0
1547
1548static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1549{
1550 return 0;
1551}
1552
1553static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1554{
1555 return 0;
1556}
1557
1558#endif
1559
1560static int num_g_regs = NUM_CORE_REGS;
1561
1562#ifdef GDB_CORE_XML
1563
1564static int memtox(char *buf, const char *mem, int len)
1565{
1566 char *p = buf;
1567 char c;
1568
1569 while (len--) {
1570 c = *(mem++);
1571 switch (c) {
1572 case '#': case '$': case '*': case '}':
1573 *(p++) = '}';
1574 *(p++) = c ^ 0x20;
1575 break;
1576 default:
1577 *(p++) = c;
1578 break;
1579 }
1580 }
1581 return p - buf;
1582}
1583
1584static const char *get_feature_xml(const char *p, const char **newp)
1585{
1586 size_t len;
1587 int i;
1588 const char *name;
1589 static char target_xml[1024];
1590
1591 len = 0;
1592 while (p[len] && p[len] != ':')
1593 len++;
1594 *newp = p + len;
1595
1596 name = NULL;
1597 if (strncmp(p, "target.xml", len) == 0) {
1598
1599 if (!target_xml[0]) {
1600 GDBRegisterState *r;
1601
1602 snprintf(target_xml, sizeof(target_xml),
1603 "<?xml version=\"1.0\"?>"
1604 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1605 "<target>"
1606 "<xi:include href=\"%s\"/>",
1607 GDB_CORE_XML);
1608
1609 for (r = first_cpu->gdb_regs; r; r = r->next) {
1610 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1611 pstrcat(target_xml, sizeof(target_xml), r->xml);
1612 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1613 }
1614 pstrcat(target_xml, sizeof(target_xml), "</target>");
1615 }
1616 return target_xml;
1617 }
1618 for (i = 0; ; i++) {
1619 name = xml_builtin[i][0];
1620 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1621 break;
1622 }
1623 return name ? xml_builtin[i][1] : NULL;
1624}
1625#endif
1626
1627static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1628{
1629 GDBRegisterState *r;
1630
1631 if (reg < NUM_CORE_REGS)
1632 return cpu_gdb_read_register(env, mem_buf, reg);
1633
1634 for (r = env->gdb_regs; r; r = r->next) {
1635 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1636 return r->get_reg(env, mem_buf, reg - r->base_reg);
1637 }
1638 }
1639 return 0;
1640}
1641
1642static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1643{
1644 GDBRegisterState *r;
1645
1646 if (reg < NUM_CORE_REGS)
1647 return cpu_gdb_write_register(env, mem_buf, reg);
1648
1649 for (r = env->gdb_regs; r; r = r->next) {
1650 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1651 return r->set_reg(env, mem_buf, reg - r->base_reg);
1652 }
1653 }
1654 return 0;
1655}
1656
1657
1658
1659
1660
1661
1662
1663void gdb_register_coprocessor(CPUState * env,
1664 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1665 int num_regs, const char *xml, int g_pos)
1666{
1667 GDBRegisterState *s;
1668 GDBRegisterState **p;
1669 static int last_reg = NUM_CORE_REGS;
1670
1671 s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1672 s->base_reg = last_reg;
1673 s->num_regs = num_regs;
1674 s->get_reg = get_reg;
1675 s->set_reg = set_reg;
1676 s->xml = xml;
1677 p = &env->gdb_regs;
1678 while (*p) {
1679
1680 if (strcmp((*p)->xml, xml) == 0)
1681 return;
1682 p = &(*p)->next;
1683 }
1684
1685 last_reg += num_regs;
1686 *p = s;
1687 if (g_pos) {
1688 if (g_pos != s->base_reg) {
1689 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1690 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1691 } else {
1692 num_g_regs = last_reg;
1693 }
1694 }
1695}
1696
1697#ifndef CONFIG_USER_ONLY
1698static const int xlat_gdb_type[] = {
1699 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1700 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1701 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1702};
1703#endif
1704
1705static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1706{
1707 CPUState *env;
1708 int err = 0;
1709
1710 if (kvm_enabled())
1711 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1712
1713 switch (type) {
1714 case GDB_BREAKPOINT_SW:
1715 case GDB_BREAKPOINT_HW:
1716 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1717 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1718 if (err)
1719 break;
1720 }
1721 return err;
1722#ifndef CONFIG_USER_ONLY
1723 case GDB_WATCHPOINT_WRITE:
1724 case GDB_WATCHPOINT_READ:
1725 case GDB_WATCHPOINT_ACCESS:
1726 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1727 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1728 NULL);
1729 if (err)
1730 break;
1731 }
1732 return err;
1733#endif
1734 default:
1735 return -ENOSYS;
1736 }
1737}
1738
1739static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1740{
1741 CPUState *env;
1742 int err = 0;
1743
1744 if (kvm_enabled())
1745 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1746
1747 switch (type) {
1748 case GDB_BREAKPOINT_SW:
1749 case GDB_BREAKPOINT_HW:
1750 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1751 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1752 if (err)
1753 break;
1754 }
1755 return err;
1756#ifndef CONFIG_USER_ONLY
1757 case GDB_WATCHPOINT_WRITE:
1758 case GDB_WATCHPOINT_READ:
1759 case GDB_WATCHPOINT_ACCESS:
1760 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1761 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1762 if (err)
1763 break;
1764 }
1765 return err;
1766#endif
1767 default:
1768 return -ENOSYS;
1769 }
1770}
1771
1772static void gdb_breakpoint_remove_all(void)
1773{
1774 CPUState *env;
1775
1776 if (kvm_enabled()) {
1777 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1778 return;
1779 }
1780
1781 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1782 cpu_breakpoint_remove_all(env, BP_GDB);
1783#ifndef CONFIG_USER_ONLY
1784 cpu_watchpoint_remove_all(env, BP_GDB);
1785#endif
1786 }
1787}
1788
1789static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1790{
1791#if defined(TARGET_I386)
1792 cpu_synchronize_state(s->c_cpu);
1793 s->c_cpu->eip = pc;
1794#elif defined (TARGET_PPC)
1795 s->c_cpu->nip = pc;
1796#elif defined (TARGET_SPARC)
1797 s->c_cpu->pc = pc;
1798 s->c_cpu->npc = pc + 4;
1799#elif defined (TARGET_ARM)
1800 s->c_cpu->regs[15] = pc;
1801#elif defined (TARGET_SH4)
1802 s->c_cpu->pc = pc;
1803#elif defined (TARGET_MIPS)
1804 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1805 if (pc & 1) {
1806 s->c_cpu->hflags |= MIPS_HFLAG_M16;
1807 } else {
1808 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1809 }
1810#elif defined (TARGET_MICROBLAZE)
1811 s->c_cpu->sregs[SR_PC] = pc;
1812#elif defined (TARGET_CRIS)
1813 s->c_cpu->pc = pc;
1814#elif defined (TARGET_ALPHA)
1815 s->c_cpu->pc = pc;
1816#elif defined (TARGET_S390X)
1817 cpu_synchronize_state(s->c_cpu);
1818 s->c_cpu->psw.addr = pc;
1819#elif defined (TARGET_LM32)
1820 s->c_cpu->pc = pc;
1821#endif
1822}
1823
1824static inline int gdb_id(CPUState *env)
1825{
1826#if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1827 return env->host_tid;
1828#else
1829 return env->cpu_index + 1;
1830#endif
1831}
1832
1833static CPUState *find_cpu(uint32_t thread_id)
1834{
1835 CPUState *env;
1836
1837 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1838 if (gdb_id(env) == thread_id) {
1839 return env;
1840 }
1841 }
1842
1843 return NULL;
1844}
1845
1846static int gdb_handle_packet(GDBState *s, const char *line_buf)
1847{
1848 CPUState *env;
1849 const char *p;
1850 uint32_t thread;
1851 int ch, reg_size, type, res;
1852 char buf[MAX_PACKET_LENGTH];
1853 uint8_t mem_buf[MAX_PACKET_LENGTH];
1854 uint8_t *registers;
1855 target_ulong addr, len;
1856
1857#ifdef DEBUG_GDB
1858 printf("command='%s'\n", line_buf);
1859#endif
1860 p = line_buf;
1861 ch = *p++;
1862 switch(ch) {
1863 case '?':
1864
1865 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1866 gdb_id(s->c_cpu));
1867 put_packet(s, buf);
1868
1869
1870
1871
1872 gdb_breakpoint_remove_all();
1873 break;
1874 case 'c':
1875 if (*p != '\0') {
1876 addr = strtoull(p, (char **)&p, 16);
1877 gdb_set_cpu_pc(s, addr);
1878 }
1879 s->signal = 0;
1880 gdb_continue(s);
1881 return RS_IDLE;
1882 case 'C':
1883 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1884 if (s->signal == -1)
1885 s->signal = 0;
1886 gdb_continue(s);
1887 return RS_IDLE;
1888 case 'v':
1889 if (strncmp(p, "Cont", 4) == 0) {
1890 int res_signal, res_thread;
1891
1892 p += 4;
1893 if (*p == '?') {
1894 put_packet(s, "vCont;c;C;s;S");
1895 break;
1896 }
1897 res = 0;
1898 res_signal = 0;
1899 res_thread = 0;
1900 while (*p) {
1901 int action, signal;
1902
1903 if (*p++ != ';') {
1904 res = 0;
1905 break;
1906 }
1907 action = *p++;
1908 signal = 0;
1909 if (action == 'C' || action == 'S') {
1910 signal = strtoul(p, (char **)&p, 16);
1911 } else if (action != 'c' && action != 's') {
1912 res = 0;
1913 break;
1914 }
1915 thread = 0;
1916 if (*p == ':') {
1917 thread = strtoull(p+1, (char **)&p, 16);
1918 }
1919 action = tolower(action);
1920 if (res == 0 || (res == 'c' && action == 's')) {
1921 res = action;
1922 res_signal = signal;
1923 res_thread = thread;
1924 }
1925 }
1926 if (res) {
1927 if (res_thread != -1 && res_thread != 0) {
1928 env = find_cpu(res_thread);
1929 if (env == NULL) {
1930 put_packet(s, "E22");
1931 break;
1932 }
1933 s->c_cpu = env;
1934 }
1935 if (res == 's') {
1936 cpu_single_step(s->c_cpu, sstep_flags);
1937 }
1938 s->signal = res_signal;
1939 gdb_continue(s);
1940 return RS_IDLE;
1941 }
1942 break;
1943 } else {
1944 goto unknown_command;
1945 }
1946 case 'k':
1947
1948 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1949 exit(0);
1950 case 'D':
1951
1952 gdb_breakpoint_remove_all();
1953 gdb_syscall_mode = GDB_SYS_DISABLED;
1954 gdb_continue(s);
1955 put_packet(s, "OK");
1956 break;
1957 case 's':
1958 if (*p != '\0') {
1959 addr = strtoull(p, (char **)&p, 16);
1960 gdb_set_cpu_pc(s, addr);
1961 }
1962 cpu_single_step(s->c_cpu, sstep_flags);
1963 gdb_continue(s);
1964 return RS_IDLE;
1965 case 'F':
1966 {
1967 target_ulong ret;
1968 target_ulong err;
1969
1970 ret = strtoull(p, (char **)&p, 16);
1971 if (*p == ',') {
1972 p++;
1973 err = strtoull(p, (char **)&p, 16);
1974 } else {
1975 err = 0;
1976 }
1977 if (*p == ',')
1978 p++;
1979 type = *p;
1980 if (gdb_current_syscall_cb)
1981 gdb_current_syscall_cb(s->c_cpu, ret, err);
1982 if (type == 'C') {
1983 put_packet(s, "T02");
1984 } else {
1985 gdb_continue(s);
1986 }
1987 }
1988 break;
1989 case 'g':
1990 cpu_synchronize_state(s->g_cpu);
1991 len = 0;
1992 for (addr = 0; addr < num_g_regs; addr++) {
1993 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1994 len += reg_size;
1995 }
1996 memtohex(buf, mem_buf, len);
1997 put_packet(s, buf);
1998 break;
1999 case 'G':
2000 cpu_synchronize_state(s->g_cpu);
2001 registers = mem_buf;
2002 len = strlen(p) / 2;
2003 hextomem((uint8_t *)registers, p, len);
2004 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2005 reg_size = gdb_write_register(s->g_cpu, registers, addr);
2006 len -= reg_size;
2007 registers += reg_size;
2008 }
2009 put_packet(s, "OK");
2010 break;
2011 case 'm':
2012 addr = strtoull(p, (char **)&p, 16);
2013 if (*p == ',')
2014 p++;
2015 len = strtoull(p, NULL, 16);
2016 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2017 put_packet (s, "E14");
2018 } else {
2019 memtohex(buf, mem_buf, len);
2020 put_packet(s, buf);
2021 }
2022 break;
2023 case 'M':
2024 addr = strtoull(p, (char **)&p, 16);
2025 if (*p == ',')
2026 p++;
2027 len = strtoull(p, (char **)&p, 16);
2028 if (*p == ':')
2029 p++;
2030 hextomem(mem_buf, p, len);
2031 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
2032 put_packet(s, "E14");
2033 else
2034 put_packet(s, "OK");
2035 break;
2036 case 'p':
2037
2038
2039
2040 if (!gdb_has_xml)
2041 goto unknown_command;
2042 addr = strtoull(p, (char **)&p, 16);
2043 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2044 if (reg_size) {
2045 memtohex(buf, mem_buf, reg_size);
2046 put_packet(s, buf);
2047 } else {
2048 put_packet(s, "E14");
2049 }
2050 break;
2051 case 'P':
2052 if (!gdb_has_xml)
2053 goto unknown_command;
2054 addr = strtoull(p, (char **)&p, 16);
2055 if (*p == '=')
2056 p++;
2057 reg_size = strlen(p) / 2;
2058 hextomem(mem_buf, p, reg_size);
2059 gdb_write_register(s->g_cpu, mem_buf, addr);
2060 put_packet(s, "OK");
2061 break;
2062 case 'Z':
2063 case 'z':
2064 type = strtoul(p, (char **)&p, 16);
2065 if (*p == ',')
2066 p++;
2067 addr = strtoull(p, (char **)&p, 16);
2068 if (*p == ',')
2069 p++;
2070 len = strtoull(p, (char **)&p, 16);
2071 if (ch == 'Z')
2072 res = gdb_breakpoint_insert(addr, len, type);
2073 else
2074 res = gdb_breakpoint_remove(addr, len, type);
2075 if (res >= 0)
2076 put_packet(s, "OK");
2077 else if (res == -ENOSYS)
2078 put_packet(s, "");
2079 else
2080 put_packet(s, "E22");
2081 break;
2082 case 'H':
2083 type = *p++;
2084 thread = strtoull(p, (char **)&p, 16);
2085 if (thread == -1 || thread == 0) {
2086 put_packet(s, "OK");
2087 break;
2088 }
2089 env = find_cpu(thread);
2090 if (env == NULL) {
2091 put_packet(s, "E22");
2092 break;
2093 }
2094 switch (type) {
2095 case 'c':
2096 s->c_cpu = env;
2097 put_packet(s, "OK");
2098 break;
2099 case 'g':
2100 s->g_cpu = env;
2101 put_packet(s, "OK");
2102 break;
2103 default:
2104 put_packet(s, "E22");
2105 break;
2106 }
2107 break;
2108 case 'T':
2109 thread = strtoull(p, (char **)&p, 16);
2110 env = find_cpu(thread);
2111
2112 if (env != NULL) {
2113 put_packet(s, "OK");
2114 } else {
2115 put_packet(s, "E22");
2116 }
2117 break;
2118 case 'q':
2119 case 'Q':
2120
2121 if (!strcmp(p,"qemu.sstepbits")) {
2122
2123 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2124 SSTEP_ENABLE,
2125 SSTEP_NOIRQ,
2126 SSTEP_NOTIMER);
2127 put_packet(s, buf);
2128 break;
2129 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2130
2131 p += 10;
2132 if (*p != '=') {
2133
2134 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2135 put_packet(s, buf);
2136 break;
2137 }
2138 p++;
2139 type = strtoul(p, (char **)&p, 16);
2140 sstep_flags = type;
2141 put_packet(s, "OK");
2142 break;
2143 } else if (strcmp(p,"C") == 0) {
2144
2145
2146 put_packet(s, "QC1");
2147 break;
2148 } else if (strcmp(p,"fThreadInfo") == 0) {
2149 s->query_cpu = first_cpu;
2150 goto report_cpuinfo;
2151 } else if (strcmp(p,"sThreadInfo") == 0) {
2152 report_cpuinfo:
2153 if (s->query_cpu) {
2154 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2155 put_packet(s, buf);
2156 s->query_cpu = s->query_cpu->next_cpu;
2157 } else
2158 put_packet(s, "l");
2159 break;
2160 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2161 thread = strtoull(p+16, (char **)&p, 16);
2162 env = find_cpu(thread);
2163 if (env != NULL) {
2164 cpu_synchronize_state(env);
2165 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2166 "CPU#%d [%s]", env->cpu_index,
2167 env->halted ? "halted " : "running");
2168 memtohex(buf, mem_buf, len);
2169 put_packet(s, buf);
2170 }
2171 break;
2172 }
2173#ifdef CONFIG_USER_ONLY
2174 else if (strncmp(p, "Offsets", 7) == 0) {
2175 TaskState *ts = s->c_cpu->opaque;
2176
2177 snprintf(buf, sizeof(buf),
2178 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2179 ";Bss=" TARGET_ABI_FMT_lx,
2180 ts->info->code_offset,
2181 ts->info->data_offset,
2182 ts->info->data_offset);
2183 put_packet(s, buf);
2184 break;
2185 }
2186#else
2187 else if (strncmp(p, "Rcmd,", 5) == 0) {
2188 int len = strlen(p + 5);
2189
2190 if ((len % 2) != 0) {
2191 put_packet(s, "E01");
2192 break;
2193 }
2194 hextomem(mem_buf, p + 5, len);
2195 len = len / 2;
2196 mem_buf[len++] = 0;
2197 qemu_chr_read(s->mon_chr, mem_buf, len);
2198 put_packet(s, "OK");
2199 break;
2200 }
2201#endif
2202 if (strncmp(p, "Supported", 9) == 0) {
2203 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2204#ifdef GDB_CORE_XML
2205 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2206#endif
2207 put_packet(s, buf);
2208 break;
2209 }
2210#ifdef GDB_CORE_XML
2211 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2212 const char *xml;
2213 target_ulong total_len;
2214
2215 gdb_has_xml = 1;
2216 p += 19;
2217 xml = get_feature_xml(p, &p);
2218 if (!xml) {
2219 snprintf(buf, sizeof(buf), "E00");
2220 put_packet(s, buf);
2221 break;
2222 }
2223
2224 if (*p == ':')
2225 p++;
2226 addr = strtoul(p, (char **)&p, 16);
2227 if (*p == ',')
2228 p++;
2229 len = strtoul(p, (char **)&p, 16);
2230
2231 total_len = strlen(xml);
2232 if (addr > total_len) {
2233 snprintf(buf, sizeof(buf), "E00");
2234 put_packet(s, buf);
2235 break;
2236 }
2237 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2238 len = (MAX_PACKET_LENGTH - 5) / 2;
2239 if (len < total_len - addr) {
2240 buf[0] = 'm';
2241 len = memtox(buf + 1, xml + addr, len);
2242 } else {
2243 buf[0] = 'l';
2244 len = memtox(buf + 1, xml + addr, total_len - addr);
2245 }
2246 put_packet_binary(s, buf, len + 1);
2247 break;
2248 }
2249#endif
2250
2251 goto unknown_command;
2252
2253 default:
2254 unknown_command:
2255
2256 buf[0] = '\0';
2257 put_packet(s, buf);
2258 break;
2259 }
2260 return RS_IDLE;
2261}
2262
2263void gdb_set_stop_cpu(CPUState *env)
2264{
2265 gdbserver_state->c_cpu = env;
2266 gdbserver_state->g_cpu = env;
2267}
2268
2269#ifndef CONFIG_USER_ONLY
2270static void gdb_vm_state_change(void *opaque, int running, int reason)
2271{
2272 GDBState *s = gdbserver_state;
2273 CPUState *env = s->c_cpu;
2274 char buf[256];
2275 const char *type;
2276 int ret;
2277
2278 if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
2279 return;
2280 }
2281 switch (reason) {
2282 case VMSTOP_DEBUG:
2283 if (env->watchpoint_hit) {
2284 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2285 case BP_MEM_READ:
2286 type = "r";
2287 break;
2288 case BP_MEM_ACCESS:
2289 type = "a";
2290 break;
2291 default:
2292 type = "";
2293 break;
2294 }
2295 snprintf(buf, sizeof(buf),
2296 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2297 GDB_SIGNAL_TRAP, gdb_id(env), type,
2298 env->watchpoint_hit->vaddr);
2299 env->watchpoint_hit = NULL;
2300 goto send_packet;
2301 }
2302 tb_flush(env);
2303 ret = GDB_SIGNAL_TRAP;
2304 break;
2305 case VMSTOP_USER:
2306 ret = GDB_SIGNAL_INT;
2307 break;
2308 case VMSTOP_SHUTDOWN:
2309 ret = GDB_SIGNAL_QUIT;
2310 break;
2311 case VMSTOP_DISKFULL:
2312 ret = GDB_SIGNAL_IO;
2313 break;
2314 case VMSTOP_WATCHDOG:
2315 ret = GDB_SIGNAL_ALRM;
2316 break;
2317 case VMSTOP_PANIC:
2318 ret = GDB_SIGNAL_ABRT;
2319 break;
2320 case VMSTOP_SAVEVM:
2321 case VMSTOP_LOADVM:
2322 return;
2323 case VMSTOP_MIGRATE:
2324 ret = GDB_SIGNAL_XCPU;
2325 break;
2326 default:
2327 ret = GDB_SIGNAL_UNKNOWN;
2328 break;
2329 }
2330 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2331
2332send_packet:
2333 put_packet(s, buf);
2334
2335
2336 cpu_single_step(env, 0);
2337}
2338#endif
2339
2340
2341
2342
2343
2344
2345void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2346{
2347 va_list va;
2348 char buf[256];
2349 char *p;
2350 target_ulong addr;
2351 uint64_t i64;
2352 GDBState *s;
2353
2354 s = gdbserver_state;
2355 if (!s)
2356 return;
2357 gdb_current_syscall_cb = cb;
2358 s->state = RS_SYSCALL;
2359#ifndef CONFIG_USER_ONLY
2360 vm_stop(VMSTOP_DEBUG);
2361#endif
2362 s->state = RS_IDLE;
2363 va_start(va, fmt);
2364 p = buf;
2365 *(p++) = 'F';
2366 while (*fmt) {
2367 if (*fmt == '%') {
2368 fmt++;
2369 switch (*fmt++) {
2370 case 'x':
2371 addr = va_arg(va, target_ulong);
2372 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2373 break;
2374 case 'l':
2375 if (*(fmt++) != 'x')
2376 goto bad_format;
2377 i64 = va_arg(va, uint64_t);
2378 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2379 break;
2380 case 's':
2381 addr = va_arg(va, target_ulong);
2382 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2383 addr, va_arg(va, int));
2384 break;
2385 default:
2386 bad_format:
2387 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2388 fmt - 1);
2389 break;
2390 }
2391 } else {
2392 *(p++) = *(fmt++);
2393 }
2394 }
2395 *p = 0;
2396 va_end(va);
2397 put_packet(s, buf);
2398#ifdef CONFIG_USER_ONLY
2399 gdb_handlesig(s->c_cpu, 0);
2400#else
2401 cpu_exit(s->c_cpu);
2402#endif
2403}
2404
2405static void gdb_read_byte(GDBState *s, int ch)
2406{
2407 int i, csum;
2408 uint8_t reply;
2409
2410#ifndef CONFIG_USER_ONLY
2411 if (s->last_packet_len) {
2412
2413
2414 if (ch == '-') {
2415#ifdef DEBUG_GDB
2416 printf("Got NACK, retransmitting\n");
2417#endif
2418 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2419 }
2420#ifdef DEBUG_GDB
2421 else if (ch == '+')
2422 printf("Got ACK\n");
2423 else
2424 printf("Got '%c' when expecting ACK/NACK\n", ch);
2425#endif
2426 if (ch == '+' || ch == '$')
2427 s->last_packet_len = 0;
2428 if (ch != '$')
2429 return;
2430 }
2431 if (vm_running) {
2432
2433
2434 vm_stop(VMSTOP_USER);
2435 } else
2436#endif
2437 {
2438 switch(s->state) {
2439 case RS_IDLE:
2440 if (ch == '$') {
2441 s->line_buf_index = 0;
2442 s->state = RS_GETLINE;
2443 }
2444 break;
2445 case RS_GETLINE:
2446 if (ch == '#') {
2447 s->state = RS_CHKSUM1;
2448 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2449 s->state = RS_IDLE;
2450 } else {
2451 s->line_buf[s->line_buf_index++] = ch;
2452 }
2453 break;
2454 case RS_CHKSUM1:
2455 s->line_buf[s->line_buf_index] = '\0';
2456 s->line_csum = fromhex(ch) << 4;
2457 s->state = RS_CHKSUM2;
2458 break;
2459 case RS_CHKSUM2:
2460 s->line_csum |= fromhex(ch);
2461 csum = 0;
2462 for(i = 0; i < s->line_buf_index; i++) {
2463 csum += s->line_buf[i];
2464 }
2465 if (s->line_csum != (csum & 0xff)) {
2466 reply = '-';
2467 put_buffer(s, &reply, 1);
2468 s->state = RS_IDLE;
2469 } else {
2470 reply = '+';
2471 put_buffer(s, &reply, 1);
2472 s->state = gdb_handle_packet(s, s->line_buf);
2473 }
2474 break;
2475 default:
2476 abort();
2477 }
2478 }
2479}
2480
2481
2482void gdb_exit(CPUState *env, int code)
2483{
2484 GDBState *s;
2485 char buf[4];
2486
2487 s = gdbserver_state;
2488 if (!s) {
2489 return;
2490 }
2491#ifdef CONFIG_USER_ONLY
2492 if (gdbserver_fd < 0 || s->fd < 0) {
2493 return;
2494 }
2495#endif
2496
2497 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2498 put_packet(s, buf);
2499
2500#ifndef CONFIG_USER_ONLY
2501 if (s->chr) {
2502 qemu_chr_close(s->chr);
2503 }
2504#endif
2505}
2506
2507#ifdef CONFIG_USER_ONLY
2508int
2509gdb_queuesig (void)
2510{
2511 GDBState *s;
2512
2513 s = gdbserver_state;
2514
2515 if (gdbserver_fd < 0 || s->fd < 0)
2516 return 0;
2517 else
2518 return 1;
2519}
2520
2521int
2522gdb_handlesig (CPUState *env, int sig)
2523{
2524 GDBState *s;
2525 char buf[256];
2526 int n;
2527
2528 s = gdbserver_state;
2529 if (gdbserver_fd < 0 || s->fd < 0)
2530 return sig;
2531
2532
2533 cpu_single_step(env, 0);
2534 tb_flush(env);
2535
2536 if (sig != 0)
2537 {
2538 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2539 put_packet(s, buf);
2540 }
2541
2542
2543 if (s->fd < 0)
2544 return sig;
2545
2546 sig = 0;
2547 s->state = RS_IDLE;
2548 s->running_state = 0;
2549 while (s->running_state == 0) {
2550 n = read (s->fd, buf, 256);
2551 if (n > 0)
2552 {
2553 int i;
2554
2555 for (i = 0; i < n; i++)
2556 gdb_read_byte (s, buf[i]);
2557 }
2558 else if (n == 0 || errno != EAGAIN)
2559 {
2560
2561
2562 return sig;
2563 }
2564 }
2565 sig = s->signal;
2566 s->signal = 0;
2567 return sig;
2568}
2569
2570
2571void gdb_signalled(CPUState *env, int sig)
2572{
2573 GDBState *s;
2574 char buf[4];
2575
2576 s = gdbserver_state;
2577 if (gdbserver_fd < 0 || s->fd < 0)
2578 return;
2579
2580 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2581 put_packet(s, buf);
2582}
2583
2584static void gdb_accept(void)
2585{
2586 GDBState *s;
2587 struct sockaddr_in sockaddr;
2588 socklen_t len;
2589 int val, fd;
2590
2591 for(;;) {
2592 len = sizeof(sockaddr);
2593 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2594 if (fd < 0 && errno != EINTR) {
2595 perror("accept");
2596 return;
2597 } else if (fd >= 0) {
2598#ifndef _WIN32
2599 fcntl(fd, F_SETFD, FD_CLOEXEC);
2600#endif
2601 break;
2602 }
2603 }
2604
2605
2606 val = 1;
2607 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2608
2609 s = qemu_mallocz(sizeof(GDBState));
2610 s->c_cpu = first_cpu;
2611 s->g_cpu = first_cpu;
2612 s->fd = fd;
2613 gdb_has_xml = 0;
2614
2615 gdbserver_state = s;
2616
2617 fcntl(fd, F_SETFL, O_NONBLOCK);
2618}
2619
2620static int gdbserver_open(int port)
2621{
2622 struct sockaddr_in sockaddr;
2623 int fd, val, ret;
2624
2625 fd = socket(PF_INET, SOCK_STREAM, 0);
2626 if (fd < 0) {
2627 perror("socket");
2628 return -1;
2629 }
2630#ifndef _WIN32
2631 fcntl(fd, F_SETFD, FD_CLOEXEC);
2632#endif
2633
2634
2635 val = 1;
2636 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2637
2638 sockaddr.sin_family = AF_INET;
2639 sockaddr.sin_port = htons(port);
2640 sockaddr.sin_addr.s_addr = 0;
2641 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2642 if (ret < 0) {
2643 perror("bind");
2644 return -1;
2645 }
2646 ret = listen(fd, 0);
2647 if (ret < 0) {
2648 perror("listen");
2649 return -1;
2650 }
2651 return fd;
2652}
2653
2654int gdbserver_start(int port)
2655{
2656 gdbserver_fd = gdbserver_open(port);
2657 if (gdbserver_fd < 0)
2658 return -1;
2659
2660 gdb_accept();
2661 return 0;
2662}
2663
2664
2665void gdbserver_fork(CPUState *env)
2666{
2667 GDBState *s = gdbserver_state;
2668 if (gdbserver_fd < 0 || s->fd < 0)
2669 return;
2670 close(s->fd);
2671 s->fd = -1;
2672 cpu_breakpoint_remove_all(env, BP_GDB);
2673 cpu_watchpoint_remove_all(env, BP_GDB);
2674}
2675#else
2676static int gdb_chr_can_receive(void *opaque)
2677{
2678
2679
2680 return MAX_PACKET_LENGTH;
2681}
2682
2683static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2684{
2685 int i;
2686
2687 for (i = 0; i < size; i++) {
2688 gdb_read_byte(gdbserver_state, buf[i]);
2689 }
2690}
2691
2692static void gdb_chr_event(void *opaque, int event)
2693{
2694 switch (event) {
2695 case CHR_EVENT_OPENED:
2696 vm_stop(VMSTOP_USER);
2697 gdb_has_xml = 0;
2698 break;
2699 default:
2700 break;
2701 }
2702}
2703
2704static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2705{
2706 char buf[MAX_PACKET_LENGTH];
2707
2708 buf[0] = 'O';
2709 if (len > (MAX_PACKET_LENGTH/2) - 1)
2710 len = (MAX_PACKET_LENGTH/2) - 1;
2711 memtohex(buf + 1, (uint8_t *)msg, len);
2712 put_packet(s, buf);
2713}
2714
2715static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2716{
2717 const char *p = (const char *)buf;
2718 int max_sz;
2719
2720 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2721 for (;;) {
2722 if (len <= max_sz) {
2723 gdb_monitor_output(gdbserver_state, p, len);
2724 break;
2725 }
2726 gdb_monitor_output(gdbserver_state, p, max_sz);
2727 p += max_sz;
2728 len -= max_sz;
2729 }
2730 return len;
2731}
2732
2733#ifndef _WIN32
2734static void gdb_sigterm_handler(int signal)
2735{
2736 if (vm_running) {
2737 vm_stop(VMSTOP_USER);
2738 }
2739}
2740#endif
2741
2742int gdbserver_start(const char *device)
2743{
2744 GDBState *s;
2745 char gdbstub_device_name[128];
2746 CharDriverState *chr = NULL;
2747 CharDriverState *mon_chr;
2748
2749 if (!device)
2750 return -1;
2751 if (strcmp(device, "none") != 0) {
2752 if (strstart(device, "tcp:", NULL)) {
2753
2754 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2755 "%s,nowait,nodelay,server", device);
2756 device = gdbstub_device_name;
2757 }
2758#ifndef _WIN32
2759 else if (strcmp(device, "stdio") == 0) {
2760 struct sigaction act;
2761
2762 memset(&act, 0, sizeof(act));
2763 act.sa_handler = gdb_sigterm_handler;
2764 sigaction(SIGINT, &act, NULL);
2765 }
2766#endif
2767 chr = qemu_chr_open("gdb", device, NULL);
2768 if (!chr)
2769 return -1;
2770
2771 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2772 gdb_chr_event, NULL);
2773 }
2774
2775 s = gdbserver_state;
2776 if (!s) {
2777 s = qemu_mallocz(sizeof(GDBState));
2778 gdbserver_state = s;
2779
2780 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2781
2782
2783 mon_chr = qemu_mallocz(sizeof(*mon_chr));
2784 mon_chr->chr_write = gdb_monitor_write;
2785 monitor_init(mon_chr, 0);
2786 } else {
2787 if (s->chr)
2788 qemu_chr_close(s->chr);
2789 mon_chr = s->mon_chr;
2790 memset(s, 0, sizeof(GDBState));
2791 }
2792 s->c_cpu = first_cpu;
2793 s->g_cpu = first_cpu;
2794 s->chr = chr;
2795 s->state = chr ? RS_IDLE : RS_INACTIVE;
2796 s->mon_chr = mon_chr;
2797
2798 return 0;
2799}
2800#endif
2801
